mod
;x0=dividend, x1=divisor
udiv x2,x0,x1
msub x3,x2,x1,x0
;x2=quotient, x3=remainder

abs - absolute value - computes the absolute value of the signed integer value in the source register, and writes the result to the destination register.
.101101011000000001000..........
f S        code2opcodeRn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

adc - add with carry - adds two register values and the Carry flag value, and writes the result to the destination register.
.0011010000.....000000..........
fpS        Rm         Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

adcs - add with carry, setting flags - adds two register values and the Carry flag value, and writes the result to the destination register. It updates the condition flags based on the result.
.0111010000.....000000..........
fpS        Rm         Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

add (extended register) - add extended and scaled register - adds a register value and a sign or zero-extended register value, followed by an optional left shift amount, and writes the result to the destination register. The argument that is extended from the <Rm> register can be a byte, halfword, word, or doubleword.
.0001011001.....................
fpS     pt Rm   ionmm3Rn   Rd   
 <Wd|WSP>:32-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Wn|WSP>:32-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <extend>
 option | <extend>
 000 | UXTB
 001 | UXTH
 010 | LSL|UXTW
 011 | UXTX
 100 | SXTB
 101 | SXTH
 110 | SXTW
 111 | SXTX
 If "Rd" or "Rn" is '11111' (WSP) and "option" is '010' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTW when "option" is '010'.
 <extend>
 option | <extend>
 000 | UXTB
 001 | UXTH
 010 | UXTW
 011 | LSL|UXTX
 100 | SXTB
 101 | SXTH
 110 | SXTW
 111 | SXTX
 If "Rd" or "Rn" is '11111' (SP) and "option" is '011' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTX when "option" is '011'.
 <amount>:left shift amount to be applied after extension in the range 0 to 4, defaulting to 0, encoded in the "imm3" field. It must be absent when <extend> is absent, is required when <extend> is LSL, and is optional when <extend> is present but not LSL.
 <Xd|SP>:64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <R>
 option | <R>
 00x | W
 010 | W
 x11 | X
 10x | W
 110 | W
 <m>:number [0-30] of the second general-purpose source register or the name ZR (31), encoded in the "Rm" field.

add (immediate) - add immediate value - adds a register value and an optionally-shifted immediate value, and writes the result to the destination register.
.00100010.......................
fpS      himm12       Rn   Rd   
 <Wd|WSP>:32-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Wn|WSP>:32-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.
 <imm>:Is an unsigned immediate, in the range 0 to 4095, encoded in the "imm12" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #12
 <Xd|SP>:64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.

add (shifted register) - add optionally-shifted register - adds a register value and an optionally-shifted register value, and writes the result to the destination register.
.0001011..0.....................
fpS     ft Rm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | RESERVED
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

addg - add with tag - adds an immediate value scaled by the Tag Granule to the address in the source register, modifies the Logical Address Tag of the address using an immediate value, and writes the result to the destination register. Tags specified in GCR_EL1.Exclude are excluded from the possible outputs when modifying the Logical Address Tag.
1001000110......00..............
fpS       imm6  p3imm4Rn   Rd   
 <Xd|SP>:64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.
 <uimm6>:Is an unsigned immediate, a multiple of 16 in the range 0 to 1008, encoded in the "imm6" field.
 <uimm4>:Is an unsigned immediate, in the range 0 to 15, encoded in the "imm4" field.

addpt - add checked pointer - adds a base address register value and an optionally-shifted register value, and writes the result to the destination register. The optionally-shifted register value is treated as the offset. If the operation would have generated a result where the most significant 8 bits of the result register differ from the most significant 8 bits of the base register, then the result is modified such that it is likely to be non-canonical when used as an address.
10011010000.....001.............
fpS        Rm      mm3Rn   Rd   
 <Xd|SP>:64-bit name of the general-purpose destination register or stack pointer, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the first general-purpose source register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <amount>:left shift amount, in the range 0 to 7, defaulting to 0, encoded in the "imm3" field.

adds (extended register) - add extended and scaled register, setting flags - adds a register value and a sign or zero-extended register value, followed by an optional left shift amount, and writes the result to the destination register. The argument that is extended from the <Rm> register can be a byte, halfword, word, or doubleword. It updates the condition flags based on the result.
.0101011001.....................
fpS     pt Rm   ionmm3Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn|WSP>:32-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <extend>
 option | <extend>
 000 | UXTB
 001 | UXTH
 010 | LSL|UXTW
 011 | UXTX
 100 | SXTB
 101 | SXTH
 110 | SXTW
 111 | SXTX
 If "Rn" is '11111' (WSP) and "option" is '010' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTW when "option" is '010'.
 <extend>
 option | <extend>
 000 | UXTB
 001 | UXTH
 010 | UXTW
 011 | LSL|UXTX
 100 | SXTB
 101 | SXTH
 110 | SXTW
 111 | SXTX
 If "Rn" is '11111' (SP) and "option" is '011' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTX when "option" is '011'.
 <amount>:left shift amount to be applied after extension in the range 0 to 4, defaulting to 0, encoded in the "imm3" field. It must be absent when <extend> is absent, is required when <extend> is LSL, and is optional when <extend> is present but not LSL.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <R>
 option | <R>
 00x | W
 010 | W
 x11 | X
 10x | W
 110 | W
 <m>:number [0-30] of the second general-purpose source register or the name ZR (31), encoded in the "Rm" field.

adds (immediate) - add immediate value, setting flags - adds a register value and an optionally-shifted immediate value, and writes the result to the destination register. It updates the condition flags based on the result.
.01100010.......................
fpS      himm12       Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn|WSP>:32-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.
 <imm>:Is an unsigned immediate, in the range 0 to 4095, encoded in the "imm12" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #12
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.

adds (shifted register) - add optionally-shifted register, setting flags - adds a register value and an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.
.0101011..0.....................
fpS     ft Rm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | RESERVED
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

adr - form pc-relative address - adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register.
0..10000........................
plo     immhi              Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <label>:program label whose address is to be calculated. Its offset from the address of this instruction, in the range +/-1MB, is encoded in "immhi:immlo".

adrp - form pc-relative address to 4kb page - adds an immediate value that is shifted left by 12 bits, to the PC value to form a PC-relative address, with the bottom 12 bits masked out, and writes the result to the destination register.
1..10000........................
plo     immhi              Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <label>:program label whose 4KB page address is to be calculated. Its offset from the page address of this instruction, in the range +/-4GB, is encoded as "immhi:immlo" times 4096.

and (immediate) - bitwise and (immediate) - performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register.
.00100100.......................
fpc      Nimmr  imms  Rn   Rd   
 <Wd|WSP>:32-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <imm>:For the "32-bit" variant: is the bitmask immediate, encoded in "imms:immr".
 <imm>:For the "64-bit" variant: is the bitmask immediate, encoded in "N:imms:immr".
 <Xd|SP>:64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

and (shifted register) - bitwise and (shifted register) - performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register.
.0001010..0.....................
fpc     ftNRm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | ROR
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

ands (immediate) - bitwise and (immediate), setting flags - performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register. It updates the condition flags based on the result.
.11100100.......................
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <imm>:For the "32-bit" variant: is the bitmask immediate, encoded in "imms:immr".
 <imm>:For the "64-bit" variant: is the bitmask immediate, encoded in "N:imms:immr".
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

ands (shifted register) - bitwise and (shifted register), setting flags - performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.
.1101010..0.....................
fpc     ftNRm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | ROR
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

apas - associate physical address space - associates a physical address space with a memory-mapped location that is protected by a memory-side physical address space filter.
110101010000111001110000000.....
          L  op1CRn CRm op2Rt   
 <Xt>:64-bit name of the general-purpose source register, encoded in the "Rt" field.

asr (immediate) - arithmetic shift right (immediate) - shifts a register value right by an immediate number of bits, shifting in copies of the sign bit in the upper bits and zeros in the lower bits, and writes the result to the destination register.
.00100110.......x11111..........
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <shift>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, encoded in the "immr" field.
 <shift>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, encoded in the "immr" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

asr (register) - arithmetic shift right (register) - shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The value of the second source register modulo the register size in bits gives the number of bits by which the first source register is right-shifted.
.0011010110.....001010..........
f S        Rm       p2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits, encoded in the "Rm" field.

asrv - arithmetic shift right variable - shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The value of the second source register modulo the register size in bits gives the number of bits by which the first source register is right-shifted.
.0011010110.....001010..........
f S        Rm       p2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits, encoded in the "Rm" field.

at - address translate - For more information, see op0==0b01, cache maintenance, TLB maintenance, and address translation instructions.
1101010100001...0111100x........
          L  op1CRn CRm op2Rt   
 <at_op>
 op1 | CRm | op2 | <at_op> | Architectural Feature
 000 | 1000 | 000 | S1E1R | 
 000 | 1000 | 001 | S1E1W | 
 000 | 1000 | 010 | S1E0R | 
 000 | 1000 | 011 | S1E0W | 
 000 | 1001 | 000 | S1E1RP | 
                  
 000 | 1001 | 001 | S1E1WP | 
                  
 000 | 1001 | 010 | S1E1A | 
                  
 100 | 1000 | 000 | S1E2R | 
 100 | 1000 | 001 | S1E2W | 
 100 | 1000 | 100 | S12E1R | 
 100 | 1000 | 101 | S12E1W | 
 100 | 1000 | 110 | S12E0R | 
 100 | 1000 | 111 | S12E0W | 
 100 | 1001 | 010 | S1E2A | 
                  
 110 | 1000 | 000 | S1E3R | 
 110 | 1000 | 001 | S1E3W | 
 110 | 1001 | 010 | S1E3A | 
                  
 <Xt>:64-bit name of the general-purpose source register, encoded in the "Rt" field.

autda, autdza - authenticate data address, using key a - authenticates a data address, using a modifier and key A. The address is in the general-purpose register that is specified by <Xd>. The modifier is: If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. For information on behavior if the authentication fails, see Faulting on pointer authentication.
110110101100000100.110..........
f S        code2  Z   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.

autdb, autdzb - authenticate data address, using key b - authenticates a data address, using a modifier and key B. The address is in the general-purpose register that is specified by <Xd>. The modifier is: If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. For information on behavior if the authentication fails, see Faulting on pointer authentication.
110110101100000100.111..........
f S        code2  Z   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.

autia, autia1716, autiasp, autiaz, autiza - authenticate instruction address, using key a - authenticates an instruction address, using a modifier and key A. If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. For information on behavior if the authentication fails, see Faulting on pointer authentication. The address is: The modifier is: If FEAT_PAuth_LR is implemented and PSTATE.PACM is 1, then AUTIA1716 and AUTIASP include a second modifier that is:
110110101100000100.100..........
f S        code2  Z   Rn   Rd   
1101010100000011001000x110x11111
                    CRm op2     
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.

autia171615 - authenticate instruction address, using key a - authenticates an instruction address, using two modifiers and key A. The address is in X17. The 64-bit value of modifier1 is the value in X16. The 64-bit value of modifier2 is the value in X15. If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. For information on behavior if the authentication fails, see Faulting on pointer authentication.
11011010110000011011101111111110
f S        code2opcodeRn   Rd   


autiasppc - authenticate return address using key a, using an immediate offset - authenticates an instruction address, using two modifiers and key A. If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. For information on behavior if the authentication fails, see Faulting on pointer authentication. The address is in X30. The first modifier is in SP. The second modifier is the address of a program label.
11110011100................11111
f        pcimm16           Rd   
 <label>:program label whose address is to be calculated. Its negative offset from the address of this instruction, a multiple of 4 in the range -262140 to 0, is encoded as an unsigned value in the "imm16" field as <label>/4.

autiasppcr - authenticate return address using key a, using a register - authenticates an instruction address, using two modifiers and key A. If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. For information on behavior if the authentication fails, see Faulting on pointer authentication. The address is in X30. The first modifier is in SP. The second modifier is in the general-purpose register that is specified by <Xn>.
1101101011000001100100.....11110
f S        code2opcodeRn   Rd   
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

autib, autib1716, autibsp, autibz, autizb - authenticate instruction address, using key b - authenticates an instruction address, using a modifier and key B. If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. For information on behavior if the authentication fails, see Faulting on pointer authentication. The address is: The modifier is: If FEAT_PAuth_LR is implemented and PSTATE.PACM is 1, then AUTIB1716 and AUTIBSP include a second modifier that is:
110110101100000100.101..........
f S        code2  Z   Rn   Rd   
1101010100000011001000x111x11111
                    CRm op2     
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.

autib171615 - authenticate instruction address, using key b - authenticates an instruction address, using two modifiers and key B. The address is in X17. The 64-bit value of modifier1 is the value in X16. The 64-bit value of modifier2 is the value in X15. If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. For information on behavior if the authentication fails, see Faulting on pointer authentication.
11011010110000011011111111111110
f S        code2opcodeRn   Rd   


autibsppc - authenticate return address using key b, using an immediate offset - authenticates an instruction address, using two modifiers and key B. If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. For information on behavior if the authentication fails, see Faulting on pointer authentication. The address is in X30. The first modifier is in SP. The second modifier is the address of a program label.
11110011101................11111
f        pcimm16           Rd   
 <label>:program label whose address is to be calculated. Its negative offset from the address of this instruction, a multiple of 4 in the range -262140 to 0, is encoded as an unsigned value in the "imm16" field as <label>/4.

autibsppcr - authenticate return address using key b, using a register - authenticates an instruction address, using two modifiers and key B. If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. For information on behavior if the authentication fails, see Faulting on pointer authentication. The address is in X30. The first modifier is in SP. The second modifier is in the general-purpose register that is specified by <Xn>.
1101101011000001100101.....11110
f S        code2opcodeRn   Rd   
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

axflag - convert floating-point condition flags from arm to external format - converts the state of the PSTATE.{N,Z,C,V} flags from a form representing the result of an Arm floating-point scalar compare instruction to an alternative representation required by some software.
11010101000000000100000001011111
             op1    CRm op2Rt   


b - branch - branches unconditionally to a label at a PC-relative offset, with a hint that this is not a subroutine call or return.
000101..........................
p     imm26                     
 <label>:program label to be unconditionally branched to. Its offset from the address of this instruction, in the range +/-128MB, is encoded as "imm26" times 4.

b.cond - branch conditionally - branches conditionally to a label at a PC-relative offset, with a hint that this is not a subroutine call or return.
01010100...................0....
        imm19              0cond
 <cond>
 cond | <cond>
 0000 | EQ
 0001 | NE
 0010 | CS
 0011 | CC
 0100 | MI
 0101 | PL
 0110 | VS
 0111 | VC
 1000 | HI
 1001 | LS
 1010 | GE
 1011 | LT
 1100 | GT
 1101 | LE
 1110 | AL
 1111 | NV
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.

bc.cond - branch consistent conditionally - branches conditionally to a label at a PC-relative offset, with a hint that this branch will behave very consistently and is very unlikely to change direction.
01010100...................1....
        imm19              0cond
 <cond>
 cond | <cond>
 0000 | EQ
 0001 | NE
 0010 | CS
 0011 | CC
 0100 | MI
 0101 | PL
 0110 | VS
 0111 | VC
 1000 | HI
 1001 | LS
 1010 | GE
 1011 | LT
 1100 | GT
 1101 | LE
 1110 | AL
 1111 | NV
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.

bfc - bitfield clear - sets a bitfield of <width> bits at bit position <lsb> of the destination register to zero, leaving the other destination bits unchanged.
.01100110.............11111.....
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <lsb>:For the "32-bit" variant: is the bit number of the lsb of the destination bitfield, in the range 0 to 31.
 <lsb>:For the "64-bit" variant: is the bit number of the lsb of the destination bitfield, in the range 0 to 63.
 <width>:For the "32-bit" variant: is the width of the bitfield, in the range 1 to 32-<lsb>.
 <width>:For the "64-bit" variant: is the width of the bitfield, in the range 1 to 64-<lsb>.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.

bfi - bitfield insert - copies a bitfield of <width> bits from the least significant bits of the source register to bit position <lsb> of the destination register, leaving the other destination bits unchanged.
.01100110.............!= 11111!= 11111!= 11111!= 11111!= 11111.....
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <lsb>:For the "32-bit" variant: is the bit number of the lsb of the destination bitfield, in the range 0 to 31.
 <lsb>:For the "64-bit" variant: is the bit number of the lsb of the destination bitfield, in the range 0 to 63.
 <width>:For the "32-bit" variant: is the width of the bitfield, in the range 1 to 32-<lsb>.
 <width>:For the "64-bit" variant: is the width of the bitfield, in the range 1 to 64-<lsb>.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

bfm - bitfield move - is usually accessed via one of its aliases, which are always preferred for disassembly. If <imms> is greater than or equal to <immr>, this copies a bitfield of (<imms>-<immr>+1) bits starting from bit position <immr> in the source register to the least significant bits of the destination register. If <imms> is less than <immr>, this copies a bitfield of (<imms>+1) bits from the least significant bits of the source register to bit position (regsize-<immr>) of the destination register, where regsize is the destination register size of 32 or 64 bits. In both cases, the other bits of the destination register remain unchanged.
.01100110.......................
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <immr>:For the "32-bit" variant: is the right rotate amount, in the range 0 to 31, encoded in the "immr" field.
 <immr>:For the "64-bit" variant: is the right rotate amount, in the range 0 to 63, encoded in the "immr" field.
 <imms>:For the "32-bit" variant: is the leftmost bit number to be moved from the source, in the range 0 to 31, encoded in the "imms" field.
 <imms>:For the "64-bit" variant: is the leftmost bit number to be moved from the source, in the range 0 to 63, encoded in the "imms" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

bfxil - bitfield extract and insert at low end - copies a bitfield of <width> bits starting from bit position <lsb> in the source register to the least significant bits of the destination register, leaving the other destination bits unchanged.
.01100110.......................
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <lsb>:For the "32-bit" variant: is the bit number of the lsb of the source bitfield, in the range 0 to 31.
 <lsb>:For the "64-bit" variant: is the bit number of the lsb of the source bitfield, in the range 0 to 63.
 <width>:For the "32-bit" variant: is the width of the bitfield, in the range 1 to 32-<lsb>.
 <width>:For the "64-bit" variant: is the width of the bitfield, in the range 1 to 64-<lsb>.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

bic (shifted register) - bitwise bit clear (shifted register) - performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register.
.0001010..1.....................
fpc     ftNRm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | ROR
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

bics (shifted register) - bitwise bit clear (shifted register), setting flags - performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.
.1101010..1.....................
fpc     ftNRm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | ROR
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

bl - branch with link - branches to a PC-relative offset, setting register X30 to PC+4. It provides a hint that this is a subroutine call.
100101..........................
p     imm26                     
 <label>:program label to be unconditionally branched to. Its offset from the address of this instruction, in the range +/-128MB, is encoded as "imm26" times 4.

blr - branch with link to register - calls a subroutine at an address in a register, setting register X30 to PC+4.
1101011000111111000000.....00000
       Z opop2      AMRn   Rm   
 <Xn>:64-bit name of the general-purpose register holding the address to be branched to, encoded in the "Rn" field.

blraa, blraaz, blrab, blrabz - branch with link to register, with pointer authentication - authenticates the address in the general-purpose register that is specified by <Xn>, using a modifier and the specified key, and calls a subroutine at the authenticated address, setting register X30 to PC+4. The modifier is: Key A is used for BLRAA and BLRAAZ. Key B is used for BLRAB and BLRABZ. If the authentication passes, the PE continues execution at the target of the branch. For information on behavior if the authentication fails, see Faulting on pointer authentication. The authenticated address is not written back to the general-purpose register.
1101011.0011111100001...........
       Z opop2      AMRn   Rm   
 <Xn>:64-bit name of the general-purpose register holding the address to be branched to, encoded in the "Rn" field.
 <Xm|SP>:64-bit name of the general-purpose source register or stack pointer holding the modifier, encoded in the "Rm" field.

br - branch to register - branches unconditionally to an address in a register, with a hint that this is not a subroutine return.
1101011000011111000000.....00000
       Z opop2      AMRn   Rm   
 <Xn>:64-bit name of the general-purpose register holding the address to be branched to, encoded in the "Rn" field.

braa, braaz, brab, brabz - branch to register, with pointer authentication - authenticates the address in the general-purpose register that is specified by <Xn>, using a modifier and the specified key, and branches to the authenticated address. The modifier is: Key A is used for BRAA and BRAAZ. Key B is used for BRAB and BRABZ. If the authentication passes, the PE continues execution at the target of the branch. For information on behavior if the authentication fails, see Faulting on pointer authentication. The authenticated address is not written back to the general-purpose register.
1101011.0001111100001...........
       Z opop2      AMRn   Rm   
 <Xn>:64-bit name of the general-purpose register holding the address to be branched to, encoded in the "Rn" field.
 <Xm|SP>:64-bit name of the general-purpose source register or stack pointer holding the modifier, encoded in the "Rm" field.

brb - branch record buffer - For more information, see op0==0b01, cache maintenance, TLB maintenance, and address translation instructions.
110101010000100101110010........
          L  op1CRn CRm op2Rt   
 <brb_op>
 op2 | <brb_op> | Architectural Feature
 100 | IALL | 
                  
 101 | INJ | 
                  

brk - breakpoint instruction - generates a Breakpoint Instruction exception. The PE records the exception in ESR_ELx, using the EC value 0x3C, and captures the value of the immediate argument in ESR_ELx.ISS. Within a guarded memory region, while PSTATE.BTYPE != 0b00, a BRK instruction will not generate a Branch Target exception and will generate a Breakpoint Instruction exception as normal. For more information, see PSTATE.BTYPE.
11010100001................00000
        opcimm16           op2LL
 <imm>:Is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm16" field.

bti - branch target identification - is used to guard against the execution of instructions that are not the intended target of a branch. Outside of a guarded memory region, a BTI instruction executes as a NOP. Within a guarded memory region, while PSTATE.BTYPE != 0b00, a BTI instruction compatible with the current value of PSTATE.BTYPE will not generate a Branch Target Exception and will allow execution of subsequent instructions within the memory region. For more information, see PSTATE.BTYPE. The operand <targets> passed to a BTI instruction determines the values of PSTATE.BTYPE that the BTI instruction is compatible with.
110101010000001100100100xx011111
                    CRm op2     
 <targets>
 op2<2:1> | <targets>
 00 | [absent]
 01 | c
 10 | j
 11 | jc

cas, casa, casal, casl - compare and swap word or doubleword in memory - reads a 32-bit word or 64-bit doubleword from memory, and compares it against the value held in a first register. If the comparison is equal, the value in a second register is written to memory. If the comparison is not equal, the architecture permits writing the value read from the location to memory. If the write is performed, the read and write occur atomically such that no other modification of the memory location can take place between the read and write. The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails. If the instruction generates a synchronous Data Abort, the register which is compared and loaded, that is <Ws>, or <Xs>, is restored to the value held in the register before the instruction was executed. For a CAS or CASA instruction, when <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, this signals to the memory system that an additional subsequent CAS, CASA, CASAL, or CASL access to the specified location is likely to occur in the near future. The memory system can respond by taking actions that are expected to enable the subsequent CAS, CASA, CASAL, or CASL access to succeed when it does occur. A code sequence starting with a CAS or CASA instruction for which <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, and ending with a subsequent CAS, CASA, CASAL, or CASL to the same location, exhibits the following properties for best performance when the location may be accessed concurrently, on one or more other PEs: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1x0010001.1......11111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register to be compared and loaded, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be conditionally stored, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register to be compared and loaded, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be conditionally stored, encoded in the "Rt" field.

casb, casab, casalb, caslb - compare and swap byte in memory - reads an 8-bit byte from memory, and compares it against the value held in a first register. If the comparison is equal, the value in a second register is written to memory. If the comparison is not equal, the architecture permits writing the value read from the location to memory. If the write is performed, the read and write occur atomically such that no other modification of the memory location can take place between the read and write. The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails. If the instruction generates a synchronous Data Abort, the register which is compared and loaded, that is <Ws>, is restored to the values held in the register before the instruction was executed. For a CASB or CASAB instruction, when <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, this signals to the memory system that an additional subsequent CASB, CASAB, CASALB, or CASLB access to the specified location is likely to occur in the near future. The memory system can respond by taking actions that are expected to enable the subsequent CASB, CASAB, CASALB, or CASLB access to succeed when it does occur. A code sequence starting with a CASB or CASAB instruction for which <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, and ending with a subsequent CASB, CASAB, CASALB, or CASLB to the same location, exhibits the following properties for best performance when the location may be accessed concurrently, on one or more other PEs: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
000010001.1......11111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register to be compared and loaded, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be conditionally stored, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

cash, casah, casalh, caslh - compare and swap halfword in memory - reads a 16-bit halfword from memory, and compares it against the value held in a first register. If the comparison is equal, the value in a second register is written to memory. If the comparison is not equal, the architecture permits writing the value read from the location to memory. If the write is performed, the read and write occur atomically such that no other modification of the memory location can take place between the read and write. The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails. If the instruction generates a synchronous Data Abort, the register which is compared and loaded, that is <Ws>, is restored to the values held in the register before the instruction was executed. For a CASH or CASAH instruction, when <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, this signals to the memory system that an additional subsequent CASH, CASAH, CASALH, or CASLH access to the specified location is likely to occur in the near future. The memory system can respond by taking actions that are expected to enable the subsequent CASH, CASAH, CASALH, or CASLH access to succeed when it does occur. A code sequence starting with a CASH or CASAH instruction for which <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, and ending with a subsequent CASH, CASAH, CASALH, or CASLH to the same location, exhibits the following properties for best performance when the location may be accessed concurrently, on one or more other PEs: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
010010001.1......11111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register to be compared and loaded, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be conditionally stored, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

casp, caspa, caspal, caspl - compare and swap pair of words or doublewords in memory - reads a pair of 32-bit words or 64-bit doublewords from memory, and compares them against the values held in the first pair of registers. If the comparison is equal, the values in the second pair of registers are written to memory. If the comparison is not equal, the architecture permits writing the value read from the location to memory. If the writes are performed, the reads and writes occur atomically such that no other modification of the memory location can take place between the reads and writes. The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails. If the instruction generates a synchronous Data Abort, the registers which are compared and loaded, that is <Ws> and <W(s+1)>, or <Xs> and <X(s+1)>, are restored to the values held in the registers before the instruction was executed. For a CASP or CASPA instruction, when <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, this signals to the memory system that an additional subsequent CASP, CASPA, CASPAL, or CASPL access to the specified location is likely to occur in the near future. The memory system can respond by taking actions that are expected to enable the subsequent CASP, CASPA, CASPAL, or CASPL access to succeed when it does occur. A code sequence starting with a CASP or CASPA instruction for which <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, and ending with a subsequent CASP, CASPA, CASPAL, or CASPL to the same location, exhibits the following properties for best performance when the location may be accessed concurrently, on one or more other PEs: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
0.0010000.1......11111..........
 z       L Rs   0Rt2  Rn   Rt   
 <Ws>:32-bit name of the first general-purpose register to be compared and loaded, encoded in the "Rs" field. <Ws> must be an even-numbered register.
 <W(s+1)>:32-bit name of the second general-purpose register to be compared and loaded.
 <Wt>:32-bit name of the first general-purpose register to be conditionally stored, encoded in the "Rt" field. <Wt> must be an even-numbered register.
 <W(t+1)>:32-bit name of the second general-purpose register to be conditionally stored.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the first general-purpose register to be compared and loaded, encoded in the "Rs" field. <Xs> must be an even-numbered register.
 <X(s+1)>:64-bit name of the second general-purpose register to be compared and loaded.
 <Xt>:64-bit name of the first general-purpose register to be conditionally stored, encoded in the "Rt" field. <Xt> must be an even-numbered register.
 <X(t+1)>:64-bit name of the second general-purpose register to be conditionally stored.

caspt, caspat, caspalt, casplt - compare and swap pair unprivileged - reads a pair of 64-bit doublewords from memory, and compares them against the values held in the first pair of registers. If the comparison is equal, the values in the second pair of registers are written to memory. If the comparison is not equal, the architecture permits writing the value read from the location to memory. If the writes are performed, the reads and writes occur atomically such that no other modification of the memory location can take place between the reads and writes. The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails. If the instruction generates a synchronous Data Abort, the registers which are compared and loaded, that is <Xs> and <X(s+1)>, are restored to the values held in the registers before the instruction was executed. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For a CASPT or CASPAT instruction, when <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, this signals to the memory system that an additional subsequent CASPT, CASPAT, CASPALT, or CASPLT access to the specified location is likely to occur in the near future. The memory system can respond by taking actions that are expected to enable the subsequent CASPT, CASPAT, CASPALT, or CASPLT access to succeed when it does occur. A code sequence starting with a CASPT or CASPAT instruction for which <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, and ending with a subsequent CASPT, CASPAT, CASPALT, or CASPLT to the same location, exhibits the following properties for best performance when the location may be accessed concurrently, on one or more other PEs: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
010010011.0......11111..........
 z       L Rs   0Rt2  Rn   Rt   
 <Xs>:64-bit name of the first general-purpose register to be compared and loaded, encoded in the "Rs" field. <Xs> must be an even-numbered register.
 <X(s+1)>:64-bit name of the second general-purpose register to be compared and loaded.
 <Xt>:64-bit name of the first general-purpose register to be conditionally stored, encoded in the "Rt" field. <Xt> must be an even-numbered register.
 <X(t+1)>:64-bit name of the second general-purpose register to be conditionally stored.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

cast, casat, casalt, caslt - compare and swap unprivileged - reads a 64-bit doubleword from memory, and compares it against the value held in a first register. If the comparison is equal, the value in a second register is written to memory. If the comparison is not equal, the architecture permits writing the value read from the location to memory. If the write is performed, the read and write occur atomically such that no other modification of the memory location can take place between the read and write. The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails. If the instruction generates a synchronous Data Abort, the register which is compared and loaded, that is <Xs>, is restored to the value held in the register before the instruction was executed. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For a CAST or CASAT instruction, when <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, this signals to the memory system that an additional subsequent CAST, CASAT, CASALT, or CASLT access to the specified location is likely to occur in the near future. The memory system can respond by taking actions that are expected to enable the subsequent CAST, CASAT, CASALT, or CASLT access to succeed when it does occur. A code sequence starting with a CAST or CASAT instruction for which <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, and ending with a subsequent CAST, CASAT, CASALT, or CASLT to the same location, exhibits the following properties for best performance when the location may be accessed concurrently, on one or more other PEs: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
110010011.0......11111..........
 z       L Rs   0Rt2  Rn   Rt   
 <Xs>:64-bit name of the general-purpose register to be compared and loaded, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be conditionally stored, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

cb<cc> (immediate) - compare register with immediate and branch - compares the value in a register with an immediate, and conditionally branches to a label at a PC-relative offset if the comparison is true. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
.1110101.........0..............
f       cc imm6   imm9     Rt   
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <imm>:Is an unsigned immediate, in the range 0 to 63, encoded in the "imm6" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.
 <Xt>:64-bit name of the general-purpose register to be tested, encoded in the "Rt" field.

cb<cc> (register) - compare registers and branch - compares the values in two registers, and conditionally branches to a label at a PC-relative offset if the condition is true. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
.1110100........00..............
f       cc Rm     imm9     Rt   
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.
 <Xt>:64-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

cbb<cc> - compare bytes and branch - compares the byte values in two registers, and conditionally branches to a label at a PC-relative offset if the condition is true. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
01110100........10..............
        cc Rm    Himm9     Rt   
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.

cbble - compare signed less than or equal bytes and branch - compares the signed byte values in two registers, and conditionally branches to a label at a PC-relative offset if the second value is less than or equal to the first. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
01110100001.....10..............
        cc Rm    Himm9     Rt   
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.

cbblo - compare unsigned lower than bytes and branch - compares the unsigned byte values in two registers, and conditionally branches to a label at a PC-relative offset if the second value is lower than the first. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
01110100010.....10..............
        cc Rm    Himm9     Rt   
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.

cbbls - compare unsigned lower than or equal bytes and branch - compares the unsigned byte values in two registers, and conditionally branches to a label at a PC-relative offset if the second value is lower than or equal to the first. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
01110100011.....10..............
        cc Rm    Himm9     Rt   
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.

cbblt - compare signed less than bytes and branch - compares the signed byte values in two registers, and conditionally branches to a label at a PC-relative offset if the second value is less than the first. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
01110100000.....10..............
        cc Rm    Himm9     Rt   
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.

cbge (immediate) - compare signed greater than or equal immediate and branch - compares the signed value in a register with an immediate, and conditionally branches to a label at a PC-relative offset if the register value is greater than or equal to the immediate. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
.1110101000......0..............
f       cc imm6   imm9     Rt   
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <immp1>:Is an unsigned immediate, in the range 1 to 64, encoded as "imm6" plus 1.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.
 <Xt>:64-bit name of the general-purpose register to be tested, encoded in the "Rt" field.

cbh<cc> - compare halfwords and branch - compares the halfword values in two registers, and conditionally branches to a label at a PC-relative offset if the condition is true. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
01110100........11..............
        cc Rm    Himm9     Rt   
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.

cbhle - compare signed less than or equal halfwords and branch - compares the signed halfword values in two registers, and conditionally branches to a label at a PC-relative offset if the second value is less than or equal to the first. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
01110100001.....11..............
        cc Rm    Himm9     Rt   
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.

cbhlo - compare unsigned lower than halfwords and branch - compares the unsigned halfword values in two registers, and conditionally branches to a label at a PC-relative offset if the second value is lower than the first. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
01110100010.....11..............
        cc Rm    Himm9     Rt   
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.

cbhls - compare unsigned lower than or equal halfwords and branch - compares the unsigned halfword values in two registers, and conditionally branches to a label at a PC-relative offset if the second value is lower than or equal to the first. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
01110100011.....11..............
        cc Rm    Himm9     Rt   
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.

cbhlt - compare signed less than halfwords and branch - compares the signed halfword values in two registers, and conditionally branches to a label at a PC-relative offset if the second value is less than the first. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
01110100000.....11..............
        cc Rm    Himm9     Rt   
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.

cbhs (immediate) - compare unsigned greater than or equal immediate and branch - compares the unsigned value in a register with an immediate, and conditionally branches to a label at a PC-relative offset if the register value is greater than or equal to the immediate. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
.1110101010......0..............
f       cc imm6   imm9     Rt   
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <immp1>:Is an unsigned immediate, in the range 1 to 64, encoded as "imm6" plus 1.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.
 <Xt>:64-bit name of the general-purpose register to be tested, encoded in the "Rt" field.

cble (immediate) - compare signed less than or equal immediate and branch - compares the signed value in a register with an immediate, and conditionally branches to a label at a PC-relative offset if the register value is less than or equal to the immediate. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
.1110101001......0..............
f       cc imm6   imm9     Rt   
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <imms1>:Is a signed immediate, in the range -1 to 62, encoded as "imm6" minus 1.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.
 <Xt>:64-bit name of the general-purpose register to be tested, encoded in the "Rt" field.

cble (register) - compare signed less than or equal register and branch - compares the signed values in two registers, and conditionally branches to a label at a PC-relative offset if the second value is less than or equal to the first. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
.1110100001.....00..............
f       cc Rm     imm9     Rt   
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Xt>:64-bit name of the general-purpose register to be tested, encoded in the "Rt" field.

cblo (register) - compare unsigned lower than register and branch - compares the unsigned values in two registers, and conditionally branches to a label at a PC-relative offset if the second value is lower than the first. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
.1110100010.....00..............
f       cc Rm     imm9     Rt   
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Xt>:64-bit name of the general-purpose register to be tested, encoded in the "Rt" field.

cbls (immediate) - compare unsigned lower than or equal immediate and branch - compares the unsigned value in a register with an immediate, and conditionally branches to a label at a PC-relative offset if the register value is lower than or equal to the immediate. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
.1110101011......0..............
f       cc imm6   imm9     Rt   
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <imms1>:Is a signed immediate, in the range -1 to 62, encoded as "imm6" minus 1.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.
 <Xt>:64-bit name of the general-purpose register to be tested, encoded in the "Rt" field.

cbls (register) - compare unsigned lower than or equal register and branch - compares the unsigned values in two registers, and conditionally branches to a label at a PC-relative offset if the second value is lower than or equal to the first. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
.1110100011.....00..............
f       cc Rm     imm9     Rt   
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Xt>:64-bit name of the general-purpose register to be tested, encoded in the "Rt" field.

cblt (register) - compare signed less than register and branch - compares the signed values in two registers, and conditionally branches to a label at a PC-relative offset if the second value is less than the first. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
.1110100000.....00..............
f       cc Rm     imm9     Rt   
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Xt>:64-bit name of the general-purpose register to be tested, encoded in the "Rt" field.

cbnz - compare and branch on nonzero - compares the value in a register with zero, and conditionally branches to a label at a PC-relative offset if the comparison is not equal. It provides a hint that this is not a subroutine call or return. does not affect the condition flags.
.0110101........................
f      pimm19              Rt   
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.
 <Xt>:64-bit name of the general-purpose register to be tested, encoded in the "Rt" field.

cbz - compare and branch on zero - compares the value in a register with zero, and conditionally branches to a label at a PC-relative offset if the comparison is equal. It provides a hint that this is not a subroutine call or return. does not affect condition flags.
.0110100........................
f      pimm19              Rt   
 <Wt>:32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.
 <Xt>:64-bit name of the general-purpose register to be tested, encoded in the "Rt" field.

ccmn (immediate) - conditional compare negative (immediate) - sets the value of the condition flags to the result of the comparison of a register value and a negated immediate value if the condition is TRUE, and an immediate value otherwise.
.0111010010.........10.....0....
fpS        imm5 cond 2Rn   3nzcv
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <imm>:Is a five bit unsigned (positive) immediate encoded in the "imm5" field.
 <nzcv>:flag bit specifier, an immediate in the range 0 to 15, giving the alternative state for the 4-bit NZCV condition flags, encoded in the "nzcv" field.
 <cond>
 cond | <cond>
 0000 | EQ
 0001 | NE
 0010 | CS
 0011 | CC
 0100 | MI
 0101 | PL
 0110 | VS
 0111 | VC
 1000 | HI
 1001 | LS
 1010 | GE
 1011 | LT
 1100 | GT
 1101 | LE
 1110 | AL
 1111 | NV
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

ccmn (register) - conditional compare negative (register) - sets the value of the condition flags to the result of the comparison of a register value and the inverse of another register value if the condition is TRUE, and an immediate value otherwise.
.0111010010.........00.....0....
fpS        Rm   cond 2Rn   3nzcv
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <nzcv>:flag bit specifier, an immediate in the range 0 to 15, giving the alternative state for the 4-bit NZCV condition flags, encoded in the "nzcv" field.
 <cond>
 cond | <cond>
 0000 | EQ
 0001 | NE
 0010 | CS
 0011 | CC
 0100 | MI
 0101 | PL
 0110 | VS
 0111 | VC
 1000 | HI
 1001 | LS
 1010 | GE
 1011 | LT
 1100 | GT
 1101 | LE
 1110 | AL
 1111 | NV
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

ccmp (immediate) - conditional compare (immediate) - sets the value of the condition flags to the result of the comparison of a register value and an immediate value if the condition is TRUE, and an immediate value otherwise.
.1111010010.........10.....0....
fpS        imm5 cond 2Rn   3nzcv
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <imm>:Is a five bit unsigned (positive) immediate encoded in the "imm5" field.
 <nzcv>:flag bit specifier, an immediate in the range 0 to 15, giving the alternative state for the 4-bit NZCV condition flags, encoded in the "nzcv" field.
 <cond>
 cond | <cond>
 0000 | EQ
 0001 | NE
 0010 | CS
 0011 | CC
 0100 | MI
 0101 | PL
 0110 | VS
 0111 | VC
 1000 | HI
 1001 | LS
 1010 | GE
 1011 | LT
 1100 | GT
 1101 | LE
 1110 | AL
 1111 | NV
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

ccmp (register) - conditional compare (register) - sets the value of the condition flags to the result of the comparison of two registers if the condition is TRUE, and an immediate value otherwise.
.1111010010.........00.....0....
fpS        Rm   cond 2Rn   3nzcv
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <nzcv>:flag bit specifier, an immediate in the range 0 to 15, giving the alternative state for the 4-bit NZCV condition flags, encoded in the "nzcv" field.
 <cond>
 cond | <cond>
 0000 | EQ
 0001 | NE
 0010 | CS
 0011 | CC
 0100 | MI
 0101 | PL
 0110 | VS
 0111 | VC
 1000 | HI
 1001 | LS
 1010 | GE
 1011 | LT
 1100 | GT
 1101 | LE
 1110 | AL
 1111 | NV
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

cfinv - invert carry flag - inverts the value of the PSTATE.C flag.
11010101000000000100000000011111
             op1    CRm op2Rt   


cfp - control flow prediction restriction by context - prevents control flow predictions that predict execution addresses based on information gathered from earlier execution within a particular execution context. Control flow predictions determined by the actions of code in the target execution context or contexts appearing in program order before the instruction cannot be used to exploitatively control speculative execution occurring after the instruction is complete and synchronized. For more information, see CFP RCTX, Control Flow Prediction Restriction by Context.
110101010000101101110011100.....
          L  op1CRn CRm op2Rt   
 <Xt>:64-bit name of the general-purpose source register, encoded in the "Rt" field.

chkfeat - check feature status - indicates the status of features. For more information, see Check Feature. If FEAT_CHK is not implemented, this instruction executes as a NOP.
11010101000000110010010100011111
                    CRm op2     


cinc - conditional increment - returns, in the destination register, the value of the source register incremented by 1 if the condition is TRUE, and otherwise returns the value of the source register.
.0011010100!= 11111!= 11111!= 11111!= 11111!= 11111!= 111x!= 111x!= 111x!= 111x01!= 11111!= 11111!= 11111!= 11111!= 11111.....
fpS        Rm   cond 2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.
 <invcond>:Maps to 
 cond | <invcond> | Description
 0000 | NE | 
                  
 0001 | EQ | 
                  
 0010 | CC | 
                  
 0011 | CS | 
                  
 0100 | PL | 
                  
 0101 | MI | 
                  
 0110 | VC | 
                  
 0111 | VS | 
                  
 1000 | LS | 
                  
 1001 | HI | 
                  
 1010 | LT | 
                  
 1011 | GE | 
                  
 1100 | LE | 
                  
 1101 | GT | 
                  
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.

cinv - conditional invert - returns, in the destination register, the bitwise inversion of the value of the source register if the condition is TRUE, and otherwise returns the value of the source register.
.1011010100!= 11111!= 11111!= 11111!= 11111!= 11111!= 111x!= 111x!= 111x!= 111x00!= 11111!= 11111!= 11111!= 11111!= 11111.....
fpS        Rm   cond 2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.
 <invcond>:Maps to 
 cond | <invcond> | Description
 0000 | NE | 
                  
 0001 | EQ | 
                  
 0010 | CC | 
                  
 0011 | CS | 
                  
 0100 | PL | 
                  
 0101 | MI | 
                  
 0110 | VC | 
                  
 0111 | VS | 
                  
 1000 | LS | 
                  
 1001 | HI | 
                  
 1010 | LT | 
                  
 1011 | GE | 
                  
 1100 | LE | 
                  
 1101 | GT | 
                  
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.

clrbhb - clear branch history - clears the branch history for the current context to the extent that branch history information created before the CLRBHB instruction cannot be used by code before the CLRBHB instruction to exploitatively control the execution of any indirect branches in code in the current context that appear in program order after the instruction.
11010101000000110010001011011111
                    CRm op2     


clrex - clear exclusive - clears the local monitor of the executing PE.
11010101000000110011....01011111
                    CRm op2Rt   
 <imm>:Is an optional 4-bit unsigned immediate, in the range 0 to 15, defaulting to 15 and encoded in the "CRm" field.

cls - count leading sign bits - counts the number of leading bits of the source register that have the same value as the most significant bit of the register, and writes the result to the destination register. This count does not include the most significant bit of the source register.
.101101011000000000101..........
f S        code2     pRn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

clz - count leading zeros - counts the number of consecutive binary zero bits, starting from the most significant bit in the source register, and places the count in the destination register.
.101101011000000000100..........
f S        code2     pRn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

cmn (extended register) - compare negative (extended register) - adds a register value and a sign or zero-extended register value, followed by an optional left shift amount. The argument that is extended from the <Rm> register can be a byte, halfword, word, or doubleword. It updates the condition flags based on the result, and discards the result.
.0101011001................11111
fpS     pt Rm   ionmm3Rn   Rd   
 <Wn|WSP>:32-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <extend>
 option | <extend>
 000 | UXTB
 001 | UXTH
 010 | LSL|UXTW
 011 | UXTX
 100 | SXTB
 101 | SXTH
 110 | SXTW
 111 | SXTX
 If "Rn" is '11111' (WSP) and "option" is '010' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTW when "option" is '010'.
 <extend>
 option | <extend>
 000 | UXTB
 001 | UXTH
 010 | UXTW
 011 | LSL|UXTX
 100 | SXTB
 101 | SXTH
 110 | SXTW
 111 | SXTX
 If "Rn" is '11111' (SP) and "option" is '011' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTX when "option" is '011'.
 <amount>:left shift amount to be applied after extension in the range 0 to 4, defaulting to 0, encoded in the "imm3" field. It must be absent when <extend> is absent, is required when <extend> is LSL, and is optional when <extend> is present but not LSL.
 <Xn|SP>:64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <R>
 option | <R>
 00x | W
 010 | W
 x11 | X
 10x | W
 110 | W
 <m>:number [0-30] of the second general-purpose source register or the name ZR (31), encoded in the "Rm" field.

cmn (immediate) - compare negative (immediate) - adds a register value and an optionally-shifted immediate value. It updates the condition flags based on the result, and discards the result.
.01100010..................11111
fpS      himm12       Rn   Rd   
 <Wn|WSP>:32-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.
 <imm>:Is an unsigned immediate, in the range 0 to 4095, encoded in the "imm12" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #12
 <Xn|SP>:64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.

cmn (shifted register) - compare negative (shifted register) - adds a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result.
.0101011..0................11111
fpS     ft Rm   imm6  Rn   Rd   
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | RESERVED
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

cmp (extended register) - compare (extended register) - subtracts a sign or zero-extended register value, followed by an optional left shift amount, from a register value. The argument that is extended from the <Rm> register can be a byte, halfword, word, or doubleword. It updates the condition flags based on the result, and discards the result.
.1101011001................11111
fpS     pt Rm   ionmm3Rn   Rd   
 <Wn|WSP>:32-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <extend>
 option | <extend>
 000 | UXTB
 001 | UXTH
 010 | LSL|UXTW
 011 | UXTX
 100 | SXTB
 101 | SXTH
 110 | SXTW
 111 | SXTX
 If "Rn" is '11111' (WSP) and "option" is '010' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTW when "option" is '010'.
 <extend>
 option | <extend>
 000 | UXTB
 001 | UXTH
 010 | UXTW
 011 | LSL|UXTX
 100 | SXTB
 101 | SXTH
 110 | SXTW
 111 | SXTX
 If "Rn" is '11111' (SP) and "option" is '011' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTX when "option" is '011'.
 <amount>:left shift amount to be applied after extension in the range 0 to 4, defaulting to 0, encoded in the "imm3" field. It must be absent when <extend> is absent, is required when <extend> is LSL, and is optional when <extend> is present but not LSL.
 <Xn|SP>:64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <R>
 option | <R>
 00x | W
 010 | W
 x11 | X
 10x | W
 110 | W
 <m>:number [0-30] of the second general-purpose source register or the name ZR (31), encoded in the "Rm" field.

cmp (immediate) - compare (immediate) - subtracts an optionally-shifted immediate value from a register value. It updates the condition flags based on the result, and discards the result.
.11100010..................11111
fpS      himm12       Rn   Rd   
 <Wn|WSP>:32-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.
 <imm>:Is an unsigned immediate, in the range 0 to 4095, encoded in the "imm12" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #12
 <Xn|SP>:64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.

cmp (shifted register) - compare (shifted register) - subtracts an optionally-shifted register value from a register value. It updates the condition flags based on the result, and discards the result.
.1101011..0................11111
fpS     ft Rm   imm6  Rn   Rd   
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | RESERVED
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

cmpp - compare with tag - subtracts the 56-bit address held in the second source register from the 56-bit address held in the first source register, updates the condition flags based on the result of the subtraction, and discards the result.
10111010110.....000000.....11111
f S        Rm   opcodeRn   Rd   
 <Xn|SP>:64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <Xm|SP>:64-bit name of the second general-purpose source register or stack pointer, encoded in the "Rm" field.

cneg - conditional negate - returns, in the destination register, the negated value of the source register if the condition is TRUE, and otherwise returns the value of the source register.
.1011010100.....!= 111x!= 111x!= 111x!= 111x01..........
fpS        Rm   cond 2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.
 <invcond>:Maps to 
 cond | <invcond> | Description
 0000 | NE | 
                  
 0001 | EQ | 
                  
 0010 | CC | 
                  
 0011 | CS | 
                  
 0100 | PL | 
                  
 0101 | MI | 
                  
 0110 | VC | 
                  
 0111 | VS | 
                  
 1000 | LS | 
                  
 1001 | HI | 
                  
 1010 | LT | 
                  
 1011 | GE | 
                  
 1100 | LE | 
                  
 1101 | GT | 
                  
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.

cnt - count bits - counts the number of binary one bits in the value of the source register, and writes the result to the destination register.
.101101011000000000111..........
f S        code2opcodeRn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

cosp - clear other speculative prediction restriction by context - prevents predictions, other than Cache prefetch, Control flow, and Data Value predictions, that predict execution addresses based on information gathered from earlier execution within a particular execution context. Predictions, other than Cache prefetch, Control flow, and Data Value predictions, determined by the actions of code in the target execution context or contexts appearing in program order before the instruction cannot exploitatively control any speculative access occurring after the instruction is complete and synchronized.
110101010000101101110011110.....
          L  op1CRn CRm op2Rt   
 <Xt>:64-bit name of the general-purpose source register, encoded in the "Rt" field.

cpp - cache prefetch prediction restriction by context - prevents cache allocation predictions that predict execution addresses based on information gathered from earlier execution within a particular execution context. The actions of code in the target execution context or contexts appearing in program order before the instruction cannot exploitatively control cache prefetch predictions occurring after the instruction is complete and synchronized. For more information, see CPP RCTX, Cache Prefetch Prediction Restriction by Context.
110101010000101101110011111.....
          L  op1CRn CRm op2Rt   
 <Xt>:64-bit name of the general-purpose source register, encoded in the "Rt" field.

cpyfp, cpyfm, cpyfe - memory copy forward-only - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFP, then CPYFM, and then CPYFE. CPYFP performs some preconditioning of the arguments suitable for using the CPYFM instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFM copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFE copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFP: On completion of CPYFP, option A: On completion of CPYFP, option B: For CPYFM, option A, when PSTATE.C = 0: For CPYFM, option B, when PSTATE.C = 1: For CPYFE, option A, when PSTATE.C = 0: For CPYFE, option B, when PSTATE.C = 1:
..011001..0.....000001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyfpn, cpyfmn, cpyfen - memory copy forward-only, reads and writes non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFPN, then CPYFMN, and then CPYFEN. CPYFPN performs some preconditioning of the arguments suitable for using the CPYFMN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFMN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFEN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFPN: On completion of CPYFPN, option A: On completion of CPYFPN, option B: For CPYFMN, option A, when PSTATE.C = 0: For CPYFMN, option B, when PSTATE.C = 1: For CPYFEN, option A, when PSTATE.C = 0: For CPYFEN, option B, when PSTATE.C = 1:
..011001..0.....110001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyfprn, cpyfmrn, cpyfern - memory copy forward-only, reads non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFPRN, then CPYFMRN, and then CPYFERN. CPYFPRN performs some preconditioning of the arguments suitable for using the CPYFMRN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFMRN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFERN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFPRN: On completion of CPYFPRN, option A: On completion of CPYFPRN, option B: For CPYFMRN, option A, when PSTATE.C = 0: For CPYFMRN, option B, when PSTATE.C = 1: For CPYFERN, option A, when PSTATE.C = 0: For CPYFERN, option B, when PSTATE.C = 1:
..011001..0.....100001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyfprt, cpyfmrt, cpyfert - memory copy forward-only, reads unprivileged - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFPRT, then CPYFMRT, and then CPYFERT. CPYFPRT performs some preconditioning of the arguments suitable for using the CPYFMRT instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFMRT copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFERT copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFPRT: On completion of CPYFPRT, option A: On completion of CPYFPRT, option B: For CPYFMRT, option A, when PSTATE.C = 0: For CPYFMRT, option B, when PSTATE.C = 1: For CPYFERT, option A, when PSTATE.C = 0: For CPYFERT, option B, when PSTATE.C = 1: Explicit Memory Read  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Read  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011001..0.....001001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyfprtn, cpyfmrtn, cpyfertn - memory copy forward-only, reads unprivileged, reads and writes non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFPRTN, then CPYFMRTN, and then CPYFERTN. CPYFPRTN performs some preconditioning of the arguments suitable for using the CPYFMRTN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFMRTN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFERTN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFPRTN: On completion of CPYFPRTN, option A: On completion of CPYFPRTN, option B: For CPYFMRTN, option A, when PSTATE.C = 0: For CPYFMRTN, option B, when PSTATE.C = 1: For CPYFERTN, option A, when PSTATE.C = 0: For CPYFERTN, option B, when PSTATE.C = 1: Explicit Memory Read  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Read  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011001..0.....111001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyfprtrn, cpyfmrtrn, cpyfertrn - memory copy forward-only, reads unprivileged and non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFPRTRN, then CPYFMRTRN, and then CPYFERTRN. CPYFPRTRN performs some preconditioning of the arguments suitable for using the CPYFMRTRN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFMRTRN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFERTRN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFPRTRN: On completion of CPYFPRTRN, option A: On completion of CPYFPRTRN, option B: For CPYFMRTRN, option A, when PSTATE.C = 0: For CPYFMRTRN, option B, when PSTATE.C = 1: For CPYFERTRN, option A, when PSTATE.C = 0: For CPYFERTRN, option B, when PSTATE.C = 1: Explicit Memory Read  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Read  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011001..0.....101001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyfprtwn, cpyfmrtwn, cpyfertwn - memory copy forward-only, reads unprivileged, writes non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFPRTWN, then CPYFMRTWN, and then CPYFERTWN. CPYFPRTWN performs some preconditioning of the arguments suitable for using the CPYFMRTWN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFMRTWN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFERTWN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFPRTWN: On completion of CPYFPRTWN, option A: On completion of CPYFPRTWN, option B: For CPYFMRTWN, option A, when PSTATE.C = 0: For CPYFMRTWN, option B, when PSTATE.C = 1: For CPYFERTWN, option A, when PSTATE.C = 0: For CPYFERTWN, option B, when PSTATE.C = 1: Explicit Memory Read  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Read  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011001..0.....011001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyfpt, cpyfmt, cpyfet - memory copy forward-only, reads and writes unprivileged - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFPT, then CPYFMT, and then CPYFET. CPYFPT performs some preconditioning of the arguments suitable for using the CPYFMT instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFMT copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFET copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFPT: On completion of CPYFPT, option A: On completion of CPYFPT, option B: For CPYFMT, option A, when PSTATE.C = 0: For CPYFMT, option B, when PSTATE.C = 1: For CPYFET, option A, when PSTATE.C = 0: For CPYFET, option B, when PSTATE.C = 1: Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011001..0.....001101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyfptn, cpyfmtn, cpyfetn - memory copy forward-only, reads and writes unprivileged and non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFPTN, then CPYFMTN, and then CPYFETN. CPYFPTN performs some preconditioning of the arguments suitable for using the CPYFMTN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFMTN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFETN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFPTN: On completion of CPYFPTN, option A: On completion of CPYFPTN, option B: For CPYFMTN, option A, when PSTATE.C = 0: For CPYFMTN, option B, when PSTATE.C = 1: For CPYFETN, option A, when PSTATE.C = 0: For CPYFETN, option B, when PSTATE.C = 1: Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011001..0.....111101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyfptrn, cpyfmtrn, cpyfetrn - memory copy forward-only, reads and writes unprivileged, reads non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFPTRN, then CPYFMTRN, and then CPYFETRN. CPYFPTRN performs some preconditioning of the arguments suitable for using the CPYFMTRN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFMTRN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFETRN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFPTRN: On completion of CPYFPTRN, option A: On completion of CPYFPTRN, option B: For CPYFMTRN, option A, when PSTATE.C = 0: For CPYFMTRN, option B, when PSTATE.C = 1: For CPYFETRN, option A, when PSTATE.C = 0: For CPYFETRN, option B, when PSTATE.C = 1: Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011001..0.....101101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyfptwn, cpyfmtwn, cpyfetwn - memory copy forward-only, reads and writes unprivileged, writes non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFPTWN, then CPYFMTWN, and then CPYFETWN. CPYFPTWN performs some preconditioning of the arguments suitable for using the CPYFMTWN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFMTWN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFETWN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFPTWN: On completion of CPYFPTWN, option A: On completion of CPYFPTWN, option B: For CPYFMTWN, option A, when PSTATE.C = 0: For CPYFMTWN, option B, when PSTATE.C = 1: For CPYFETWN, option A, when PSTATE.C = 0: For CPYFETWN, option B, when PSTATE.C = 1: Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011001..0.....011101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyfpwn, cpyfmwn, cpyfewn - memory copy forward-only, writes non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFPWN, then CPYFMWN, and then CPYFEWN. CPYFPWN performs some preconditioning of the arguments suitable for using the CPYFMWN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFMWN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFEWN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFPWN: On completion of CPYFPWN, option A: On completion of CPYFPWN, option B: For CPYFMWN, option A, when PSTATE.C = 0: For CPYFMWN, option B, when PSTATE.C = 1: For CPYFEWN, option A, when PSTATE.C = 0: For CPYFEWN, option B, when PSTATE.C = 1:
..011001..0.....010001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyfpwt, cpyfmwt, cpyfewt - memory copy forward-only, writes unprivileged - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFPWT, then CPYFMWT, and then CPYFEWT. CPYFPWT performs some preconditioning of the arguments suitable for using the CPYFMWT instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFMWT copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFEWT copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFPWT: On completion of CPYFPWT, option A: On completion of CPYFPWT, option B: For CPYFMWT, option A, when PSTATE.C = 0: For CPYFMWT, option B, when PSTATE.C = 1: For CPYFEWT, option A, when PSTATE.C = 0: For CPYFEWT, option B, when PSTATE.C = 1: Explicit Memory Write  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Write  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011001..0.....000101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyfpwtn, cpyfmwtn, cpyfewtn - memory copy forward-only, writes unprivileged, reads and writes non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFPWTN, then CPYFMWTN, and then CPYFEWTN. CPYFPWTN performs some preconditioning of the arguments suitable for using the CPYFMWTN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFMWTN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFEWTN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFPWTN: On completion of CPYFPWTN, option A: On completion of CPYFPWTN, option B: For CPYFMWTN, option A, when PSTATE.C = 0: For CPYFMWTN, option B, when PSTATE.C = 1: For CPYFEWTN, option A, when PSTATE.C = 0: For CPYFEWTN, option B, when PSTATE.C = 1: Explicit Memory Write  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Write  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011001..0.....110101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyfpwtrn, cpyfmwtrn, cpyfewtrn - memory copy forward-only, writes unprivileged, reads non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFPWTRN, then CPYFMWTRN, and then CPYFEWTRN. CPYFPWTRN performs some preconditioning of the arguments suitable for using the CPYFMWTRN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFMWTRN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFEWTRN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFPWTRN: On completion of CPYFPWTRN, option A: On completion of CPYFPWTRN, option B: For CPYFMWTRN, option A, when PSTATE.C = 0: For CPYFMWTRN, option B, when PSTATE.C = 1: For CPYFEWTRN, option A, when PSTATE.C = 0: For CPYFEWTRN, option B, when PSTATE.C = 1: Explicit Memory Write  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Write  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011001..0.....100101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyfpwtwn, cpyfmwtwn, cpyfewtwn - memory copy forward-only, writes unprivileged and non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address in a forward direction. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYFPWTWN, then CPYFMWTWN, and then CPYFEWTWN. CPYFPWTWN performs some preconditioning of the arguments suitable for using the CPYFMWTWN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYFMWTWN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYFEWTWN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The memory copy performed by these instructions is in the forward direction only, so the instructions are suitable for a memory copy only where there is no overlap between the source and destination locations, or where the source address is greater than the destination address. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYFPWTWN: On completion of CPYFPWTWN, option A: On completion of CPYFPWTWN, option B: For CPYFMWTWN, option A, when PSTATE.C = 0: For CPYFMWTWN, option B, when PSTATE.C = 1: For CPYFEWTWN, option A, when PSTATE.C = 0: For CPYFEWTWN, option B, when PSTATE.C = 1: Explicit Memory Write  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Write  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011001..0.....010101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyp, cpym, cpye - memory copy - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYP, then CPYM, and then CPYE. CPYP performs some preconditioning of the arguments suitable for using the CPYM instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYM copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYE copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYP: On completion of CPYP, option A: On completion of CPYP, option B: For CPYM, option A, when PSTATE.C = 0: For CPYM, option B, when PSTATE.C = 1: For CPYE, option A, when PSTATE.C = 0: For CPYE, option B, when PSTATE.C = 1:
..011101..0.....000001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpypn, cpymn, cpyen - memory copy, reads and writes non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYPN, then CPYMN, and then CPYEN. CPYPN performs some preconditioning of the arguments suitable for using the CPYMN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYMN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYEN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYPN: On completion of CPYPN, option A: On completion of CPYPN, option B: For CPYMN, option A, when PSTATE.C = 0: For CPYMN, option B, when PSTATE.C = 1: For CPYEN, option A, when PSTATE.C = 0: For CPYEN, option B, when PSTATE.C = 1:
..011101..0.....110001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyprn, cpymrn, cpyern - memory copy, reads non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYPRN, then CPYMRN, and then CPYERN. CPYPRN performs some preconditioning of the arguments suitable for using the CPYMRN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYMRN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYERN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYPRN: On completion of CPYPRN, option A: On completion of CPYPRN, option B: For CPYMRN, option A, when PSTATE.C = 0: For CPYMRN, option B, when PSTATE.C = 1: For CPYERN, option A, when PSTATE.C = 0: For CPYERN, option B, when PSTATE.C = 1:
..011101..0.....100001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyprt, cpymrt, cpyert - memory copy, reads unprivileged - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYPRT, then CPYMRT, and then CPYERT. CPYPRT performs some preconditioning of the arguments suitable for using the CPYMRT instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYMRT copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYERT copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYPRT: On completion of CPYPRT, option A: On completion of CPYPRT, option B: For CPYMRT, option A, when PSTATE.C = 0: For CPYMRT, option B, when PSTATE.C = 1: For CPYERT, option A, when PSTATE.C = 0: For CPYERT, option B, when PSTATE.C = 1: Explicit Memory Read  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Read  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011101..0.....001001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyprtn, cpymrtn, cpyertn - memory copy, reads unprivileged, reads and writes non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYPRTN, then CPYMRTN, and then CPYERTN. CPYPRTN performs some preconditioning of the arguments suitable for using the CPYMRTN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYMRTN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYERTN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYPRTN: On completion of CPYPRTN, option A: On completion of CPYPRTN, option B: For CPYMRTN, option A, when PSTATE.C = 0: For CPYMRTN, option B, when PSTATE.C = 1: For CPYERTN, option A, when PSTATE.C = 0: For CPYERTN, option B, when PSTATE.C = 1: Explicit Memory Read  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Read  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011101..0.....111001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyprtrn, cpymrtrn, cpyertrn - memory copy, reads unprivileged and non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYPRTRN, then CPYMRTRN, and then CPYERTRN. CPYPRTRN performs some preconditioning of the arguments suitable for using the CPYMRTRN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYMRTRN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYERTRN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYPRTRN: On completion of CPYPRTRN, option A: On completion of CPYPRTRN, option B: For CPYMRTRN, option A, when PSTATE.C = 0: For CPYMRTRN, option B, when PSTATE.C = 1: For CPYERTRN, option A, when PSTATE.C = 0: For CPYERTRN, option B, when PSTATE.C = 1: Explicit Memory Read  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Read  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011101..0.....101001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyprtwn, cpymrtwn, cpyertwn - memory copy, reads unprivileged, writes non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYPRTWN, then CPYMRTWN, and then CPYERTWN. CPYPRTWN performs some preconditioning of the arguments suitable for using the CPYMRTWN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYMRTWN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYERTWN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYPRTWN: On completion of CPYPRTWN, option A: On completion of CPYPRTWN, option B: For CPYMRTWN, option A, when PSTATE.C = 0: For CPYMRTWN, option B, when PSTATE.C = 1: For CPYERTWN, option A, when PSTATE.C = 0: For CPYERTWN, option B, when PSTATE.C = 1: Explicit Memory Read  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Read  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011101..0.....011001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpypt, cpymt, cpyet - memory copy, reads and writes unprivileged - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYPT, then CPYMT, and then CPYET. CPYPT performs some preconditioning of the arguments suitable for using the CPYMT instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYMT copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYET copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYPT: On completion of CPYPT, option A: On completion of CPYPT, option B: For CPYMT, option A, when PSTATE.C = 0: For CPYMT, option B, when PSTATE.C = 1: For CPYET, option A, when PSTATE.C = 0: For CPYET, option B, when PSTATE.C = 1: Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011101..0.....001101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyptn, cpymtn, cpyetn - memory copy, reads and writes unprivileged and non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYPTN, then CPYMTN, and then CPYETN. CPYPTN performs some preconditioning of the arguments suitable for using the CPYMTN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYMTN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYETN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYPTN: On completion of CPYPTN, option A: On completion of CPYPTN, option B: For CPYMTN, option A, when PSTATE.C = 0: For CPYMTN, option B, when PSTATE.C = 1: For CPYETN, option A, when PSTATE.C = 0: For CPYETN, option B, when PSTATE.C = 1: Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011101..0.....111101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyptrn, cpymtrn, cpyetrn - memory copy, reads and writes unprivileged, reads non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYPTRN, then CPYMTRN, and then CPYETRN. CPYPTRN performs some preconditioning of the arguments suitable for using the CPYMTRN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYMTRN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYETRN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYPTRN: On completion of CPYPTRN, option A: On completion of CPYPTRN, option B: For CPYMTRN, option A, when PSTATE.C = 0: For CPYMTRN, option B, when PSTATE.C = 1: For CPYETRN, option A, when PSTATE.C = 0: For CPYETRN, option B, when PSTATE.C = 1: Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011101..0.....101101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpyptwn, cpymtwn, cpyetwn - memory copy, reads and writes unprivileged, writes non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYPTWN, then CPYMTWN, and then CPYETWN. CPYPTWN performs some preconditioning of the arguments suitable for using the CPYMTWN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYMTWN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYETWN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYPTWN: On completion of CPYPTWN, option A: On completion of CPYPTWN, option B: For CPYMTWN, option A, when PSTATE.C = 0: For CPYMTWN, option B, when PSTATE.C = 1: For CPYETWN, option A, when PSTATE.C = 0: For CPYETWN, option B, when PSTATE.C = 1: Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011101..0.....011101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpypwn, cpymwn, cpyewn - memory copy, writes non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYPWN, then CPYMWN, and then CPYEWN. CPYPWN performs some preconditioning of the arguments suitable for using the CPYMWN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYMWN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYEWN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYPWN: On completion of CPYPWN, option A: On completion of CPYPWN, option B: For CPYMWN, option A, when PSTATE.C = 0: For CPYMWN, option B, when PSTATE.C = 1: For CPYEWN, option A, when PSTATE.C = 0: For CPYEWN, option B, when PSTATE.C = 1:
..011101..0.....010001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpypwt, cpymwt, cpyewt - memory copy, writes unprivileged - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYPWT, then CPYMWT, and then CPYEWT. CPYPWT performs some preconditioning of the arguments suitable for using the CPYMWT instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYMWT copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYEWT copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYPWT: On completion of CPYPWT, option A: On completion of CPYPWT, option B: For CPYMWT, option A, when PSTATE.C = 0: For CPYMWT, option B, when PSTATE.C = 1: For CPYEWT, option A, when PSTATE.C = 0: For CPYEWT, option B, when PSTATE.C = 1: Explicit Memory Write  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Write  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011101..0.....000101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpypwtn, cpymwtn, cpyewtn - memory copy, writes unprivileged, reads and writes non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYPWTN, then CPYMWTN, and then CPYEWTN. CPYPWTN performs some preconditioning of the arguments suitable for using the CPYMWTN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYMWTN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYEWTN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYPWTN: On completion of CPYPWTN, option A: On completion of CPYPWTN, option B: For CPYMWTN, option A, when PSTATE.C = 0: For CPYMWTN, option B, when PSTATE.C = 1: For CPYEWTN, option A, when PSTATE.C = 0: For CPYEWTN, option B, when PSTATE.C = 1: Explicit Memory Write  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Write  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011101..0.....110101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpypwtrn, cpymwtrn, cpyewtrn - memory copy, writes unprivileged, reads non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYPWTRN, then CPYMWTRN, and then CPYEWTRN. CPYPWTRN performs some preconditioning of the arguments suitable for using the CPYMWTRN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYMWTRN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYEWTRN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYPWTRN: On completion of CPYPWTRN, option A: On completion of CPYPWTRN, option B: For CPYMWTRN, option A, when PSTATE.C = 0: For CPYMWTRN, option B, when PSTATE.C = 1: For CPYEWTRN, option A, when PSTATE.C = 0: For CPYEWTRN, option B, when PSTATE.C = 1: Explicit Memory Write  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Write  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011101..0.....100101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

cpypwtwn, cpymwtwn, cpyewtwn - memory copy, writes unprivileged and non-temporal - These instructions copy a requested number of bytes in memory from a source address to a destination address. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: CPYPWTWN, then CPYMWTWN, and then CPYEWTWN. CPYPWTWN performs some preconditioning of the arguments suitable for using the CPYMWTWN instruction, and copies an IMPLEMENTATION DEFINED portion of the requested number of bytes. CPYMWTWN copies a further IMPLEMENTATION DEFINED portion of the remaining bytes. CPYEWTWN copies any final remaining bytes. For more information on exceptions specific to memory copy instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory copy: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For CPYPWTWN: On completion of CPYPWTWN, option A: On completion of CPYPWTWN, option B: For CPYMWTWN, option A, when PSTATE.C = 0: For CPYMWTWN, option B, when PSTATE.C = 1: For CPYEWTWN, option A, when PSTATE.C = 0: For CPYEWTWN, option B, when PSTATE.C = 1: Explicit Memory Write  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Write  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011101..0.....010101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address, encoded in the "Rd" field.
 <Xs>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the source address and is updated by the instruction, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the source address, encoded in the "Rs" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be transferred and is updated by the instruction to encode the remaining size and destination, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be transferred and is set to zero on completion of the instruction, encoded in the "Rn" field.

crc32b, crc32h, crc32w, crc32x - crc32 checksum - performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation. In an Armv8.0 implementation, this is an OPTIONAL instruction. From Armv8.1, it is mandatory for all implementations to implement this instruction.
.0011010110.....0100............
f S        Rm      CszRn   Rd   
 <Wd>:32-bit name of the general-purpose accumulator output register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose accumulator input register, encoded in the "Rn" field.
 <Wm>:32-bit name of the general-purpose data source register, encoded in the "Rm" field.
 <Xm>:64-bit name of the general-purpose data source register, encoded in the "Rm" field.

crc32cb, crc32ch, crc32cw, crc32cx - crc32c checksum - performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the CRC calculation. In an Armv8.0 implementation, this is an OPTIONAL instruction. From Armv8.1, it is mandatory for all implementations to implement this instruction.
.0011010110.....0101............
f S        Rm      CszRn   Rd   
 <Wd>:32-bit name of the general-purpose accumulator output register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose accumulator input register, encoded in the "Rn" field.
 <Wm>:32-bit name of the general-purpose data source register, encoded in the "Rm" field.
 <Xm>:64-bit name of the general-purpose data source register, encoded in the "Rm" field.

csdb - consumption of speculative data barrier - is a memory barrier that controls speculative execution arising from data value prediction. For more information and details of the semantics, see Consumption of Speculative Data Barrier (CSDB).
11010101000000110010001010011111
                    CRm op2     


csel - conditional select - writes the value of the first source register to the destination register if the condition is TRUE. If the condition is FALSE, it writes the value of the second source register to the destination register.
.0011010100.........00..........
fpS        Rm   cond 2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <cond>
 cond | <cond>
 0000 | EQ
 0001 | NE
 0010 | CS
 0011 | CC
 0100 | MI
 0101 | PL
 0110 | VS
 0111 | VC
 1000 | HI
 1001 | LS
 1010 | GE
 1011 | LT
 1100 | GT
 1101 | LE
 1110 | AL
 1111 | NV
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

cset - conditional set - sets the destination register to 1 if the condition is TRUE, and otherwise sets it to 0.
.001101010011111!= 111x!= 111x!= 111x!= 111x0111111.....
fpS        Rm   cond 2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <invcond>:Maps to 
 cond | <invcond> | Description
 0000 | NE | 
                  
 0001 | EQ | 
                  
 0010 | CC | 
                  
 0011 | CS | 
                  
 0100 | PL | 
                  
 0101 | MI | 
                  
 0110 | VC | 
                  
 0111 | VS | 
                  
 1000 | LS | 
                  
 1001 | HI | 
                  
 1010 | LT | 
                  
 1011 | GE | 
                  
 1100 | LE | 
                  
 1101 | GT | 
                  
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.

csetm - conditional set mask - sets all bits of the destination register to 1 if the condition is TRUE, and otherwise sets all bits to 0.
.101101010011111!= 111x!= 111x!= 111x!= 111x0011111.....
fpS        Rm   cond 2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <invcond>:Maps to 
 cond | <invcond> | Description
 0000 | NE | 
                  
 0001 | EQ | 
                  
 0010 | CC | 
                  
 0011 | CS | 
                  
 0100 | PL | 
                  
 0101 | MI | 
                  
 0110 | VC | 
                  
 0111 | VS | 
                  
 1000 | LS | 
                  
 1001 | HI | 
                  
 1010 | LT | 
                  
 1011 | GE | 
                  
 1100 | LE | 
                  
 1101 | GT | 
                  
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.

csinc - conditional select increment - returns, in the destination register, the value of the first source register if the condition is TRUE, and otherwise returns the value of the second source register incremented by 1.
.0011010100.........01..........
fpS        Rm   cond 2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <cond>
 cond | <cond>
 0000 | EQ
 0001 | NE
 0010 | CS
 0011 | CC
 0100 | MI
 0101 | PL
 0110 | VS
 0111 | VC
 1000 | HI
 1001 | LS
 1010 | GE
 1011 | LT
 1100 | GT
 1101 | LE
 1110 | AL
 1111 | NV
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

csinv - conditional select invert - returns, in the destination register, the value of the first source register if the condition is TRUE, and otherwise returns the bitwise inversion value of the second source register.
.1011010100.........00..........
fpS        Rm   cond 2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <cond>
 cond | <cond>
 0000 | EQ
 0001 | NE
 0010 | CS
 0011 | CC
 0100 | MI
 0101 | PL
 0110 | VS
 0111 | VC
 1000 | HI
 1001 | LS
 1010 | GE
 1011 | LT
 1100 | GT
 1101 | LE
 1110 | AL
 1111 | NV
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

csneg - conditional select negation - returns, in the destination register, the value of the first source register if the condition is TRUE, and otherwise returns the negated value of the second source register.
.1011010100.........01..........
fpS        Rm   cond 2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <cond>
 cond | <cond>
 0000 | EQ
 0001 | NE
 0010 | CS
 0011 | CC
 0100 | MI
 0101 | PL
 0110 | VS
 0111 | VC
 1000 | HI
 1001 | LS
 1010 | GE
 1011 | LT
 1100 | GT
 1101 | LE
 1110 | AL
 1111 | NV
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

ctz - count trailing zeros - counts the number of consecutive binary zero bits, starting from the least significant bit in the source register, and places the count in the destination register.
.101101011000000000110..........
f S        code2opcodeRn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

dc - data cache operation - For more information, see op0==0b01, cache maintenance, TLB maintenance, and address translation instructions.
1101010100001...0111............
          L  op1CRn CRm op2Rt   
 <dc_op>
 op1 | CRm | op2 | <dc_op> | Architectural Feature
 000 | 0110 | 001 | IVAC | 
 000 | 0110 | 010 | ISW | 
 000 | 0110 | 011 | IGVAC | 
                  
 000 | 0110 | 100 | IGSW | 
                  
 000 | 0110 | 101 | IGDVAC | 
                  
 000 | 0110 | 110 | IGDSW | 
                  
 000 | 1010 | 010 | CSW | 
 000 | 1010 | 100 | CGSW | 
                  
 000 | 1010 | 110 | CGDSW | 
                  
 000 | 1110 | 010 | CISW | 
 000 | 1110 | 100 | CIGSW | 
                  
 000 | 1110 | 110 | CIGDSW | 
                  
 000 | 1111 | 001 | CIVAPS | 
                  
 000 | 1111 | 101 | CIGDVAPS | 
                  
 011 | 0100 | 001 | ZVA | 
 011 | 0100 | 011 | GVA | 
                  
 011 | 0100 | 100 | GZVA | 
                  
 011 | 1010 | 001 | CVAC | 
 011 | 1010 | 011 | CGVAC | 
                  
 011 | 1010 | 101 | CGDVAC | 
                  
 011 | 1011 | 000 | CVAOC | 
                  
 011 | 1011 | 001 | CVAU | 
 011 | 1011 | 111 | CGDVAOC | 
                  
 011 | 1100 | 001 | CVAP | 
                  
 011 | 1100 | 011 | CGVAP | 
                  
 011 | 1100 | 101 | CGDVAP | 
                  
 011 | 1101 | 001 | CVADP | 
                  
 011 | 1101 | 011 | CGVADP | 
                  
 011 | 1101 | 101 | CGDVADP | 
                  
 011 | 1110 | 001 | CIVAC | 
 011 | 1110 | 011 | CIGVAC | 
                  
 011 | 1110 | 101 | CIGDVAC | 
                  
 011 | 1111 | 000 | CIVAOC | 
                  
 011 | 1111 | 111 | CIGDVAOC | 
                  
 100 | 1110 | 000 | CIPAE | 
                  
 100 | 1110 | 111 | CIGDPAE | 
                  
 110 | 1110 | 001 | CIPAPA | 
                  
 110 | 1110 | 101 | CIGDPAPA | 
                  
 <Xt>:64-bit name of the general-purpose source register, encoded in the "Rt" field.

dcps1 - debug change pe state to el1 - This instruction, when executed in Debug state: The target exception level of a DCPS1 instruction is: When the target Exception level of a DCPS1 instruction is ELx, on executing this instruction: is always UNDEFINED in Non-debug state. is UNDEFINED at EL0 in Non-secure state if EL2 is implemented and HCR_EL2.TGE == 1. For more information on the operation of the DCPS<n> instructions, see DCPS.
11010100101................00001
        opcimm16           op2LL
 <imm>:Is an optional 16-bit unsigned immediate, in the range 0 to 65535, defaulting to 0 and encoded in the "imm16" field.

dcps2 - debug change pe state to el2 - This instruction, when executed in Debug state: The target exception level of a DCPS2 instruction is: When the target Exception level of a DCPS2 instruction is ELx, on executing this instruction: is always UNDEFINED in Non-debug state. is UNDEFINED at the following exception levels: For more information on the operation of the DCPS<n> instructions, see DCPS.
11010100101................00010
        opcimm16           op2LL
 <imm>:Is an optional 16-bit unsigned immediate, in the range 0 to 65535, defaulting to 0 and encoded in the "imm16" field.

dcps3 - debug change pe state to el3 - This instruction, when executed in Debug state: The target exception level of a DCPS3 instruction is EL3. On executing a DCPS3 instruction: is always UNDEFINED in Non-debug state. is UNDEFINED at all exception levels if either: For more information on the operation of the DCPS<n> instructions, see DCPS.
11010100101................00011
        opcimm16           op2LL
 <imm>:Is an optional 16-bit unsigned immediate, in the range 0 to 65535, defaulting to 0 and encoded in the "imm16" field.

dgh - data gathering hint - is a hint instruction that indicates that it is not expected to be performance optimal to merge memory accesses with Normal Non-cacheable or Device-GRE attributes appearing in program order before the hint instruction with any memory accesses appearing after the hint instruction into a single memory transaction on an interconnect.
11010101000000110010000011011111
                    CRm op2     


dmb - data memory barrier - is a memory barrier that ensures the ordering of observations of memory accesses, see Data Memory Barrier.
11010101000000110011....10111111
                    CRm  pcRt   
 <option>:Specifies the limitation on the barrier operation. Values are:
 CRm | <option>
 xx00 | RESERVED
 0001 | OSHLD
 0010 | OSHST
 0011 | OSH
 0101 | NSHLD
 0110 | NSHST
 0111 | NSH
 1001 | ISHLD
 1010 | ISHST
 1011 | ISH
 1101 | LD
 1110 | ST
 1111 | SY
 <imm>:Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the "CRm" field.

drps - debug restore pe state - restores PSTATE from the SPSR. The SPSR is checked for the current Exception level for an illegal return event. See Illegal exception returns from AArch64 state. is UNDEFINED in Non-debug state. is UNDEFINED at EL0. For more information on the operation of DRPS, see DRPS.
11010110101111110000001111100000
       opc op2  op3   Rn   op4  


dsb - data synchronization barrier - is a memory barrier that ensures the completion of memory accesses, see Data Synchronization Barrier.
11010101000000110011....10011111
                    CRm  pcRt   
11010101000000110011..1000111111
                    m2  op2Rt   
 <option>:For the "Memory barrier" variant: specifies the limitation on the barrier operation. Values are:
 CRm | <option>
 0001 | OSHLD
 0010 | OSHST
 0011 | OSH
 0101 | NSHLD
 0110 | NSHST
 0111 | NSH
 1000 | RESERVED
 1001 | ISHLD
 1010 | ISHST
 1011 | ISH
 1100 | RESERVED
 1101 | LD
 1110 | ST
 1111 | SY
 <option>:For the "Memory nXS barrier" variant: specifies the limitation on the barrier operation. Values are:
 imm2 | <option>
 00 | OSH
 01 | NSH
 10 | ISH
 11 | SY
 <imm>:Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the "CRm" field.

dvp - data value prediction restriction by context - prevents data value predictions that predict execution addresses based on information gathered from earlier execution within a particular execution context. Data value predictions determined by the actions of code in the target execution context or contexts appearing in program order before the instruction cannot be used to exploitatively control speculative execution occurring after the instruction is complete and synchronized. For more information, see DVP RCTX, Data Value Prediction Restriction by Context.
110101010000101101110011101.....
          L  op1CRn CRm op2Rt   
 <Xt>:64-bit name of the general-purpose source register, encoded in the "Rt" field.

eon (shifted register) - bitwise exclusive-or not (shifted register) - performs a bitwise exclusive-OR NOT of a register value and an optionally-shifted register value, and writes the result to the destination register.
.1001010..1.....................
fpc     ftNRm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | ROR
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

eor (immediate) - bitwise exclusive-or (immediate) - performs a bitwise exclusive-OR of a register value and an immediate value, and writes the result to the destination register.
.10100100.......................
fpc      Nimmr  imms  Rn   Rd   
 <Wd|WSP>:32-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <imm>:For the "32-bit" variant: is the bitmask immediate, encoded in "imms:immr".
 <imm>:For the "64-bit" variant: is the bitmask immediate, encoded in "N:imms:immr".
 <Xd|SP>:64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

eor (shifted register) - bitwise exclusive-or (shifted register) - performs a bitwise exclusive-OR of a register value and an optionally-shifted register value, and writes the result to the destination register.
.1001010..0.....................
fpc     ftNRm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | ROR
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

eret - exception return - restores PSTATE from the SPSR, and branches to the address held in the ELR. The SPSR is checked for the current Exception level for an illegal return event. See Illegal exception returns from AArch64 state. ERET is UNDEFINED at EL0.
11010110100111110000001111100000
       opc op2      AMRn   op4  


eretaa, eretab - exception return, with pointer authentication - authenticates the address in ELR, using SP as the modifier and the specified key, restores PSTATE from the SPSR for the current Exception level, and branches to the authenticated address. Key A is used for ERETAA. Key B is used for ERETAB. If the authentication passes, the PE continues execution at the target of the branch. For information on behavior if the authentication fails, see Faulting on pointer authentication. The authenticated address is not written back to ELR. The SPSR is checked for the current Exception level for an illegal return event. See Illegal exception returns from AArch64 state. ERETAA and ERETAB are UNDEFINED at EL0.
110101101001111100001.1111111111
       opc op2      AMRn   op4  


esb - error synchronization barrier - is an error synchronization event that might also update DISR_EL1 and VDISR_EL2. can be used at all Exception levels and in Debug state. In Debug state, this instruction behaves as if SError interrupts are masked at all Exception levels. For more information, see RAS PE architecture and Arm® Reliability, Availability, and Serviceability (RAS) System Architecture, for A-profile architecture (ARM IHI 0100). If FEAT_RAS is not implemented, this instruction executes as a NOP.
11010101000000110010001000011111
                    CRm op2     


extr - extract register - extracts a register from a pair of registers.
.00100111.0.....................
f21      N0Rm   imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <lsb>:For the "32-bit" variant: is the least significant bit position from which to extract, in the range 0 to 31, encoded in the "imms" field.
 <lsb>:For the "64-bit" variant: is the least significant bit position from which to extract, in the range 0 to 63, encoded in the "imms" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

gcsb - guarded control stack barrier - generates a GCSB effect. If FEAT_GCS is not implemented, this instruction executes as a NOP.
11010101000000110010001001111111
                    CRm op2     


gcspopcx - guarded control stack pop and compare exception return record - loads an exception return record from the location indicated by the current Guarded control stack pointer register, compares the loaded values with the current ELR_ELx, SPSR_ELx, and LR, and increments the pointer by the size of a Guarded Control Stack exception return record.
110101010000100001110111101.....
          L  op1CRn CRm op2Rt   


gcspopm - guarded control stack pop - loads the 64-bit doubleword that is pointed to by the current Guarded Control Stack pointer, writes it to the destination register, and increments the current Guarded Control Stack pointer register by the size of a Guarded Control Stack procedure return record.
110101010010101101110111001.....
          L  op1CRn CRm op2Rt   
 <Xt>:64-bit name of the optional general-purpose destination register, encoded in the "Rt" field. Defaults to XZR if absent.

gcspopx - guarded control stack pop exception return record - loads an exception return record from the location indicated by the current Guarded Control Stack pointer register, checks that the record is an exception return record, and increments the pointer by the size of a Guarded Control Stack exception return record.
110101010000100001110111110.....
          L  op1CRn CRm op2Rt   


gcspushm - guarded control stack push - decrements the current Guarded Control Stack pointer register by the size of a Guarded control procedure return record and stores an entry to the Guarded Control Stack.
110101010000101101110111000.....
          L  op1CRn CRm op2Rt   
 <Xt>:64-bit name of the general-purpose source register, encoded in the "Rt" field.

gcspushx - guarded control stack push exception return record - decrements the current Guarded Control Stack pointer register by the size of a Guarded Control Stack exception return record and stores an exception return record to the Guarded Control Stack.
110101010000100001110111100.....
          L  op1CRn CRm op2Rt   


gcsss1 - guarded control stack switch stack 1 - validates that the stack being switched to contains a Valid cap entry, stores an In-progress cap entry to the stack that is being switched to, and sets the current Guarded control stack pointer to the stack that is being switched to. If the instruction generates a synchronous Data Abort exception, Watchpoint exception, GPC exception, or GCS Data Check exception, the value of GCSPR_ELx for the current Exception level is restored to the value held in the register before the instruction was executed.
110101010000101101110111010.....
          L  op1CRn CRm op2Rt   
 <Xt>:64-bit name of the general-purpose source register, encoded in the "Rt" field.

gcsss2 - guarded control stack switch stack 2 - validates that the most recent entry of the Guarded Control Stack being switched to contains an In-progress cap entry, stores a Valid cap entry to the Guarded Control Stack that is being switched from, and sets Xt to the Guarded Control Stack pointer that is being switched from.
110101010010101101110111011.....
          L  op1CRn CRm op2Rt   
 <Xt>:64-bit name of the general-purpose destination register, encoded in the "Rt" field.

gcsstr - guarded control stack store register - stores a doubleword from a register to memory. The address that is used for the store is calculated from a base register.
1101100100011111000011..........
                 opc  Rn   Rt   
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

gcssttr - guarded control stack store register (unprivileged) - stores a doubleword from a register to memory. The address that is used for the store is calculated from a base register. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
1101100100011111000111..........
                 opc  Rn   Rt   
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

gmi - tag mask insert - inserts the tag in the first source register into the excluded set specified in the second source register, writing the new excluded set to the destination register.
10011010110.....000101..........
f S        Rm   opcodeRn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

hint - hint instruction - is for the instruction set space that is reserved for architectural hint instructions. Some encodings described here are not allocated in this revision of the architecture, and behave as NOPs. These encodings might be allocated to other hint functionality in future revisions of the architecture and therefore must not be used by software.
11010101000000110010.......11111
                    CRm op2     
 <imm>:Is a 7-bit unsigned immediate, in the range 0 to 127, encoded in the "CRm:op2" field.

hlt - halt instruction - can generate a Halt Instruction debug event, which causes entry into Debug state. Within a guarded memory region, while PSTATE.BTYPE != 0b00, an HLT instruction that would cause entry into Debug state will not generate a Branch Target exception and will cause entry into Debug state as normal. For more information, see PSTATE.BTYPE.
11010100010................00000
        opcimm16           op2LL
 <imm>:Is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm16" field.

hvc - hypervisor call - causes an exception to EL2. Software executing at EL1 can use this instruction to call the hypervisor to request a service. The HVC instruction is UNDEFINED: On executing an HVC instruction, the PE records the exception as a Hypervisor Call exception in ESR_ELx, using the EC value 0x16, and the value of the immediate argument.
11010100000................00010
        opcimm16           op2LL
 <imm>:Is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm16" field.

ic - instruction cache operation - For more information, see op0==0b01, cache maintenance, TLB maintenance, and address translation instructions.
1101010100001...0111............
          L  op1CRn CRm op2Rt   
 <ic_op>
 op1 | CRm | op2 | <ic_op>
 000 | 0001 | 000 | IALLUIS
 000 | 0101 | 000 | IALLU
 011 | 0101 | 001 | IVAU
 <Xt>:64-bit name of the optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field.

irg - insert random tag - inserts a random Logical Address Tag into the address in the first source register, and writes the result to the destination register. Any tags specified in the optional second source register or in GCR_EL1.Exclude are excluded from the selection of the random Logical Address Tag.
10011010110.....000100..........
f S        Rm   opcodeRn   Rd   
 <Xd|SP>:64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field. Defaults to XZR if absent.

isb - instruction synchronization barrier - flushes the pipeline in the PE and is a context synchronization event. For more information, see Instruction Synchronization Barrier (ISB).
11010101000000110011....11011111
                    CRm  pcRt   
 <option>:Specifies an optional limitation on the barrier operation. Values are:
 <imm>:Is an optional 4-bit unsigned immediate, in the range 0 to 15, defaulting to 15 and encoded in the "CRm" field.

ld64b - single-copy atomic 64-byte load - derives an address from a base register value, loads eight 64-bit doublewords from a memory location, and writes them to consecutive registers. The load starts at register Xt, with the data being read as X(t+7):X(t+6):X(t+5):X(t+4):X(t+3):X(t+2):X(t+1):Xt = Data<511:0>. The data is loaded atomically and is required to be 64-byte aligned. It is IMPLEMENTATION DEFINED which memory locations support this instruction. A memory location that supports LD64B also supports ST64B. For more information, including about the memory types accessible and how the accesses are performed, see Single-copy atomic 64-byte load/store.
1111100000111111110100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Xt>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldadd, ldadda, ldaddal, ldaddl - atomic add on word or doubleword in memory - atomically loads a 32-bit word or 64-bit doubleword from memory, adds the value held in a register to it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1x111000..1.....000000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

ldaddb, ldaddab, ldaddalb, ldaddlb - atomic add on byte in memory - atomically loads an 8-bit byte from memory, adds the value held in a register to it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
00111000..1.....000000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldaddh, ldaddah, ldaddalh, ldaddlh - atomic add on halfword in memory - atomically loads a 16-bit halfword from memory, adds the value held in a register to it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
01111000..1.....000000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldapr - load-acquire rcpc register - derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from the derived address in memory, and writes it to a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: This difference in memory ordering is not described in the pseudocode. For information about addressing modes, see Load/Store addressing modes.
1x01100111000000000010..........
ze       L            Rn   Rt   
1x11100010111111110000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

ldaprb - load-acquire rcpc register byte - derives an address from a base register value, loads a byte from the derived address in memory, zero-extends it and writes it to a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: This difference in memory ordering is not described in the pseudocode. For information about addressing modes, see Load/Store addressing modes.
0011100010111111110000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldaprh - load-acquire rcpc register halfword - derives an address from a base register value, loads a halfword from the derived address in memory, zero-extends it and writes it to a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: This difference in memory ordering is not described in the pseudocode. For information about addressing modes, see Load/Store addressing modes.
0111100010111111110000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldapur - load-acquire rcpc register (unscaled) - calculates an address from a base register and an immediate offset, loads a 32-bit word or 64-bit doubleword from memory, zero-extends it, and writes it to a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: This difference in memory ordering is not described in the pseudocode. For information about addressing modes, see Load/Store addressing modes.
1x011001010.........00..........
ze      pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldapurb - load-acquire rcpc register byte (unscaled) - calculates an address from a base register and an immediate offset, loads a byte from memory, zero-extends it, and writes it to a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: This difference in memory ordering is not described in the pseudocode. For information about addressing modes, see Load/Store addressing modes.
00011001010.........00..........
ze      pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

ldapurh - load-acquire rcpc register halfword (unscaled) - calculates an address from a base register and an immediate offset, loads a halfword from memory, zero-extends it, and writes it to a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: This difference in memory ordering is not described in the pseudocode. For information about addressing modes, see Load/Store addressing modes.
01011001010.........00..........
ze      pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

ldapursb - load-acquire rcpc register signed byte (unscaled) - calculates an address from a base register and an immediate offset, loads a signed byte from memory, sign-extends it, and writes it to a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: This difference in memory ordering is not described in the pseudocode. For information about addressing modes, see Load/Store addressing modes.
000110011x0.........00..........
ze      pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldapursh - load-acquire rcpc register signed halfword (unscaled) - calculates an address from a base register and an immediate offset, loads a signed halfword from memory, sign-extends it, and writes it to a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: This difference in memory ordering is not described in the pseudocode. For information about addressing modes, see Load/Store addressing modes.
010110011x0.........00..........
ze      pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldapursw - load-acquire rcpc register signed word (unscaled) - calculates an address from a base register and an immediate offset, loads a signed word from memory, sign-extends it, and writes it to a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: This difference in memory ordering is not described in the pseudocode. For information about addressing modes, see Load/Store addressing modes.
10011001100.........00..........
ze      pc imm9       Rn   Rt   
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

ldar - load-acquire register - derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from memory, and writes it to a register. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1x00100011011111111111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldarb - load-acquire register byte - derives an address from a base register value, loads a byte from memory, zero-extends it and writes it to a register. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
0000100011011111111111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldarh - load-acquire register halfword - derives an address from a base register value, loads a halfword from memory, zero-extends it, and writes it to a register. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
0100100011011111111111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldatxr - load-acquire unprivileged exclusive register - derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from memory, and writes it to a register. The memory access is atomic. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For information about addressing modes, see Load/Store addressing modes.
1.00100101011111111111..........
 z       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldaxp - load-acquire exclusive pair of registers - derives an address from a base register value, loads two 32-bit words or two 64-bit doublewords from memory, and writes them to two registers. For information on single-copy atomicity and alignment requirements, see Requirements for single-copy atomicity and Alignment of data accesses. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. The instruction also has memory ordering semantics, as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1.001000011111111...............
 z       L Rs   0Rt2  Rn   Rt   
 <Wt1>:32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Wt2>:32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

ldaxr - load-acquire exclusive register - derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from memory, and writes it to a register. The memory access is atomic. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1x00100001011111111111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldaxrb - load-acquire exclusive register byte - derives an address from a base register value, loads a byte from memory, zero-extends it and writes it to a register. The memory access is atomic. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
0000100001011111111111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldaxrh - load-acquire exclusive register halfword - derives an address from a base register value, loads a halfword from memory, zero-extends it and writes it to a register. The memory access is atomic. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
0100100001011111111111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldclr, ldclra, ldclral, ldclrl - atomic bit clear on word or doubleword in memory - atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1x111000..1.....000100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

ldclrb, ldclrab, ldclralb, ldclrlb - atomic bit clear on byte in memory - atomically loads an 8-bit byte from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
00111000..1.....000100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldclrh, ldclrah, ldclralh, ldclrlh - atomic bit clear on halfword in memory - atomically loads a 16-bit halfword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
01111000..1.....000100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldclrp, ldclrpa, ldclrpal, ldclrpl - atomic bit clear on quadword in memory - atomically loads a 128-bit quadword from memory, performs a bitwise AND with the complement of the value held in a pair of registers on it, and stores the result back to memory. The value initially loaded from memory is returned in the same pair of registers.
00011001..1.....000100..........
 S      AR Rt2  3opc  Rn   Rt   
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldeor, ldeora, ldeoral, ldeorl - atomic exclusive-or on word or doubleword in memory - atomically loads a 32-bit word or 64-bit doubleword from memory, performs an exclusive-OR with the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1x111000..1.....001000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

ldeorb, ldeorab, ldeoralb, ldeorlb - atomic exclusive-or on byte in memory - atomically loads an 8-bit byte from memory, performs an exclusive-OR with the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
00111000..1.....001000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldeorh, ldeorah, ldeoralh, ldeorlh - atomic exclusive-or on halfword in memory - atomically loads a 16-bit halfword from memory, performs an exclusive-OR with the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
01111000..1.....001000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldg - load allocation tag - loads an Allocation Tag from a memory address, generates a Logical Address Tag from the Allocation Tag and merges it into the destination register. The address used for the load is calculated from the base register and an immediate signed offset scaled by the Tag Granule.
11011001011.........00..........
        pc imm9     p2Rn   Rt   
 <Xt>:64-bit name of the general-purpose destination register, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0 and encoded in the "imm9" field.

ldgm - load tag multiple - reads a naturally aligned block of N Allocation Tags, where the size of N is identified in GMID_EL1.BS, and writes the Allocation Tag read from address A to the destination register at 4*A<7:4>+3:4*A<7:4>. Bits of the destination register not written with an Allocation Tag are set to 0. is UNDEFINED at EL0. generates an Unchecked access.
1101100111100000000000..........
        pc imm9     p2Rn   Rt   
 <Xt>:64-bit name of the general-purpose destination register, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldiapp - load-acquire rcpc ordered pair of registers - calculates an address from a base register value and an optional offset, loads two 32-bit words or two 64-bit doublewords from memory, and writes them to two registers. For information on single-copy atomicity and alignment requirements, see Requirements for single-copy atomicity and Alignment of data accesses. The instruction also has memory ordering semantics, as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: For information about addressing modes, see Load/Store addressing modes.
1x011001010.....000x10..........
ze       L Rt2  opc2  Rn   Rt   
 <Wt1>:32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Wt2>:32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

ldlar - load loacquire register - loads a 32-bit word or 64-bit doubleword from memory, and writes it to a register. The instruction also has memory ordering semantics as described in Load LOAcquire, Store LORelease. For information about addressing modes, see Load/Store addressing modes.
1x00100011011111011111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldlarb - load loacquire register byte - loads a byte from memory, zero-extends it and writes it to a register. The instruction also has memory ordering semantics as described in Load LOAcquire, Store LORelease. For information about addressing modes, see Load/Store addressing modes.
0000100011011111011111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldlarh - load loacquire register halfword - loads a halfword from memory, zero-extends it, and writes it to a register. The instruction also has memory ordering semantics as described in Load LOAcquire, Store LORelease. For information about addressing modes, see Load/Store addressing modes.
0100100011011111011111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldnp - load pair of registers, with non-temporal hint - calculates an address from a base register value and an immediate offset, loads two 32-bit words or two 64-bit doublewords from memory, and writes them to two registers. For information about addressing modes, see Load/Store addressing modes. For information about non-temporal pair instructions, see Load/Store non-temporal pair.
x010100001......................
pc   R   Limm7   Rt2  Rn   Rt   
 <Wt1>:32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Wt2>:32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "32-bit" variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.
 <imm>:For the "64-bit" variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

ldp - load pair of registers - calculates an address from a base register value and an immediate offset, loads two 32-bit words or two 64-bit doublewords from memory, and writes them to two registers. For information about addressing modes, see Load/Store addressing modes.
x010100011......................
pc   R   Limm7   Rt2  Rn   Rt   
x010100111......................
pc   R   Limm7   Rt2  Rn   Rt   
x010100101......................
pc   R   Limm7   Rt2  Rn   Rt   
 <Wt1>:32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Wt2>:32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "32-bit Post-index" and "32-bit Pre-index" variants: is the signed immediate byte offset, a multiple of 4 in the range -256 to 252, encoded in the "imm7" field as <imm>/4.
 <imm>:For the "64-bit Post-index" and "64-bit Pre-index" variants: is the signed immediate byte offset, a multiple of 8 in the range -512 to 504, encoded in the "imm7" field as <imm>/8.
 <imm>:For the "32-bit Signed offset" variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.
 <imm>:For the "64-bit Signed offset" variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

ldpsw - load pair of registers signed word - calculates an address from a base register value and an immediate offset, loads two 32-bit words from memory, sign-extends them, and writes them to two registers. For information about addressing modes, see Load/Store addressing modes.
0110100011......................
pc   R   Limm7   Rt2  Rn   Rt   
0110100111......................
pc   R   Limm7   Rt2  Rn   Rt   
0110100101......................
pc   R   Limm7   Rt2  Rn   Rt   
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Post-index" and "Pre-index" variants: is the signed immediate byte offset, a multiple of 4 in the range -256 to 252, encoded in the "imm7" field as <imm>/4.
 <imm>:For the "Signed offset" variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.

ldr (immediate) - load register (immediate) - loads a word or doubleword from memory and writes it to a register. The address that is used for the load is calculated from a base register and an immediate offset. For information about addressing modes, see Load/Store addressing modes. The Unsigned offset variant scales the immediate offset value by the size of the value accessed before adding it to the base register value.
1x111000010.........01..........
ze   R  pc imm9       Rn   Rt   
1x111000010.........11..........
ze   R  pc imm9       Rn   Rt   
1x11100101......................
ze   R  pcimm12       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <pimm>:For the "32-bit" variant: is the optional positive immediate byte offset, a multiple of 4 in the range 0 to 16380, defaulting to 0 and encoded in the "imm12" field as <pimm>/4.
 <pimm>:For the "64-bit" variant: is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as <pimm>/8.

ldr (literal) - load register (literal) - calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about addressing modes, see Load/Store addressing modes.
0x011000........................
pc   R  imm19              Rt   
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <label>:program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

ldr (register) - load register (register) - calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted and extended. For information about addressing modes, see Load/Store addressing modes.
1x111000011.........10..........
ze   R  pc Rm   ionS  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Wm>:When 
 <Xm>:When 
 <extend>
 option | <extend>
 010 | UXTW
 011 | LSL
 110 | SXTW
 111 | SXTX
 <amount>
 S | <amount>
 0 | #0
 1 | #2
 <amount>
 S | <amount>
 0 | #0
 1 | #3
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldraa, ldrab - load register, with pointer authentication - authenticates an address from a base register using a modifier of zero and the specified key, adds an immediate offset to the authenticated address, and loads a 64-bit doubleword from memory at this resulting address into a register. Key A is used for LDRAA. Key B is used for LDRAB. If the authentication passes, the PE behaves the same as for an LDR instruction. For information on behavior if the authentication fails, see Faulting on pointer authentication. The authenticated address is not written back to the base register, unless the pre-indexed variant of the instruction is used. In this case, the address that is written back to the base register does not include the pointer authentication code. For information about addressing modes, see Load/Store addressing modes.
11111000..1..........1..........
ze   R  MS imm9     W Rn   Rt   
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, a multiple of 8 in the range -4096 to 4088, defaulting to 0 and encoded in the "S:imm9" field as <simm>/8.

ldrb (immediate) - load register byte (immediate) - loads a byte from memory, zero-extends it, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset.  For information about addressing modes, see Load/Store addressing modes.
00111000010.........01..........
ze   R  pc imm9       Rn   Rt   
00111000010.........11..........
ze   R  pc imm9       Rn   Rt   
0011100101......................
ze   R  pcimm12       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.
 <pimm>:optional positive immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.

ldrb (register) - load register byte (register) - calculates an address from a base register value and an offset register value, loads a byte from memory, zero-extends it, and writes it to a register. For information about addressing modes, see Load/Store addressing modes.
00111000011.........10..........
ze   R  pc Rm   ionS  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Wm>:When 
 <Xm>:When 
 <extend>
 option | <extend>
 010 | UXTW
 110 | SXTW
 111 | SXTX
 <amount>:index shift amount, it must be 

ldrh (immediate) - load register halfword (immediate) - loads a halfword from memory, zero-extends it, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset. For information about addressing modes, see Load/Store addressing modes.
01111000010.........01..........
ze   R  pc imm9       Rn   Rt   
01111000010.........11..........
ze   R  pc imm9       Rn   Rt   
0111100101......................
ze   R  pcimm12       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.
 <pimm>:optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0 and encoded in the "imm12" field as <pimm>/2.

ldrh (register) - load register halfword (register) - calculates an address from a base register value and an offset register value, loads a halfword from memory, zero-extends it, and writes it to a register. For information about addressing modes, see Load/Store addressing modes.
01111000011.........10..........
ze   R  pc Rm   ionS  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Wm>:When 
 <Xm>:When 
 <extend>
 option | <extend>
 010 | UXTW
 011 | LSL
 110 | SXTW
 111 | SXTX
 <amount>
 S | <amount>
 0 | #0
 1 | #1

ldrsb (immediate) - load register signed byte (immediate) - loads a byte from memory, sign-extends it to either 32 bits or 64 bits, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset. For information about addressing modes, see Load/Store addressing modes.
001110001x0.........01..........
ze   R  pc imm9       Rn   Rt   
001110001x0.........11..........
ze   R  pc imm9       Rn   Rt   
001110011x......................
ze   R  pcimm12       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <pimm>:optional positive immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.

ldrsb (register) - load register signed byte (register) - calculates an address from a base register value and an offset register value, loads a byte from memory, sign-extends it, and writes it to a register. For information about addressing modes, see Load/Store addressing modes.
001110001x1.........10..........
ze   R  pc Rm   ionS  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Wm>:When 
 <Xm>:When 
 <extend>
 option | <extend>
 010 | UXTW
 110 | SXTW
 111 | SXTX
 <amount>:index shift amount, it must be 
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldrsh (immediate) - load register signed halfword (immediate) - loads a halfword from memory, sign-extends it to 32 bits or 64 bits, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset. For information about addressing modes, see Load/Store addressing modes.
011110001x0.........01..........
ze   R  pc imm9       Rn   Rt   
011110001x0.........11..........
ze   R  pc imm9       Rn   Rt   
011110011x......................
ze   R  pcimm12       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <pimm>:optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0 and encoded in the "imm12" field as <pimm>/2.

ldrsh (register) - load register signed halfword (register) - calculates an address from a base register value and an offset register value, loads a halfword from memory, sign-extends it, and writes it to a register. For information about addressing modes, see Load/Store addressing modes.
011110001x1.........10..........
ze   R  pc Rm   ionS  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Wm>:When 
 <Xm>:When 
 <extend>
 option | <extend>
 010 | UXTW
 011 | LSL
 110 | SXTW
 111 | SXTX
 <amount>
 S | <amount>
 0 | #0
 1 | #1
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldrsw (immediate) - load register signed word (immediate) - loads a word from memory, sign-extends it to 64 bits, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset. For information about addressing modes, see Load/Store addressing modes.
10111000100.........01..........
ze   R  pc imm9       Rn   Rt   
10111000100.........11..........
ze   R  pc imm9       Rn   Rt   
1011100110......................
ze   R  pcimm12       Rn   Rt   
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.
 <pimm>:optional positive immediate byte offset, a multiple of 4 in the range 0 to 16380, defaulting to 0 and encoded in the "imm12" field as <pimm>/4.

ldrsw (literal) - load register signed word (literal) - calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about addressing modes, see Load/Store addressing modes.
10011000........................
pc   R  imm19              Rt   
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <label>:program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.

ldrsw (register) - load register signed word (register) - calculates an address from a base register value and an offset register value, loads a word from memory, sign-extends it to form a 64-bit value, and writes it to a register. The offset register value can be shifted left by 0 or 2 bits. For information about addressing modes, see Load/Store addressing modes.
10111000101.........10..........
ze   R  pc Rm   ionS  Rn   Rt   
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Wm>:When 
 <Xm>:When 
 <extend>
 option | <extend>
 010 | UXTW
 011 | LSL
 110 | SXTW
 111 | SXTX
 <amount>
 S | <amount>
 0 | #0
 1 | #2

ldset, ldseta, ldsetal, ldsetl - atomic bit set on word or doubleword in memory - atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise OR with the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1x111000..1.....001100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

ldsetb, ldsetab, ldsetalb, ldsetlb - atomic bit set on byte in memory - atomically loads an 8-bit byte from memory, performs a bitwise OR with the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
00111000..1.....001100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldseth, ldsetah, ldsetalh, ldsetlh - atomic bit set on halfword in memory - atomically loads a 16-bit halfword from memory, performs a bitwise OR with the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
01111000..1.....001100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldsetp, ldsetpa, ldsetpal, ldsetpl - atomic bit set on quadword in memory - atomically loads a 128-bit quadword from memory, performs a bitwise OR with the value held in a pair of registers on it, and stores the result back to memory. The value initially loaded from memory is returned in the same pair of registers.
00011001..1.....001100..........
 S      AR Rt2  3opc  Rn   Rt   
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldsmax, ldsmaxa, ldsmaxal, ldsmaxl - atomic signed maximum on word or doubleword in memory - atomically loads a 32-bit word or 64-bit doubleword from memory, compares it against the value held in a register, and stores the larger value back to memory, treating the values as signed numbers. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1x111000..1.....010000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

ldsmaxb, ldsmaxab, ldsmaxalb, ldsmaxlb - atomic signed maximum on byte in memory - atomically loads an 8-bit byte from memory, compares it against the value held in a register, and stores the larger value back to memory, treating the values as signed numbers. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
00111000..1.....010000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldsmaxh, ldsmaxah, ldsmaxalh, ldsmaxlh - atomic signed maximum on halfword in memory - atomically loads a 16-bit halfword from memory, compares it against the value held in a register, and stores the larger value back to memory, treating the values as signed numbers. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
01111000..1.....010000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldsmin, ldsmina, ldsminal, ldsminl - atomic signed minimum on word or doubleword in memory - atomically loads a 32-bit word or 64-bit doubleword from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as signed numbers. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1x111000..1.....010100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

ldsminb, ldsminab, ldsminalb, ldsminlb - atomic signed minimum on byte in memory - atomically loads an 8-bit byte from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as signed numbers. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
00111000..1.....010100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldsminh, ldsminah, ldsminalh, ldsminlh - atomic signed minimum on halfword in memory - atomically loads a 16-bit halfword from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as signed numbers. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
01111000..1.....010100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldtadd, ldtadda, ldtaddal, ldtaddl - atomic add unprivileged - atomically loads a 32-bit word or 64-bit doubleword from memory, adds the value held in a register to it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
0.011001..1.....000001..........
 z      AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

ldtclr, ldtclra, ldtclral, ldtclrl - atomic bit clear unprivileged - atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
0.011001..1.....000101..........
 z      AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

ldtnp - load unprivileged pair of registers, with non-temporal hint - calculates an address from a base register value and an immediate offset, loads two 64-bit doublewords from memory, and writes them to two registers. For information about addressing modes, see Load/Store addressing modes. For information about non-temporal pair instructions, see Load/Store non-temporal pair. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
1110100001......................
pc   R   Limm7   Rt2  Rn   Rt   
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.

ldtp - load unprivileged pair of registers - calculates an address from a base register value and an immediate offset, loads two 64-bit doublewords from memory, and writes them to two registers. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For information about addressing modes, see Load/Store addressing modes.
1110100011......................
pc   R   Limm7   Rt2  Rn   Rt   
1110100111......................
pc   R   Limm7   Rt2  Rn   Rt   
1110100101......................
pc   R   Limm7   Rt2  Rn   Rt   
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Post-index" and "Pre-index" variants: is the signed immediate byte offset, a multiple of 8 in the range -512 to 504, encoded in the "imm7" field as <imm>/8.
 <imm>:For the "Signed offset" variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.

ldtr - load register (unprivileged) - loads a word or doubleword from memory, and writes it to a register. The address that is used for the load is calculated from a base register and an immediate offset. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For information about addressing modes, see Load/Store addressing modes.
1x111000010.........10..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldtrb - load register byte (unprivileged) - loads a byte from memory, zero-extends it, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For information about addressing modes, see Load/Store addressing modes.
00111000010.........10..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

ldtrh - load register halfword (unprivileged) - loads a halfword from memory, zero-extends it, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For information about addressing modes, see Load/Store addressing modes.
01111000010.........10..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

ldtrsb - load register signed byte (unprivileged) - loads a byte from memory, sign-extends it to 32 bits or 64 bits, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For information about addressing modes, see Load/Store addressing modes.
001110001x0.........10..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldtrsh - load register signed halfword (unprivileged) - loads a halfword from memory, sign-extends it to 32 bits or 64 bits, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For information about addressing modes, see Load/Store addressing modes.
011110001x0.........10..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldtrsw - load register signed word (unprivileged) - loads a word from memory, sign-extends it to 64 bits, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For information about addressing modes, see Load/Store addressing modes.
10111000100.........10..........
ze   R  pc imm9       Rn   Rt   
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

ldtset, ldtseta, ldtsetal, ldtsetl - atomic bit set unprivileged - atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise OR with the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
0.011001..1.....001101..........
 z      AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

ldtxr - load unprivileged exclusive register - derives an address from a base register value, loads a 32-bit word or a 64-bit doubleword from memory, and writes it to a register. The memory access is atomic. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For information about addressing modes, see Load/Store addressing modes.
1.00100101011111011111..........
 z       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldumax, ldumaxa, ldumaxal, ldumaxl - atomic unsigned maximum on word or doubleword in memory - atomically loads a 32-bit word or 64-bit doubleword from memory, compares it against the value held in a register, and stores the larger value back to memory, treating the values as unsigned numbers. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1x111000..1.....011000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

ldumaxb, ldumaxab, ldumaxalb, ldumaxlb - atomic unsigned maximum on byte in memory - atomically loads an 8-bit byte from memory, compares it against the value held in a register, and stores the larger value back to memory, treating the values as unsigned numbers. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
00111000..1.....011000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldumaxh, ldumaxah, ldumaxalh, ldumaxlh - atomic unsigned maximum on halfword in memory - atomically loads a 16-bit halfword from memory, compares it against the value held in a register, and stores the larger value back to memory, treating the values as unsigned numbers. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
01111000..1.....011000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldumin, ldumina, lduminal, lduminl - atomic unsigned minimum on word or doubleword in memory - atomically loads a 32-bit word or 64-bit doubleword from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as unsigned numbers. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1x111000..1.....011100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

lduminb, lduminab, lduminalb, lduminlb - atomic unsigned minimum on byte in memory - atomically loads an 8-bit byte from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as unsigned numbers. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
00111000..1.....011100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

lduminh, lduminah, lduminalh, lduminlh - atomic unsigned minimum on halfword in memory - atomically loads a 16-bit halfword from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as unsigned numbers. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
01111000..1.....011100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldur - load register (unscaled) - calculates an address from a base register and an immediate offset, loads a 32-bit word or 64-bit doubleword from memory, zero-extends it, and writes it to a register. For information about addressing modes, see Load/Store addressing modes.
1x111000010.........00..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldurb - load register byte (unscaled) - calculates an address from a base register and an immediate offset, loads a byte from memory, zero-extends it, and writes it to a register. For information about addressing modes, see Load/Store addressing modes.
00111000010.........00..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

ldurh - load register halfword (unscaled) - calculates an address from a base register and an immediate offset, loads a halfword from memory, zero-extends it, and writes it to a register. For information about addressing modes, see Load/Store addressing modes.
01111000010.........00..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

ldursb - load register signed byte (unscaled) - calculates an address from a base register and an immediate offset, loads a signed byte from memory, sign-extends it, and writes it to a register. For information about addressing modes, see Load/Store addressing modes.
001110001x0.........00..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldursh - load register signed halfword (unscaled) - calculates an address from a base register and an immediate offset, loads a signed halfword from memory, sign-extends it, and writes it to a register. For information about addressing modes, see Load/Store addressing modes.
011110001x0.........00..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldursw - load register signed word (unscaled) - calculates an address from a base register and an immediate offset, loads a signed word from memory, sign-extends it, and writes it to a register. For information about addressing modes, see Load/Store addressing modes.
10111000100.........00..........
ze   R  pc imm9       Rn   Rt   
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

ldxp - load exclusive pair of registers - derives an address from a base register value, loads two 32-bit words or two 64-bit doublewords from memory, and writes them to two registers. For information on single-copy atomicity and alignment requirements, see Requirements for single-copy atomicity and Alignment of data accesses. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. For information about addressing modes, see Load/Store addressing modes.
1.001000011111110...............
 z       L Rs   0Rt2  Rn   Rt   
 <Wt1>:32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Wt2>:32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

ldxr - load exclusive register - derives an address from a base register value, loads a 32-bit word or a 64-bit doubleword from memory, and writes it to a register. The memory access is atomic. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. For information about addressing modes, see Load/Store addressing modes.
1x00100001011111011111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

ldxrb - load exclusive register byte - derives an address from a base register value, loads a byte from memory, zero-extends it and writes it to a register. The memory access is atomic. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. For information about addressing modes, see Load/Store addressing modes.
0000100001011111011111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldxrh - load exclusive register halfword - derives an address from a base register value, loads a halfword from memory, zero-extends it and writes it to a register. The memory access is atomic. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. For information about addressing modes, see Load/Store addressing modes.
0100100001011111011111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

lsl (immediate) - logical shift left (immediate) - shifts a register value left by an immediate number of bits, shifting in zeros, and writes the result to the destination register.
.10100110.......................
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <shift>:For the "32-bit" variant: is the shift amount, in the range 0 to 31.
 <shift>:For the "64-bit" variant: is the shift amount, in the range 0 to 63.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

lsl (register) - logical shift left (register) - shifts a register value left by a variable number of bits, shifting in zeros, and writes the result to the destination register. The value of the second source register modulo the register size in bits gives the number of bits by which the first source register is left-shifted.
.0011010110.....001000..........
f S        Rm       p2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits, encoded in the "Rm" field.

lslv - logical shift left variable - shifts a register value left by a variable number of bits, shifting in zeros, and writes the result to the destination register. The value of the second source register modulo the register size in bits gives the number of bits by which the first source register is left-shifted.
.0011010110.....001000..........
f S        Rm       p2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits, encoded in the "Rm" field.

lsr (immediate) - logical shift right (immediate) - shifts a register value right by an immediate number of bits, shifting in zeros, and writes the result to the destination register.
.10100110.......x11111..........
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <shift>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, encoded in the "immr" field.
 <shift>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, encoded in the "immr" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

lsr (register) - logical shift right (register) - shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The value of the second source register modulo the register size in bits gives the number of bits by which the first source register is right-shifted.
.0011010110.....001001..........
f S        Rm       p2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits, encoded in the "Rm" field.

lsrv - logical shift right variable - shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The value of the second source register modulo the register size in bits gives the number of bits by which the first source register is right-shifted.
.0011010110.....001001..........
f S        Rm       p2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits, encoded in the "Rm" field.

madd - multiply-add - multiplies two register values, adds a third register value, and writes the result to the destination register.
.0011011000.....0...............
f54     p31Rm   0Ra   Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.
 <Wa>:32-bit name of the third general-purpose source register holding the addend, encoded in the "Ra" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.
 <Xa>:64-bit name of the third general-purpose source register holding the addend, encoded in the "Ra" field.

maddpt - multiply-add checked pointer - multiplies two register values, adds a third register value, and writes the result to the destination register. The intermediate product is treated as the offset. If the operation would have generated a result where the most significant 8 bits of the result register differ from the most significant 8 bits of the base register, then the result is modified such that it is likely to be non-canonical when used as an address. If the intermediate product cannot be correctly represented as a 64-bit two's complement value, then the result is modified such that it is likely to be non-canonical when used as an address.
10011011011.....0...............
f54     p31Rm   0Ra   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.
 <Xa>:64-bit name of the third general-purpose source register holding the addend, encoded in the "Ra" field.

mneg - multiply-negate - multiplies two register values, negates the product, and writes the result to the destination register.
.0011011000.....111111..........
f54     p31Rm   0Ra   Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.

mov (bitmask immediate) - move bitmask immediate value - writes a bitmask immediate value to a register.
.01100100.............11111.....
fpc      Nimmr  imms  Rn   Rd   
 <Wd|WSP>:32-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <imm>:For the "32-bit" variant: is the bitmask immediate, encoded in "imms:immr", but excluding values which could be encoded by MOVZ or MOVN.
 <imm>:For the "64-bit" variant: is the bitmask immediate, encoded in "N:imms:immr", but excluding values which could be encoded by MOVZ or MOVN.
 <Xd|SP>:64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.

mov (inverted wide immediate) - move inverted wide immediate value - moves an inverted 16-bit immediate value to a register.
.00100101.......................
fpc      hwimm16           Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <imm>:For the "32-bit" variant: is a 32-bit immediate, the bitwise inverse of which can be encoded in "imm16:hw", but excluding 
 <imm>:For the "64-bit" variant: is a 64-bit immediate, the bitwise inverse of which can be encoded in "imm16:hw".
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.

mov (register) - move register value - copies the value in a source register to the destination register.
.0101010000.....00000011111.....
fpc     ftNRm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wm>:32-bit name of the general-purpose source register, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xm>:64-bit name of the general-purpose source register, encoded in the "Rm" field.

mov (to/from sp) - move register value to or from sp - copies the value of a register to or from the stack pointer.
.001000100000000000000..........
fpS      himm12       Rn   Rd   
 <Wd|WSP>:32-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Wn|WSP>:32-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.
 <Xd|SP>:64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.

mov (wide immediate) - move wide immediate value - moves a 16-bit immediate value to a register.
.10100101.......................
fpc      hwimm16           Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <imm>:For the "32-bit" variant: is a 32-bit immediate which can be encoded in "imm16:hw".
 <imm>:For the "64-bit" variant: is a 64-bit immediate which can be encoded in "imm16:hw".
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.

movk - move wide with keep - moves an optionally-shifted 16-bit immediate value into a register, keeping other bits unchanged.
.11100101.......................
fpc      hwimm16           Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <imm>:16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm16" field.
 <shift>:For the "32-bit" variant: is the amount by which to shift the immediate left, either 0 (the default) or 16, encoded in the "hw" field as <shift>/16.
 <shift>:For the "64-bit" variant: is the amount by which to shift the immediate left, either 0 (the default), 16, 32 or 48, encoded in the "hw" field as <shift>/16.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.

movn - move wide with not - moves the inverse of an optionally-shifted 16-bit immediate value to a register.
.00100101.......................
fpc      hwimm16           Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <imm>:16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm16" field.
 <shift>:For the "32-bit" variant: is the amount by which to shift the immediate left, either 0 (the default) or 16, encoded in the "hw" field as <shift>/16.
 <shift>:For the "64-bit" variant: is the amount by which to shift the immediate left, either 0 (the default), 16, 32 or 48, encoded in the "hw" field as <shift>/16.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.

movz - move wide with zero - moves an optionally-shifted 16-bit immediate value to a register.
.10100101.......................
fpc      hwimm16           Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <imm>:16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm16" field.
 <shift>:For the "32-bit" variant: is the amount by which to shift the immediate left, either 0 (the default) or 16, encoded in the "hw" field as <shift>/16.
 <shift>:For the "64-bit" variant: is the amount by which to shift the immediate left, either 0 (the default), 16, 32 or 48, encoded in the "hw" field as <shift>/16.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.

mrrs - move system register to two adjacent general-purpose registers - allows the PE to read an AArch64 128-bit System register into two adjacent 64-bit general-purpose registers.
110101010111....................
          L 0op1CRn CRm op2Rt   
 <Xt>:64-bit name of the first general-purpose destination register, encoded in the "Rt" field.
 <Xt+1>:64-bit name of the second general-purpose destination register, encoded as "Rt" +1.
 <systemreg>:Is a System register name, encoded in "o0:op1:CRn:CRm:op2".
 <op0>
 o0 | <op0>
 0 | 2
 1 | 3
 <op1>:Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.
 <Cn>:Is a name 'Cn', with 'n' in the range 0 to 15, encoded in the "CRn" field.
 <Cm>:Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.
 <op2>:Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.

mrs - move system register to general-purpose register - allows the PE to read an AArch64 System register into a general-purpose register.
110101010011....................
          L 0op1CRn CRm op2Rt   
 <Xt>:64-bit name of the general-purpose destination register, encoded in the "Rt" field.
 <systemreg>:Is a System register name, encoded in "o0:op1:CRn:CRm:op2".
 <op0>
 o0 | <op0>
 0 | 2
 1 | 3
 <op1>:Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.
 <Cn>:Is a name 'Cn', with 'n' in the range 0 to 15, encoded in the "CRn" field.
 <Cm>:Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.
 <op2>:Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.

msr (immediate) - move immediate value to special register - moves an immediate value to selected bits of the PSTATE. For more information, see Process state, PSTATE. The bits that can be written by this instruction are: If FEAT_MTE is implemented and FEAT_MTE2 is not implemented, it is IMPLEMENTATION DEFINED whether writes to PSTATE.TCO by this instruction are ignored.
1101010100000...0100.......11111
             op1    CRm op2Rt   
 <pstatefield>
 CRm | op1 | op2 | <pstatefield> | Architectural Feature
 xxxx | 000 | 011 | UAO | 
                  
 xxxx | 000 | 100 | PAN | 
                  
 xxxx | 000 | 101 | SPSel | 
 xxxx | 000 | 11x | RESERVED | 
 000x | 001 | 000 | ALLINT | 
                  
 xxxx | 001 | 001 | RESERVED | 
 xxxx | 001 | 01x | RESERVED | 
 xxxx | 001 | 1xx | RESERVED | 
 xxxx | 010 | xxx | RESERVED | 
 xxxx | 011 | 000 | RESERVED | 
 xxxx | 011 | 001 | SSBS | 
                  
 xxxx | 011 | 010 | DIT | 
                  
 000x | 011 | 011 | RESERVED | 
 xxxx | 011 | 100 | TCO | 
                  
 xxxx | 011 | 101 | RESERVED | 
 xxxx | 011 | 110 | DAIFSet | 
 xxxx | 011 | 111 | DAIFClr | 
 xxxx | 1xx | xxx | RESERVED | 
 001x | 001 | 000 | PM | 
                  
 001x | 011 | 011 | SVCRSM | 
                  
 01xx | 001 | 000 | RESERVED | 
 010x | 011 | 011 | SVCRZA | 
                  
 011x | 011 | 011 | SVCRSMZA | 
                  
 1xxx | 001 | 000 | RESERVED | 
 1xxx | 011 | 011 | RESERVED | 
 For the SMSTART and SMSTOP aliases, this is encoded in "CRm<2:1>", where 
 <imm>:Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the "CRm" field. Restricted to the range 0 to 1, encoded in "CRm<0>", when <pstatefield> is ALLINT, PM, SVCRSM, SVCRSMZA, or SVCRZA.

msr (register) - move general-purpose register to system register - allows the PE to write an AArch64 System register from a general-purpose register.
110101010001....................
          L 0op1CRn CRm op2Rt   
 <systemreg>:Is a System register name, encoded in "o0:op1:CRn:CRm:op2".
 <op0>
 o0 | <op0>
 0 | 2
 1 | 3
 <op1>:Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.
 <Cn>:Is a name 'Cn', with 'n' in the range 0 to 15, encoded in the "CRn" field.
 <Cm>:Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.
 <op2>:Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.
 <Xt>:64-bit name of the general-purpose source register, encoded in the "Rt" field.

msrr - move two adjacent general-purpose registers to system register - allows the PE to write an AArch64 128-bit System register from two adjacent 64-bit general-purpose registers.
110101010101....................
          L 0op1CRn CRm op2Rt   
 <systemreg>:Is a System register name, encoded in "o0:op1:CRn:CRm:op2".
 <op0>
 o0 | <op0>
 0 | 2
 1 | 3
 <op1>:Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.
 <Cn>:Is a name 'Cn', with 'n' in the range 0 to 15, encoded in the "CRn" field.
 <Cm>:Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.
 <op2>:Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.
 <Xt>:64-bit name of the first general-purpose source register, encoded in the "Rt" field.
 <Xt+1>:64-bit name of the second  general-purpose source register, encoded as "Rt" +1.

msub - multiply-subtract - multiplies two register values, subtracts the product from a third register value, and writes the result to the destination register.
.0011011000.....1...............
f54     p31Rm   0Ra   Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.
 <Wa>:32-bit name of the third general-purpose source register holding the minuend, encoded in the "Ra" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.
 <Xa>:64-bit name of the third general-purpose source register holding the minuend, encoded in the "Ra" field.

msubpt - multiply-subtract checked pointer - multiplies two register values, subtracts the product from a third register value, and writes the result to the destination register. The intermediate product is treated as the offset. If the operation would have generated a result where the most significant 8 bits of the result register differ from the most significant 8 bits of the base register, then the result is modified such that it is likely to be non-canonical when used as an address. If the intermediate product cannot be correctly represented as a 64-bit two's complement value, then the result is modified such that it is likely to be non-canonical when used as an address.
10011011011.....1...............
f54     p31Rm   0Ra   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.
 <Xa>:64-bit name of the third general-purpose source register holding the minuend, encoded in the "Ra" field.

mul - multiply - multiplies two register values and writes the result to the destination register.
.0011011000.....011111..........
f54     p31Rm   0Ra   Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.

mvn - bitwise not - writes the bitwise inverse of a register value to the destination register.
.0101010..1...........11111.....
fpc     ftNRm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wm>:32-bit name of the general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | ROR
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xm>:64-bit name of the general-purpose source register, encoded in the "Rm" field.

neg (shifted register) - negate (shifted register) - negates an optionally-shifted register value, and writes the result to the destination register.
.1001011..0...........11111.....
fpS     ft Rm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wm>:32-bit name of the general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | RESERVED
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xm>:64-bit name of the general-purpose source register, encoded in the "Rm" field.

negs - negate, setting flags - negates an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.
.1101011..0...........11111!= 11111!= 11111!= 11111!= 11111!= 11111
fpS     ft Rm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wm>:32-bit name of the general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | RESERVED
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xm>:64-bit name of the general-purpose source register, encoded in the "Rm" field.

ngc - negate with carry - negates the sum of a register value and the value of NOT (Carry flag), and writes the result to the destination register.
.1011010000.....00000011111.....
fpS        Rm         Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wm>:32-bit name of the general-purpose source register, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xm>:64-bit name of the general-purpose source register, encoded in the "Rm" field.

ngcs - negate with carry, setting flags - negates the sum of a register value and the value of NOT (Carry flag), and writes the result to the destination register. It updates the condition flags based on the result.
.1111010000.....00000011111.....
fpS        Rm         Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wm>:32-bit name of the general-purpose source register, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xm>:64-bit name of the general-purpose source register, encoded in the "Rm" field.

nop - no operation - does nothing, other than advance the value of the program counter by 4. can be used for instruction alignment purposes.
11010101000000110010000000011111
                    CRm op2     


orn (shifted register) - bitwise or not (shifted register) - performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register.
.0101010..1.....................
fpc     ftNRm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | ROR
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

orr (immediate) - bitwise or (immediate) - performs a bitwise (inclusive) OR of a register value and an immediate value, and writes the result to the destination register.
.01100100.......................
fpc      Nimmr  imms  Rn   Rd   
 <Wd|WSP>:32-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <imm>:For the "32-bit" variant: is the bitmask immediate, encoded in "imms:immr".
 <imm>:For the "64-bit" variant: is the bitmask immediate, encoded in "N:imms:immr".
 <Xd|SP>:64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

orr (shifted register) - bitwise or (shifted register) - performs a bitwise (inclusive) OR of a register value and an optionally-shifted register value, and writes the result to the destination register.
.0101010..0.....................
fpc     ftNRm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | ROR
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

pacda, pacdza - pointer authentication code for data address, using key a - computes and inserts a Pointer Authentication Code for a data address, using a modifier and key A. The address is in the general-purpose register that is specified by <Xd>. The modifier is:
110110101100000100.010..........
f S        code2  Z   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.

pacdb, pacdzb - pointer authentication code for data address, using key b - computes and inserts a Pointer Authentication Code for a data address, using a modifier and key B. The address is in the general-purpose register that is specified by <Xd>. The modifier is:
110110101100000100.011..........
f S        code2  Z   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.

pacga - pointer authentication code, using generic key - computes the Pointer Authentication Code for a 64-bit value in the first source register, using a modifier in the second source register, and the generic key. The computed Pointer Authentication Code is written to the most significant 32 bits of the destination register, and the least significant 32 bits of the destination register are set to zero.
10011010110.....001100..........
f S        Rm   opcodeRn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm|SP>:64-bit name of the second general-purpose source register or stack pointer, encoded in the "Rm" field.

pacia, pacia1716, paciasp, paciaz, paciza - pointer authentication code for instruction address, using key a - computes and inserts a Pointer Authentication Code for an instruction address, using a modifier and key A. The address is: The modifier is: If FEAT_PAuth_LR is implemented and PSTATE.PACM is 1, then PACIA1716 and PACIASP include a second modifier that is: A PACIASP instruction has an implicit BTI instruction. The implicit BTI instruction of a PACIASP instruction is always compatible with PSTATE.BTYPE == 0b01 and PSTATE.BTYPE == 0b10. Controls in SCTLR_ELx configure whether the implicit BTI instruction of a PACIASP instruction is compatible with PSTATE.BTYPE == 0b11. For more information, see PSTATE.BTYPE.
110110101100000100.000..........
f S        code2  Z   Rn   Rd   
1101010100000011001000x100x11111
                    CRm op2     
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.

pacia171615 - pointer authentication code for instruction address, using key a - computes and inserts a pointer authentication code for an instruction address, using two modifiers and key A. The address is in X17. The 64-bit value of modifier1 is the value in X16. The 64-bit value of modifier2 is the value in X15.
11011010110000011000101111111110
f S        code2opcodeRn   Rd   


paciasppc - pointer authentication code for return address, using key a - computes and inserts a Pointer Authentication Code for an instruction address, using two modifiers and key A. The address is in X30. The first modifier is in SP. The second modifier is the value of PC. A PACIASPPC instruction has an implicit BTI instruction. The implicit BTI instruction of a PACIASPPC instruction is always compatible with PSTATE.BTYPE == 0b01 and PSTATE.BTYPE == 0b10. Controls in SCTLR_ELx configure whether the implicit BTI instruction of a PACIASPPC instruction is compatible with PSTATE.BTYPE == 0b11. For more information, see PSTATE.BTYPE.
11011010110000011010001111111110
f S        code2opcodeRn   Rd   


pacib, pacib1716, pacibsp, pacibz, pacizb - pointer authentication code for instruction address, using key b - computes and inserts a Pointer Authentication Code for an instruction address, using a modifier and key B. The address is: The modifier is: If FEAT_PAuth_LR is implemented and PSTATE.PACM is 1, then PACIB1716 and PACIBSP include a second modifier that is: A PACIBSP instruction has an implicit BTI instruction. The implicit BTI instruction of a PACIBSP instruction is always compatible with PSTATE.BTYPE == 0b01 and PSTATE.BTYPE == 0b10. Controls in SCTLR_ELx configure whether the implicit BTI instruction of a PACIBSP instruction is compatible with PSTATE.BTYPE == 0b11. For more information, see PSTATE.BTYPE.
110110101100000100.001..........
f S        code2  Z   Rn   Rd   
1101010100000011001000x101x11111
                    CRm op2     
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.

pacib171615 - pointer authentication code for instruction address, using key b - computes and inserts a pointer authentication code for an instruction address, using two modifiers and key B. The address is in X17. The 64-bit value of modifier1 is the value in X16. The 64-bit value of modifier2 is the value in X15.
11011010110000011000111111111110
f S        code2opcodeRn   Rd   


pacibsppc - pointer authentication code for return address, using key b - computes and inserts a Pointer Authentication Code for an instruction address, using two modifiers and key B. The address is in X30. The first modifier is in SP. The second modifier is the value of PC. A PACIBSPPC instruction has an implicit BTI instruction. The implicit BTI instruction of a PACIBSPPC instruction is always compatible with PSTATE.BTYPE == 0b01 and PSTATE.BTYPE == 0b10. Controls in SCTLR_ELx configure whether the implicit BTI instruction of a PACIBSPPC instruction is compatible with PSTATE.BTYPE == 0b11. For more information, see PSTATE.BTYPE.
11011010110000011010011111111110
f S        code2opcodeRn   Rd   


pacm - pointer authentication modifier - is used to set the value of PSTATE.PACM to 1. If FEAT_PAuth_LR is not implemented, this instruction behaves as a NOP.
11010101000000110010010011111111
                    CRm op2     


pacnbiasppc - pointer authentication code for return address, using key a, not a branch target - computes and inserts a Pointer Authentication Code for an instruction address, using two modifiers and key A. The address is in X30. The first modifier is in SP. The second modifier is the value of PC.
11011010110000011000001111111110
f S        code2opcodeRn   Rd   


pacnbibsppc - pointer authentication code for return address, using key b, not a branch target - computes and inserts a Pointer Authentication Code for an instruction address, using two modifiers and key B. The address is in X30. The first modifier is in SP. The second modifier is the value of PC.
11011010110000011000011111111110
f S        code2opcodeRn   Rd   


prfm (immediate) - prefetch memory (immediate) - signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as prefetching the cache line containing the specified address into one or more caches. The effect of a PRFM instruction is IMPLEMENTATION DEFINED. For more information, see Prefetch memory. For information about addressing modes, see Load/Store addressing modes.
1111100110......................
ze   R  pcimm12       Rn   Rt   
 <prfop>:prefetch operation, defined as 
 Rt | <prfop> | Architectural Feature
 00000 | PLDL1KEEP | 
 00001 | PLDL1STRM | 
 00010 | PLDL2KEEP | 
 00011 | PLDL2STRM | 
 00100 | PLDL3KEEP | 
 00101 | PLDL3STRM | 
 00110 | PLDSLCKEEP | 
                  
 00111 | PLDSLCSTRM | 
                  
 01000 | PLIL1KEEP | 
 01001 | PLIL1STRM | 
 01010 | PLIL2KEEP | 
 01011 | PLIL2STRM | 
 01100 | PLIL3KEEP | 
 01101 | PLIL3STRM | 
 01110 | PLISLCKEEP | 
                  
 01111 | PLISLCSTRM | 
                  
 10000 | PSTL1KEEP | 
 10001 | PSTL1STRM | 
 10010 | PSTL2KEEP | 
 10011 | PSTL2STRM | 
 10100 | PSTL3KEEP | 
 10101 | PSTL3STRM | 
 10110 | PSTSLCKEEP | 
                  
 10111 | PSTSLCSTRM | 
                  
 11000 | IR | 
                  
 <imm5>:prefetch operation encoding as an immediate, in the range 0 to 31, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <pimm>:optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as <pimm>/8.

prfm (literal) - prefetch memory (literal) - signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as prefetching the cache line containing the specified address into one or more caches. The effect of a PRFM instruction is IMPLEMENTATION DEFINED. For more information, see Prefetch memory. For information about addressing modes, see Load/Store addressing modes.
11011000........................
pc   R  imm19              Rt   
 <prfop>:prefetch operation, defined as 
 Rt | <prfop> | Architectural Feature
 00000 | PLDL1KEEP | 
 00001 | PLDL1STRM | 
 00010 | PLDL2KEEP | 
 00011 | PLDL2STRM | 
 00100 | PLDL3KEEP | 
 00101 | PLDL3STRM | 
 00110 | PLDSLCKEEP | 
                  
 00111 | PLDSLCSTRM | 
                  
 01000 | PLIL1KEEP | 
 01001 | PLIL1STRM | 
 01010 | PLIL2KEEP | 
 01011 | PLIL2STRM | 
 01100 | PLIL3KEEP | 
 01101 | PLIL3STRM | 
 01110 | PLISLCKEEP | 
                  
 01111 | PLISLCSTRM | 
                  
 10000 | PSTL1KEEP | 
 10001 | PSTL1STRM | 
 10010 | PSTL2KEEP | 
 10011 | PSTL2STRM | 
 10100 | PSTL3KEEP | 
 10101 | PSTL3STRM | 
 10110 | PSTSLCKEEP | 
                  
 10111 | PSTSLCSTRM | 
                  
 <imm5>:prefetch operation encoding as an immediate, in the range 0 to 31, encoded in the "Rt" field.
 <label>:program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.

prfm (register) - prefetch memory (register) - signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as prefetching the cache line containing the specified address into one or more caches. The effect of a PRFM instruction is IMPLEMENTATION DEFINED. For more information, see Prefetch memory. For information about addressing modes, see Load/Store addressing modes.
11111000101.....x1x.10.....!= 11xxx!= 11xxx!= 11xxx!= 11xxx!= 11xxx
ze   R  pc Rm   ionS  Rn   Rt   
 <prfop>:prefetch operation, defined as 
 Rt | <prfop> | Architectural Feature
 00000 | PLDL1KEEP | 
 00001 | PLDL1STRM | 
 00010 | PLDL2KEEP | 
 00011 | PLDL2STRM | 
 00100 | PLDL3KEEP | 
 00101 | PLDL3STRM | 
 00110 | PLDSLCKEEP | 
                  
 00111 | PLDSLCSTRM | 
                  
 01000 | PLIL1KEEP | 
 01001 | PLIL1STRM | 
 01010 | PLIL2KEEP | 
 01011 | PLIL2STRM | 
 01100 | PLIL3KEEP | 
 01101 | PLIL3STRM | 
 01110 | PLISLCKEEP | 
                  
 01111 | PLISLCSTRM | 
                  
 10000 | PSTL1KEEP | 
 10001 | PSTL1STRM | 
 10010 | PSTL2KEEP | 
 10011 | PSTL2STRM | 
 10100 | PSTL3KEEP | 
 10101 | PSTL3STRM | 
 10110 | PSTSLCKEEP | 
                  
 10111 | PSTSLCSTRM | 
                  
 <imm5>:prefetch operation encoding as an immediate, in the range 0 to 31, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Wm>:When 
 <Xm>:When 
 <extend>
 option | <extend>
 010 | UXTW
 011 | LSL
 110 | SXTW
 111 | SXTX
 <amount>
 S | <amount>
 0 | #0
 1 | #3

prfum - prefetch memory (unscaled offset) - signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as prefetching the cache line containing the specified address into one or more caches. The effect of a PRFUM instruction is IMPLEMENTATION DEFINED. For more information, see Prefetch memory. For information about addressing modes, see Load/Store addressing modes.
11111000100.........00..........
ze   R  pc imm9       Rn   Rt   
 <prfop>:prefetch operation, defined as 
 Rt | <prfop>
 00000 | PLDL1KEEP
 00001 | PLDL1STRM
 00010 | PLDL2KEEP
 00011 | PLDL2STRM
 00100 | PLDL3KEEP
 00101 | PLDL3STRM
 01000 | PLIL1KEEP
 01001 | PLIL1STRM
 01010 | PLIL2KEEP
 01011 | PLIL2STRM
 01100 | PLIL3KEEP
 01101 | PLIL3STRM
 10000 | PSTL1KEEP
 10001 | PSTL1STRM
 10010 | PSTL2KEEP
 10011 | PSTL2STRM
 10100 | PSTL3KEEP
 10101 | PSTL3STRM
 <imm5>:prefetch operation encoding as an immediate, in the range 0 to 31, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

psb - profiling synchronization barrier - is a barrier that ensures that all existing profiling data for the current PE has been formatted, and profiling buffer addresses have been translated such that all writes to the profiling buffer have been initiated. A following DSB instruction completes when the writes to the profiling buffer have completed. If FEAT_SPE is not implemented, this instruction executes as a NOP.
11010101000000110010001000111111
                    CRm op2     


pssbb - physical speculative store bypass barrier - is a memory barrier that prevents speculative loads from bypassing earlier stores to the same physical address under certain conditions. For more information and details of the semantics, see Physical Speculative Store Bypass Barrier (PSSBB).
11010101000000110011010010011111
                    CRm  pcRt   


rbit - reverse bits - reverses the bit order in a register.
.101101011000000000000..........
f S        code2opcodeRn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

rcwcas, rcwcasa, rcwcasal, rcwcasl - read check write compare and swap doubleword in memory - reads a 64-bit doubleword from memory, and compares it against the value held in a register. If the comparison is equal, the value in a second register is conditionally written to memory. Storing back to memory is conditional on RCW Checks. If the compare fails or the RCW Checks fail, the architecture permits writing the value read from the location to memory. If the write is performed, the read and the write occur atomically such that no other modification of the memory location can take place between the read and the write. updates the condition flags based on the result of the update of memory.
00011001..1.....000010..........
 S      AR Rs         Rn   Rt   
 <Xs>:64-bit name of the general-purpose register to be compared and loaded, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be conditionally stored, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

rcwcasp, rcwcaspa, rcwcaspal, rcwcaspl - read check write compare and swap quadword in memory - reads a 128-bit quadword from memory, and compares it against the value held in a pair of registers. If the comparison is equal, the value in a second pair of registers is conditionally written to memory. Storing back to memory is conditional on RCW Checks. If the compare fails or the RCW Checks fail, the architecture permits writing the value read from the location to memory. If the write is performed, the read and the write occur atomically such that no other modification of the memory location can take place between the read and the write. updates the condition flags based on the result of the update of memory.
00011001..1.....000011..........
 S      AR Rs         Rn   Rt   
 <Xs>:64-bit name of the first general-purpose register to be compared and loaded, encoded in the "Rs" field. <Xs> must be an even-numbered register.
 <X(s+1)>:64-bit name of the second general-purpose register to be compared and loaded.
 <Xt>:64-bit name of the first general-purpose register to be conditionally stored, encoded in the "Rt" field. <Xt> must be an even-numbered register.
 <X(t+1)>:64-bit name of the second general-purpose register to be conditionally stored.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

rcwclr, rcwclra, rcwclral, rcwclrl - read check write atomic bit clear on doubleword in memory - atomically loads a 64-bit doubleword from memory, performs a bitwise AND with the complement of the value held in a register on it, and conditionally stores the result back to memory. Storing of the result back to memory is conditional on RCW Checks. The value initially loaded from memory is returned in the destination register. updates the condition flags based on the result of the update of memory.
00111000..1.....100100..........
 S   R  AR Rs   3opc  Rn   Rt   
 <Xs>:64-bit name of the general-purpose register to be stored, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

rcwclrp, rcwclrpa, rcwclrpal, rcwclrpl - read check write atomic bit clear on quadword in memory - atomically loads a 128-bit quadword from memory, performs a bitwise AND with the complement of the value held in a pair of registers on it, and conditionally stores the result back to memory. Storing of the result back to memory is conditional on RCW Checks. The value initially loaded from memory is returned in the same pair of registers. updates the condition flags based on the result of the update of memory.
00011001..1.....100100..........
 S      AR Rt2  3opc  Rn   Rt   
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

rcwscas, rcwscasa, rcwscasal, rcwscasl - read check write software compare and swap doubleword in memory - reads a 64-bit doubleword from memory, and compares it against the value held in a register. If the comparison is equal, the value in a second register is conditionally written to memory. Storing back to memory is conditional on RCW Checks and RCWS Checks. If the compare fails, the RCW Checks fail, or the RCWS Checks fail, the architecture permits writing the value read from the location to memory. If the write is performed, the read and the write occur atomically such that no other modification of the memory location can take place between the read and the write. updates the condition flags based on the result of the update of memory.
01011001..1.....000010..........
 S      AR Rs         Rn   Rt   
 <Xs>:64-bit name of the general-purpose register to be compared and loaded, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be conditionally stored, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

rcwscasp, rcwscaspa, rcwscaspal, rcwscaspl - read check write software compare and swap quadword in memory - reads a 128-bit quadword from memory, and compares it against the value held in a pair of registers. If the comparison is equal, the value in a second pair of registers is conditionally written to memory. Storing back to memory is conditional on RCW Checks and RCWS Checks. If the compare fails, the RCW Checks fail, or the RCWS Checks fail, the architecture permits writing the value read from the location to memory. If the write is performed, the read and the write occur atomically such that no other modification of the memory location can take place between the read and the write. updates the condition flags based on the result of the update of memory.
01011001..1.....000011..........
 S      AR Rs         Rn   Rt   
 <Xs>:64-bit name of the first general-purpose register to be compared and loaded, encoded in the "Rs" field. <Xs> must be an even-numbered register.
 <X(s+1)>:64-bit name of the second general-purpose register to be compared and loaded.
 <Xt>:64-bit name of the first general-purpose register to be conditionally stored, encoded in the "Rt" field. <Xt> must be an even-numbered register.
 <X(t+1)>:64-bit name of the second general-purpose register to be conditionally stored.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

rcwsclr, rcwsclra, rcwsclral, rcwsclrl - read check write software atomic bit clear on doubleword in memory - atomically loads a 64-bit doubleword from memory, performs a bitwise AND with the complement of the value held in a register on it, and conditionally stores the result back to memory. Storing of the result back to memory is conditional on RCW Checks and RCWS Checks. The value initially loaded from memory is returned in the destination register. updates the condition flags based on the result of the update of memory.
01111000..1.....100100..........
 S   R  AR Rs   3opc  Rn   Rt   
 <Xs>:64-bit name of the general-purpose register to be stored, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

rcwsclrp, rcwsclrpa, rcwsclrpal, rcwsclrpl - read check write software atomic bit clear on quadword in memory - atomically loads a 128-bit quadword from memory, performs a bitwise AND with the complement of the value held in a pair of registers on it, and conditionally stores the result back to memory. Storing of the result back to memory is conditional on RCW Checks and RCWS Checks. The value initially loaded from memory is returned in the same pair of registers. updates the condition flags based on the result of the update of memory.
01011001..1.....100100..........
 S      AR Rt2  3opc  Rn   Rt   
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

rcwset, rcwseta, rcwsetal, rcwsetl - read check write atomic bit set on doubleword in memory - atomically loads a 64-bit doubleword from memory, performs a bitwise OR with the complement of the value held in a register on it, and conditionally stores the result back to memory. Storing of the result back to memory is conditional on RCW Checks. The value initially loaded from memory is returned in the destination register. updates the condition flags based on the result of the update of memory.
00111000..1.....101100..........
 S   R  AR Rs   3opc  Rn   Rt   
 <Xs>:64-bit name of the general-purpose register to be stored, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

rcwsetp, rcwsetpa, rcwsetpal, rcwsetpl - read check write atomic bit set on quadword in memory - atomically loads a 128-bit quadword from memory, performs a bitwise OR with the value held in a pair of registers on it, and conditionally stores the result back to memory. Storing of the result back to memory is conditional on RCW Checks. The value initially loaded from memory is returned in the same pair of registers. updates the condition flags based on the result of the update of memory.
00011001..1.....101100..........
 S      AR Rt2  3opc  Rn   Rt   
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

rcwsset, rcwsseta, rcwssetal, rcwssetl - read check write software atomic bit set on doubleword in memory - atomically loads a 64-bit doubleword from memory, performs a bitwise OR with the complement of the value held in a register on it, and conditionally stores the result back to memory. Storing of the result back to memory is conditional on RCW Checks and RCWS Checks. The value initially loaded from memory is returned in the destination register. updates the condition flags based on the result of the update of memory.
01111000..1.....101100..........
 S   R  AR Rs   3opc  Rn   Rt   
 <Xs>:64-bit name of the general-purpose register to be stored, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

rcwssetp, rcwssetpa, rcwssetpal, rcwssetpl - read check write software atomic bit set on quadword in memory - atomically loads a 128-bit quadword from memory, performs a bitwise OR with the value held in a pair of registers on it, and conditionally stores the result back to memory. Storing of the result back to memory is conditional on RCW Checks and RCWS Checks. The value initially loaded from memory is returned in the same pair of registers. updates the condition flags based on the result of the update of memory.
01011001..1.....101100..........
 S      AR Rt2  3opc  Rn   Rt   
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

rcwsswp, rcwsswpa, rcwsswpal, rcwsswpl - read check write software swap doubleword in memory - atomically loads a 64-bit doubleword from a memory location, and conditionally stores the value held in a register back to the same memory location. Storing back to memory is conditional on RCW Checks and RCWS Checks. The value initially loaded from memory is returned in the destination register. updates the condition flags based on the result of the update of memory.
01111000..1.....101000..........
 S   R  AR Rs   3opc  Rn   Rt   
 <Xs>:64-bit name of the general-purpose register to be stored, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

rcwsswpp, rcwsswppa, rcwsswppal, rcwsswppl - read check write software swap quadword in memory - atomically loads a 128-bit quadword from a memory location, and conditionally stores the value held in a pair of registers back to the same memory location. Storing back to memory is conditional on RCW Checks and RCWS Checks. The value initially loaded from memory is returned in the same pair of registers. updates the condition flags based on the result of the update of memory.
01011001..1.....101000..........
 S      AR Rt2  3opc  Rn   Rt   
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

rcwswp, rcwswpa, rcwswpal, rcwswpl - read check write swap doubleword in memory - atomically loads a 64-bit doubleword from a memory location, and conditionally stores the value held in a register back to the same memory location. Storing back to memory is conditional on RCW Checks. The value initially loaded from memory is returned in the destination register. updates the condition flags based on the result of the update of memory.
00111000..1.....101000..........
 S   R  AR Rs   3opc  Rn   Rt   
 <Xs>:64-bit name of the general-purpose register to be stored, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

rcwswpp, rcwswppa, rcwswppal, rcwswppl - read check write swap quadword in memory - atomically loads a 128-bit quadword from a memory location, and conditionally stores the value held in a pair of registers back to the same memory location. Storing back to memory is conditional on RCW Checks. The value initially loaded from memory is returned in the same pair of registers. updates the condition flags based on the result of the update of memory.
00011001..1.....101000..........
 S      AR Rt2  3opc  Rn   Rt   
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ret - return from subroutine - branches unconditionally to an address in a register, with a hint that this is a subroutine return.
1101011001011111000000.....00000
       Z opop2      AMRn   Rm   
 <Xn>:64-bit name of the general-purpose register holding the address to be branched to, encoded in the "Rn" field. Defaults to X30 if absent.

retaa, retab - return from subroutine, with pointer authentication - authenticates the address that is held in LR, using SP as the modifier and the specified key, and branches to the authenticated address, with a hint that this instruction is a subroutine return. Key A is used for RETAA. Key B is used for RETAB. If the authentication passes, the PE continues execution at the target of the branch. For information on behavior if the authentication fails, see Faulting on pointer authentication. The authenticated address is not written back to LR. If FEAT_PAuth_LR is implemented and PSTATE.PACM is 1, then RETAA and RETAB include a second modifier that is in X16.
110101100101111100001.1111111111
       Z opop2      AMRn   Rm   


retaasppc, retabsppc - return from subroutine, with enhanced pointer authentication using an immediate offset - authenticates the address that is held in LR, using SP as the first modifier, the specified immediate subtracted from PC as the second modifier, and the specified key, and branches to the authenticated address, with a hint that this instruction is a subroutine return. Key A is used for RETAASPPC. Key B is used for RETABSPPC. If the authentication passes, the PE continues execution at the target of the branch. For information on behavior if the authentication fails, see Faulting on pointer authentication. The authenticated address is not written back to LR.
0101010100x................11111
        opcimm16           op2  
 <label>:program label whose address is to be calculated. Its negative offset from the address of this instruction, a multiple of 4 in the range -262140 to 0, is encoded as an unsigned value in the "imm16" field as <label>/4.

retaasppcr, retabsppcr - return from subroutine, with enhanced pointer authentication using a register - authenticates the address that is held in LR, using SP as the first modifier, the value in the specified register as the second modifier, and the specified key, and branches to the authenticated address, with a hint that this instruction is a subroutine return. Key A is used for RETAASPPCR. Key B is used for RETABSPPCR. If the authentication passes, the PE continues execution at the target of the branch. For information on behavior if the authentication fails, see Faulting on pointer authentication. The authenticated address is not written back to LR.
110101100101111100001.11111!= 11111!= 11111!= 11111!= 11111!= 11111
       opc op2       MRn   Rm   
 <Xm>:64-bit name of the general-purpose source register, encoded in the "Rm" field.

rev - reverse bytes - reverses the byte order in a register.
.10110101100000000001x..........
f S        code2    pcRn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

rev16 - reverse bytes in 16-bit halfwords - reverses the byte order in each 16-bit halfword of a register.
.101101011000000000001..........
f S        code2    pcRn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

rev32 - reverse bytes in 32-bit words - reverses the byte order in each 32-bit word of a register.
1101101011000000000010..........
f S        code2    pcRn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

rev64 - reverse bytes - reverses the byte order in a 64-bit general-purpose register. When assembling for Armv8.2, an assembler must support this pseudo-instruction. It is OPTIONAL whether an assembler supports this pseudo-instruction when assembling for an architecture earlier than Armv8.2.
1101101011000000000011..........
f S        code2    pcRn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

rmif - rotate, mask insert flags - performs a rotation right of a value held in a general-purpose register by an immediate value, and then inserts a selection of the bottom four bits of the result of the rotation into the PSTATE flags, under the control of a second immediate mask.
10111010000......00001.....0....
fpS        imm6       Rn   2mask
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.
 <shift>:shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <mask>:flag bit mask, an immediate in the range 0 to 15, which selects the bits that are inserted into the NZCV condition flags, encoded in the "mask" field.

ror (immediate) - rotate right (immediate) - provides the value of the contents of a register rotated by a variable number of bits. The bits that are rotated off the right end are inserted into the vacated bit positions on the left.
.00100111.0.....................
f21      N0Rm   imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Ws>:32-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.
 <shift>:For the "32-bit" variant: is the amount by which to rotate, in the range 0 to 31, encoded in the "imms" field.
 <shift>:For the "64-bit" variant: is the amount by which to rotate, in the range 0 to 63, encoded in the "imms" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xs>:64-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.

ror (register) - rotate right (register) - provides the value of the contents of a register rotated by a variable number of bits. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. The value of the second source register modulo the register size in bits gives the number of bits by which the first source register is right-shifted.
.0011010110.....001011..........
f S        Rm       p2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits, encoded in the "Rm" field.

rorv - rotate right variable - provides the value of the contents of a register rotated by a variable number of bits. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. The value of the second source register modulo the register size in bits gives the number of bits by which the first source register is right-shifted.
.0011010110.....001011..........
f S        Rm       p2Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits, encoded in the "Rm" field.

rprfm - range prefetch memory - signals the memory system that data memory accesses from a specified range of addresses are likely to occur in the near future. The instruction may also signal the memory system about the likelihood of data reuse of the specified range of addresses. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as prefetching locations within the specified address ranges into one or more caches. The memory system may also exploit the data reuse hints to decide whether to retain the data in other caches upon eviction from the innermost caches or to discard it. The effect of an RPRFM instruction is IMPLEMENTATION DEFINED. For more information, see Prefetch memory. An RPRFM instruction specifies the type of accesses and range of addresses using the following parameters:
11111000101.....x1x.10.....11xxx
ze   R  pc Rm   ionS  Rn   Rt   
 <rprfop>:range prefetch operation, defined as 
 option | S | Rt | <rprfop>
 010 | 0 | 11000 | PLDKEEP
 010 | 0 | 11001 | PSTKEEP
 010 | 0 | 11100 | PLDSTRM
 010 | 0 | 11101 | PSTSTRM
 <imm6>:range prefetch operation encoding as an immediate, in the range 0 to 63, encoded in "option<2>:option<0>:S:Rt<2:0>". This syntax is only for encodings that are not representable using 
 <Xm>:64-bit name of the general-purpose register that holds an encoding of the metadata, encoded in the "Rm" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

sb - speculation barrier - is a barrier that controls speculation. For more information and details of the semantics, see Speculation Barrier (SB).
11010101000000110011000011111111
                    CRm  pcRt   


sbc - subtract with carry - subtracts a register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register.
.1011010000.....000000..........
fpS        Rm         Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

sbcs - subtract with carry, setting flags - subtracts a register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It updates the condition flags based on the result.
.1111010000.....000000..........
fpS        Rm         Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

sbfiz - signed bitfield insert in zeros - copies a bitfield of <width> bits from the least significant bits of the source register to bit position <lsb> of the destination register, setting the destination bits below the bitfield to zero, and the bits above the bitfield to a copy of the most significant bit of the bitfield.
.00100110.......................
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <lsb>:For the "32-bit" variant: is the bit number of the lsb of the destination bitfield, in the range 0 to 31.
 <lsb>:For the "64-bit" variant: is the bit number of the lsb of the destination bitfield, in the range 0 to 63.
 <width>:For the "32-bit" variant: is the width of the bitfield, in the range 1 to 32-<lsb>.
 <width>:For the "64-bit" variant: is the width of the bitfield, in the range 1 to 64-<lsb>.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

sbfm - signed bitfield move - is usually accessed via one of its aliases, which are always preferred for disassembly. If <imms> is greater than or equal to <immr>, this copies a bitfield of (<imms>-<immr>+1) bits starting from bit position <immr> in the source register to the least significant bits of the destination register. If <imms> is less than <immr>, this copies a bitfield of (<imms>+1) bits from the least significant bits of the source register to bit position (regsize-<immr>) of the destination register, where regsize is the destination register size of 32 or 64 bits. In both cases, the destination bits below the bitfield are set to zero, and the bits above the bitfield are set to a copy of the most significant bit of the bitfield.
.00100110.......................
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <immr>:For the "32-bit" variant: is the right rotate amount, in the range 0 to 31, encoded in the "immr" field.
 <immr>:For the "64-bit" variant: is the right rotate amount, in the range 0 to 63, encoded in the "immr" field.
 <imms>:For the "32-bit" variant: is the leftmost bit number to be moved from the source, in the range 0 to 31, encoded in the "imms" field.
 <imms>:For the "64-bit" variant: is the leftmost bit number to be moved from the source, in the range 0 to 63, encoded in the "imms" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

sbfx - signed bitfield extract - copies a bitfield of <width> bits starting from bit position <lsb> in the source register to the least significant bits of the destination register, and sets destination bits above the bitfield to a copy of the most significant bit of the bitfield.
.00100110.......................
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <lsb>:For the "32-bit" variant: is the bit number of the lsb of the source bitfield, in the range 0 to 31.
 <lsb>:For the "64-bit" variant: is the bit number of the lsb of the source bitfield, in the range 0 to 63.
 <width>:For the "32-bit" variant: is the width of the bitfield, in the range 1 to 32-<lsb>.
 <width>:For the "64-bit" variant: is the width of the bitfield, in the range 1 to 64-<lsb>.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

sdiv - signed divide - divides the first signed source register value by the second signed source register value, and writes the result to the destination register. Dividing by zero writes the value zero to the destination register. The condition flags are not affected.
.0011010110.....000011..........
f S        Rm        1Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

setf8, setf16 - evaluation of 8-bit or 16-bit flag values - sets the PSTATE.NZV flags based on the value in the specified general-purpose register. SETF8 treats the value as an 8-bit value. SETF16 treats the value as a 16-bit value. The PSTATE.C flag is not affected by these instructions.
00111010000000000.0010.....01101
fpS        pcode2z    Rn   3mask
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.

setgp, setgm, setge - memory set with tag setting - These instructions set a requested number of bytes in memory to the value in the least significant byte of the source data register and store an Allocation Tag to memory for each Tag Granule written. The Allocation Tag is calculated from the Logical Address Tag in the register that holds the first address to be set. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: SETGP, then SETGM, and then SETGE. SETGP performs some preconditioning of the arguments suitable for using the SETGM instruction, and sets an IMPLEMENTATION DEFINED portion of the requested number of bytes. SETGM sets a further IMPLEMENTATION DEFINED portion of the remaining bytes. SETGE sets any final remaining bytes. For more information on exceptions specific to memory set instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory set: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For SETGP: On completion of SETGP, option A: On completion of SETGP, option B: For SETGM, option A, when PSTATE.C = 0: For SETGM, option B, when PSTATE.C = 1: For SETGE, option A, when PSTATE.C = 0: For SETGE, option B, when PSTATE.C = 1:
..011101110.....xx0001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the destination address (an integer multiple of 16) and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address (an integer multiple of 16) and for option B is updated by the instruction, encoded in the "Rd" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set (an integer multiple of 16) and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set (an integer multiple of 16) and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set (an integer multiple of 16) and is set to zero on completion of the instruction, encoded in the "Rn" field.
 <Xs>:For the "Main" and "Prologue" variants: is the 64-bit name of the general-purpose register that holds the source data in bits<7:0>, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds the source data, encoded in the "Rs" field.

setgpn, setgmn, setgen - memory set with tag setting, non-temporal - These instructions set a requested number of bytes in memory to the value in the least significant byte of the source data register and store an Allocation Tag to memory for each Tag Granule written. The Allocation Tag is calculated from the Logical Address Tag in the register that holds the first address to be set. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: SETGPN, then SETGMN, and then SETGEN. SETGPN performs some preconditioning of the arguments suitable for using the SETGMN instruction, and sets an IMPLEMENTATION DEFINED portion of the requested number of bytes. SETGMN sets a further IMPLEMENTATION DEFINED portion of the remaining bytes. SETGEN sets any final remaining bytes. For more information on exceptions specific to memory set instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory set: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For SETGPN: On completion of SETGPN, option A: On completion of SETGPN, option B: For SETGMN, option A, when PSTATE.C = 0: For SETGMN, option B, when PSTATE.C = 1: For SETGEN, option A, when PSTATE.C = 0: For SETGEN, option B, when PSTATE.C = 1:
..011101110.....xx1001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the destination address (an integer multiple of 16) and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address (an integer multiple of 16) and for option B is updated by the instruction, encoded in the "Rd" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set (an integer multiple of 16) and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set (an integer multiple of 16) and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set (an integer multiple of 16) and is set to zero on completion of the instruction, encoded in the "Rn" field.
 <Xs>:For the "Main" and "Prologue" variants: is the 64-bit name of the general-purpose register that holds the source data in bits<7:0>, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds the source data, encoded in the "Rs" field.

setgpt, setgmt, setget - memory set with tag setting, unprivileged - These instructions set a requested number of bytes in memory to the value in the least significant byte of the source data register and store an Allocation Tag to memory for each Tag Granule written. The Allocation Tag is calculated from the Logical Address Tag in the register that holds the first address to be set. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: SETGPT, then SETGMT, and then SETGET. SETGPT performs some preconditioning of the arguments suitable for using the SETGMT instruction, and sets an IMPLEMENTATION DEFINED portion of the requested number of bytes. SETGMT sets a further IMPLEMENTATION DEFINED portion of the remaining bytes. SETGET sets any final remaining bytes. For more information on exceptions specific to memory set instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory set: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For SETGPT: On completion of SETGPT, option A: On completion of SETGPT, option B: For SETGMT, option A, when PSTATE.C = 0: For SETGMT, option B, when PSTATE.C = 1: For SETGET, option A, when PSTATE.C = 0: For SETGET, option B, when PSTATE.C = 1: Explicit Memory Write  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Write  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011101110.....xx0101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the destination address (an integer multiple of 16) and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address (an integer multiple of 16) and for option B is updated by the instruction, encoded in the "Rd" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set (an integer multiple of 16) and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set (an integer multiple of 16) and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set (an integer multiple of 16) and is set to zero on completion of the instruction, encoded in the "Rn" field.
 <Xs>:For the "Main" and "Prologue" variants: is the 64-bit name of the general-purpose register that holds the source data in bits<7:0>, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds the source data, encoded in the "Rs" field.

setgptn, setgmtn, setgetn - memory set with tag setting, unprivileged and non-temporal - These instructions set a requested number of bytes in memory to the value in the least significant byte of the source data register and store an Allocation Tag to memory for each Tag Granule written. The Allocation Tag is calculated from the Logical Address Tag in the register that holds the first address to be set. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: SETGPTN, then SETGMTN, and then SETGETN. SETGPTN performs some preconditioning of the arguments suitable for using the SETGMTN instruction, and sets an IMPLEMENTATION DEFINED portion of the requested number of bytes. SETGMTN sets a further IMPLEMENTATION DEFINED portion of the remaining bytes. SETGETN sets any final remaining bytes. For more information on exceptions specific to memory set instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory set: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For SETGPTN: On completion of SETGPTN, option A: On completion of SETGPTN, option B: For SETGMTN, option A, when PSTATE.C = 0: For SETGMTN, option B, when PSTATE.C = 1: For SETGETN, option A, when PSTATE.C = 0: For SETGETN, option B, when PSTATE.C = 1: Explicit Memory Write  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Write  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011101110.....xx1101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the destination address (an integer multiple of 16) and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address (an integer multiple of 16) and for option B is updated by the instruction, encoded in the "Rd" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set (an integer multiple of 16) and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set (an integer multiple of 16) and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set (an integer multiple of 16) and is set to zero on completion of the instruction, encoded in the "Rn" field.
 <Xs>:For the "Main" and "Prologue" variants: is the 64-bit name of the general-purpose register that holds the source data in bits<7:0>, encoded in the "Rs" field.
 <Xs>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds the source data, encoded in the "Rs" field.

setp, setm, sete - memory set - These instructions set a required number of bytes in memory to the value in the least significant byte of the source data register. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: SETP, then SETM, and then SETE. SETP performs some preconditioning of the arguments suitable for using the SETM instruction, and sets an IMPLEMENTATION DEFINED portion of the requested number of bytes. SETM sets a further IMPLEMENTATION DEFINED portion of the remaining bytes. SETE sets any final remaining bytes. For more information on exceptions specific to memory set instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory set: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For SETP: On completion of SETP, option A: On completion of SETP, option B: For SETM, option A, when PSTATE.C = 0: For SETM, option B, when PSTATE.C = 1: For SETE, option A, when PSTATE.C = 0: For SETE, option B, when PSTATE.C = 1:
..011001110.....xx0001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address and for option B is updated by the instruction, encoded in the "Rd" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set and is set to zero on completion of the instruction, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register that holds the source data, encoded in the "Rs" field.

setpn, setmn, seten - memory set, non-temporal - These instructions set a required number of bytes in memory to the value in the least significant byte of the source data register. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: SETPN, then SETMN, and then SETEN. SETPN performs some preconditioning of the arguments suitable for using the SETMN instruction, and sets an IMPLEMENTATION DEFINED portion of the requested number of bytes. SETMN sets a further IMPLEMENTATION DEFINED portion of the remaining bytes. SETEN sets any final remaining bytes. For more information on exceptions specific to memory set instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory set: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For SETPN: On completion of SETPN, option A: On completion of SETPN, option B: For SETMN, option A, when PSTATE.C = 0: For SETMN, option B, when PSTATE.C = 1: For SETEN, option A, when PSTATE.C = 0: For SETEN, option B, when PSTATE.C = 1:
..011001110.....xx1001..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address and for option B is updated by the instruction, encoded in the "Rd" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set and is set to zero on completion of the instruction, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register that holds the source data, encoded in the "Rs" field.

setpt, setmt, setet - memory set, unprivileged - These instructions set a required number of bytes in memory to the value in the least significant byte of the source data register. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: SETPT, then SETMT, and then SETET. SETPT performs some preconditioning of the arguments suitable for using the SETMT instruction, and sets an IMPLEMENTATION DEFINED portion of the requested number of bytes. SETMT sets a further IMPLEMENTATION DEFINED portion of the remaining bytes. SETET sets any final remaining bytes. For more information on exceptions specific to memory set instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory set: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For SETPT: On completion of SETPT, option A: On completion of SETPT, option B: For SETMT, option A, when PSTATE.C = 0: For SETMT, option B, when PSTATE.C = 1: For SETET, option A, when PSTATE.C = 0: For SETET, option B, when PSTATE.C = 1: Explicit Memory Write  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Write  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011001110.....xx0101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address and for option B is updated by the instruction, encoded in the "Rd" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set and is set to zero on completion of the instruction, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register that holds the source data, encoded in the "Rs" field.

setptn, setmtn, setetn - memory set, unprivileged and non-temporal - These instructions set a required number of bytes in memory to the value in the least significant byte of the source data register. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: SETPTN, then SETMTN, and then SETETN. SETPTN performs some preconditioning of the arguments suitable for using the SETMTN instruction, and sets an IMPLEMENTATION DEFINED portion of the requested number of bytes. SETMTN sets a further IMPLEMENTATION DEFINED portion of the remaining bytes. SETETN sets any final remaining bytes. For more information on exceptions specific to memory set instructions, see Memory Copy and Memory Set exceptions. The architecture supports two algorithms for the memory set: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. For SETPTN: On completion of SETPTN, option A: On completion of SETPTN, option B: For SETMTN, option A, when PSTATE.C = 0: For SETMTN, option B, when PSTATE.C = 1: For SETETN, option A, when PSTATE.C = 0: For SETETN, option B, when PSTATE.C = 1: Explicit Memory Write  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory Write  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
..011001110.....xx1101..........
sz   0  p1 Rs   op2   Rn   Rd   
 <Xd>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field.
 <Xd>:For the "Epilogue" and "Main" variants: is the 64-bit name of the general-purpose register that holds an encoding of the destination address and for option B is updated by the instruction, encoded in the "Rd" field.
 <Xn>:For the "Prologue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Main" variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set and is updated by the instruction, encoded in the "Rn" field.
 <Xn>:For the "Epilogue" variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set and is set to zero on completion of the instruction, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register that holds the source data, encoded in the "Rs" field.

sev - send event - is a hint instruction that causes an event to be signaled to all PEs in the multiprocessor system. For more information, see Wait for Event mechanism and Send event.
11010101000000110010000010011111
                    CRm op2     


sevl - send event local - is a hint instruction that causes an event to be signaled locally without requiring the event to be signaled to other PEs in the multiprocessor system. It can prime a wait-loop that starts with a WFE instruction.
11010101000000110010000010111111
                    CRm op2     


smaddl - signed multiply-add long - multiplies two 32-bit register values, adds a 64-bit register value, and writes the result to the 64-bit destination register.
10011011001.....0...............
f54     U  Rm   0Ra   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.
 <Xa>:64-bit name of the third general-purpose source register holding the addend, encoded in the "Ra" field.

smax (immediate) - signed maximum (immediate) - determines the signed maximum of the source register value and immediate, and writes the result to the destination register.
.0010001110000..................
fpS       opc imm8    Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <simm>:Is a signed immediate, in the range -128 to 127, encoded in the "imm8" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

smax (register) - signed maximum (register) - determines the signed maximum of the two source register values and writes the result to the destination register.
.0011010110.....011000..........
f S        Rm   opcodeRn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

smc - secure monitor call - causes an exception to EL3. SMC is available only for software executing at EL1 or higher. It is UNDEFINED in EL0. If the values of HCR_EL2.TSC and SCR_EL3.SMD are both 0, execution of an SMC instruction at EL1 or higher generates a Secure Monitor Call exception, recording it in ESR_ELx, using the EC value 0x17, that is taken to EL3. If the value of HCR_EL2.TSC is 1 and EL2 is enabled in the current Security state, execution of an SMC instruction at EL1 generates an exception that is taken to EL2, regardless of the value of SCR_EL3.SMD. If the value of HCR_EL2.TSC is 0 and the value of SCR_EL3.SMD is 1, the SMC instruction is UNDEFINED.
11010100000................00011
        opcimm16           op2LL
 <imm>:Is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm16" field.

smin (immediate) - signed minimum (immediate) - determines the signed minimum of the source register value and immediate, and writes the result to the destination register.
.0010001110010..................
fpS       opc imm8    Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <simm>:Is a signed immediate, in the range -128 to 127, encoded in the "imm8" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

smin (register) - signed minimum (register) - determines the signed minimum of the two source register values and writes the result to the destination register.
.0011010110.....011010..........
f S        Rm   opcodeRn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

smnegl - signed multiply-negate long - multiplies two 32-bit register values, negates the product, and writes the result to the 64-bit destination register.
10011011001.....111111..........
f54     U  Rm   0Ra   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.

smstart - enables access to streaming sve mode and sme architectural state - enables access to Streaming SVE mode and SME architectural state. SMSTART enters Streaming SVE mode, and enables the SME ZA storage. SMSTART SM enters Streaming SVE mode, but does not enable the SME ZA storage. SMSTART ZA enables the SME ZA storage, but does not cause an entry to Streaming SVE mode.
110101010000001101000xx101111111
             op1    CRm op2Rt   
 <option>:Maps to 
 CRm<2:1> | <option> | Description
 00 | RESERVED | 
 01 | SM | 
                  
 10 | ZA | 
                  
 11 | [absent] | 
                  

smstop - disables access to streaming sve mode and sme architectural state - disables access to Streaming SVE mode and SME architectural state. SMSTOP exits Streaming SVE mode, and disables the SME ZA storage. SMSTOP SM exits Streaming SVE mode, but does not disable the SME ZA storage. SMSTOP ZA disables the SME ZA storage, but does not cause an exit from Streaming SVE mode.
110101010000001101000xx001111111
             op1    CRm op2Rt   
 <option>:Maps to 
 CRm<2:1> | <option> | Description
 00 | RESERVED | 
 01 | SM | 
                  
 10 | ZA | 
                  
 11 | [absent] | 
                  

smsubl - signed multiply-subtract long - multiplies two 32-bit register values, subtracts the product from a 64-bit register value, and writes the result to the 64-bit destination register.
10011011001.....1...............
f54     U  Rm   0Ra   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.
 <Xa>:64-bit name of the third general-purpose source register holding the minuend, encoded in the "Ra" field.

smulh - signed multiply high - multiplies two 64-bit register values, and writes bits[127:64] of the 128-bit result to the 64-bit destination register.
10011011010.....011111..........
f54     U  Rm   0Ra   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.

smull - signed multiply long - multiplies two 32-bit register values, and writes the result to the 64-bit destination register.
10011011001.....011111..........
f54     U  Rm   0Ra   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.

ssbb - speculative store bypass barrier - is a memory barrier that prevents speculative loads from bypassing earlier stores to the same virtual address under certain conditions. For more information and details of the semantics, see Speculative Store Bypass Barrier (SSBB).
11010101000000110011000010011111
                    CRm  pcRt   


st2g - store allocation tags - stores an Allocation Tag to two Tag Granules of memory. The address used for the store is calculated from the base register and an immediate signed offset scaled by the Tag Granule. The Allocation Tag is calculated from the Logical Address Tag in the source register. generates an Unchecked access.
11011001101.........01..........
        pc imm9     p2Rn   Rt   
11011001101.........11..........
        pc imm9     p2Rn   Rt   
11011001101.........10..........
        pc imm9     p2Rn   Rt   
 <Xt|SP>:64-bit name of the general-purpose source register or stack pointer, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0 and encoded in the "imm9" field.

st64b - single-copy atomic 64-byte store without status result - stores eight 64-bit doublewords from consecutive registers to a memory location. The store starts at register Xt, with the data being formed as Data<511:0> = X(t+7):X(t+6):X(t+5):X(t+4):X(t+3):X(t+2):X(t+1):Xt. The data is stored atomically and is required to be 64-byte aligned. It is IMPLEMENTATION DEFINED which memory locations support this instruction. A memory location that supports ST64B also supports LD64B. For more information, including about the memory types accessible and how the accesses are performed, see Single-copy atomic 64-byte load/store.
1111100000111111100100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Xt>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

st64bv - single-copy atomic 64-byte store with status result - stores eight 64-bit doublewords from consecutive registers to a memory location, and writes the status result of the store to a register. The store starts at register Xt, with the data being formed as Data<511:0> = X(t+7):X(t+6):X(t+5):X(t+4):X(t+3):X(t+2):X(t+1):Xt. The data is stored atomically and is required to be 64-byte aligned. It is IMPLEMENTATION DEFINED which memory locations support this instruction. A memory location that supports ST64BV also supports ST64BV0. For more information, including about the memory types accessible and how the accesses are performed, see Single-copy atomic 64-byte load/store.
11111000001.....101100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Xs>:64-bit name of the general-purpose register into which the status result of this instruction is written, encoded in the "Rs" field.
 <Xt>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

st64bv0 - single-copy atomic 64-byte el0 store with status result - stores eight 64-bit doublewords from consecutive registers to a memory location, with the bottom 32 bits taken from ACCDATA_EL1, and writes the status result of the store to a register. The store starts at register Xt, with the data being formed as Data<511:0>  = X(t+7):X(t+6):X(t+5):X(t+4):X(t+3):X(t+2):X(t+1):Xt<63:32>:ACCDATA_EL1<31:0>. The data is stored atomically and is required to be 64-byte aligned. It is IMPLEMENTATION DEFINED which memory locations support this instruction. A memory location that supports ST64BV0 also supports ST64BV. For more information, including about the memory types accessible and how the accesses are performed, see Single-copy atomic 64-byte load/store.
11111000001.....101000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Xs>:64-bit name of the general-purpose register into which the status result of this instruction is written, encoded in the "Rs" field.
 <Xt>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stadd, staddl - atomic add on word or doubleword in memory, without return - atomically loads a 32-bit word or 64-bit doubleword from memory, adds the value held in a register to it, and stores the result back to memory. For information about addressing modes, see Load/Store addressing modes.
1x1110000.1.....000000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

staddb, staddlb - atomic add on byte in memory, without return - atomically loads an 8-bit byte from memory, adds the value held in a register to it, and stores the result back to memory. For information about addressing modes, see Load/Store addressing modes.
001110000.1.....000000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

staddh, staddlh - atomic add on halfword in memory, without return - atomically loads a 16-bit halfword from memory, adds the value held in a register to it, and stores the result back to memory. For information about addressing modes, see Load/Store addressing modes.
011110000.1.....000000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stclr, stclrl - atomic bit clear on word or doubleword in memory, without return - atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. For information about addressing modes, see Load/Store addressing modes.
1x1110000.1.....000100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

stclrb, stclrlb - atomic bit clear on byte in memory, without return - atomically loads an 8-bit byte from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. For information about addressing modes, see Load/Store addressing modes.
001110000.1.....000100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stclrh, stclrlh - atomic bit clear on halfword in memory, without return - atomically loads a 16-bit halfword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. For information about addressing modes, see Load/Store addressing modes.
011110000.1.....000100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

steor, steorl - atomic exclusive-or on word or doubleword in memory, without return - atomically loads a 32-bit word or 64-bit doubleword from memory, performs an exclusive-OR with the value held in a register on it, and stores the result back to memory. For information about addressing modes, see Load/Store addressing modes.
1x1110000.1.....001000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

steorb, steorlb - atomic exclusive-or on byte in memory, without return - atomically loads an 8-bit byte from memory, performs an exclusive-OR with the value held in a register on it, and stores the result back to memory. For information about addressing modes, see Load/Store addressing modes.
001110000.1.....001000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

steorh, steorlh - atomic exclusive-or on halfword in memory, without return - atomically loads a 16-bit halfword from memory, performs an exclusive-OR with the value held in a register on it, and stores the result back to memory. For information about addressing modes, see Load/Store addressing modes.
011110000.1.....001000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stg - store allocation tag - stores an Allocation Tag to memory. The address used for the store is calculated from the base register and an immediate signed offset scaled by the Tag Granule. The Allocation Tag is calculated from the Logical Address Tag in the source register. generates an Unchecked access.
11011001001.........01..........
        pc imm9     p2Rn   Rt   
11011001001.........11..........
        pc imm9     p2Rn   Rt   
11011001001.........10..........
        pc imm9     p2Rn   Rt   
 <Xt|SP>:64-bit name of the general-purpose source register or stack pointer, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0 and encoded in the "imm9" field.

stgm - store allocation tag multiple - writes a naturally aligned block of N Allocation Tags, where the size of N is identified in GMID_EL1.BS, and the Allocation Tag written to address A is taken from the source register at 4*A<7:4>+3:4*A<7:4>. is UNDEFINED at EL0. generates an Unchecked access.
1101100110100000000000..........
        pc imm9     p2Rn   Rt   
 <Xt>:64-bit name of the general-purpose source register, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stgp - store allocation tag and pair of registers - stores an Allocation Tag and two 64-bit doublewords to memory, from two registers. The address used for the store is calculated from the base register and an immediate signed offset scaled by the Tag Granule. The Allocation Tag is calculated from the Logical Address Tag in the base register. generates an Unchecked access.
0110100010......................
pc   R   Lsimm7  Rt2  Rn   Rt   
0110100110......................
pc   R   Lsimm7  Rt2  Rn   Rt   
0110100100......................
pc   R   Lsimm7  Rt2  Rn   Rt   
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Post-index" and "Pre-index" variants: is the signed immediate offset, a multiple of 16 in the range -1024 to 1008, encoded in the "simm7" field.
 <imm>:For the "Signed offset" variant: is the optional signed immediate offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "simm7" field.

stilp - store-release ordered pair of registers - calculates an address from a base register value and an optional offset, and stores two 32-bit words or two 64-bit doublewords to the calculated address, from two registers. For information on single-copy atomicity and alignment requirements, see Requirements for single-copy atomicity and Alignment of data accesses. The instruction also has memory ordering semantics, as described in Load-Acquire, Load-AcquirePC, and Store-Release, with the additional requirement that: For information about addressing modes, see Load/Store addressing modes.
1x011001000.....000x10..........
ze       L Rt2  opc2  Rn   Rt   
 <Wt1>:32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Wt2>:32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

stllr - store lorelease register - stores a 32-bit word or a 64-bit doubleword to a memory location, from a register. The instruction also has memory ordering semantics as described in Load LOAcquire, Store LORelease. For information about addressing modes, see Load/Store addressing modes.
1x00100010011111011111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

stllrb - store lorelease register byte - stores a byte from a 32-bit register to a memory location. The instruction also has memory ordering semantics as described in Load LOAcquire, Store LORelease. For information about addressing modes, see Load/Store addressing modes.
0000100010011111011111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stllrh - store lorelease register halfword - stores a halfword from a 32-bit register to a memory location. The instruction also has memory ordering semantics as described in Load LOAcquire, Store LORelease. For information about addressing modes, see Load/Store addressing modes.
0100100010011111011111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stlr - store-release register - stores a 32-bit word or a 64-bit doubleword to a memory location, from a register. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1x00100010011111111111..........
ze       L Rs   0Rt2  Rn   Rt   
1x01100110000000000010..........
ze       L            Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

stlrb - store-release register byte - stores a byte from a 32-bit register to a memory location. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
0000100010011111111111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stlrh - store-release register halfword - stores a halfword from a 32-bit register to a memory location. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
0100100010011111111111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stltxr - store-release unprivileged exclusive register - stores a 32-bit word or a 64-bit doubleword to memory if the PE has exclusive access to the memory address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores. The memory access is atomic. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For information about addressing modes, see Load/Store addressing modes.
1.001001000.....111111..........
 z       L Rs   0Rt2  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register into which the status result of the store exclusive is written, encoded in the "Rs" field. The value returned is:
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

stlur - store-release register (unscaled) - calculates an address from a base register value and an immediate offset, and stores a 32-bit word or a 64-bit doubleword to the calculated address, from a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release For information about addressing modes, see Load/Store addressing modes.
1x011001000.........00..........
ze      pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

stlurb - store-release register byte (unscaled) - calculates an address from a base register value and an immediate offset, and stores a byte to the calculated address, from a 32-bit register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release For information about addressing modes, see Load/Store addressing modes.
00011001000.........00..........
ze      pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

stlurh - store-release register halfword (unscaled) - calculates an address from a base register value and an immediate offset, and stores a halfword to the calculated address, from a 32-bit register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release For information about addressing modes, see Load/Store addressing modes.
01011001000.........00..........
ze      pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

stlxp - store-release exclusive pair of registers - stores two 32-bit words or two 64-bit doublewords to a memory location if the PE has exclusive access to the memory address, from two registers, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores. For information on single-copy atomicity and alignment requirements, see Requirements for single-copy atomicity and Alignment of data accesses. If a 64-bit pair Store-Exclusive succeeds, it causes a single-copy atomic update of the 128-bit memory location being updated. The instruction also has memory ordering semantics, as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1.001000001.....1...............
 z       L Rs   0Rt2  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register into which the status result of the store exclusive is written, encoded in the "Rs" field. The value returned is:
 <Wt1>:32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Wt2>:32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

stlxr - store-release exclusive register - stores a 32-bit word or a 64-bit doubleword to memory if the PE has exclusive access to the memory address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores. The memory access is atomic. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1x001000000.....111111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register into which the status result of the store exclusive is written, encoded in the "Rs" field. The value returned is:
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

stlxrb - store-release exclusive register byte - stores a byte from a 32-bit register to memory if the PE has exclusive access to the memory address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores. The memory access is atomic. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
00001000000.....111111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register into which the status result of the store exclusive is written, encoded in the "Rs" field. The value returned is:
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stlxrh - store-release exclusive register halfword - stores a halfword from a 32-bit register to memory if the PE has exclusive access to the memory address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores. The memory access is atomic. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
01001000000.....111111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register into which the status result of the store exclusive is written, encoded in the "Rs" field. The value returned is:
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stnp - store pair of registers, with non-temporal hint - calculates an address from a base register value and an immediate offset, and stores two 32-bit words or two 64-bit doublewords to the calculated address, from two registers. For information about addressing modes, see Load/Store addressing modes. For information about non-temporal pair instructions, see Load/Store non-temporal pair.
x010100000......................
pc   R   Limm7   Rt2  Rn   Rt   
 <Wt1>:32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Wt2>:32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "32-bit" variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.
 <imm>:For the "64-bit" variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

stp - store pair of registers - calculates an address from a base register value and an immediate offset, and stores two 32-bit words or two 64-bit doublewords to the calculated address, from two registers. For information about addressing modes, see Load/Store addressing modes.
x010100010......................
pc   R   Limm7   Rt2  Rn   Rt   
x010100110......................
pc   R   Limm7   Rt2  Rn   Rt   
x010100100......................
pc   R   Limm7   Rt2  Rn   Rt   
 <Wt1>:32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Wt2>:32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "32-bit Post-index" and "32-bit Pre-index" variants: is the signed immediate byte offset, a multiple of 4 in the range -256 to 252, encoded in the "imm7" field as <imm>/4.
 <imm>:For the "64-bit Post-index" and "64-bit Pre-index" variants: is the signed immediate byte offset, a multiple of 8 in the range -512 to 504, encoded in the "imm7" field as <imm>/8.
 <imm>:For the "32-bit Signed offset" variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.
 <imm>:For the "64-bit Signed offset" variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

str (immediate) - store register (immediate) - stores a word or a doubleword from a register to memory. The address that is used for the store is calculated from a base register and an immediate offset. For information about addressing modes, see Load/Store addressing modes.
1x111000000.........01..........
ze   R  pc imm9       Rn   Rt   
1x111000000.........11..........
ze   R  pc imm9       Rn   Rt   
1x11100100......................
ze   R  pcimm12       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <pimm>:For the "32-bit" variant: is the optional positive immediate byte offset, a multiple of 4 in the range 0 to 16380, defaulting to 0 and encoded in the "imm12" field as <pimm>/4.
 <pimm>:For the "64-bit" variant: is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as <pimm>/8.

str (register) - store register (register) - calculates an address from a base register value and an offset register value, and stores a 32-bit word or a 64-bit doubleword to the calculated address, from a register. For information about addressing modes, see Load/Store addressing modes. The instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an offset register value. The offset can be optionally shifted and extended.
1x111000001.........10..........
ze   R  pc Rm   ionS  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Wm>:When 
 <Xm>:When 
 <extend>
 option | <extend>
 010 | UXTW
 011 | LSL
 110 | SXTW
 111 | SXTX
 <amount>
 S | <amount>
 0 | #0
 1 | #2
 <amount>
 S | <amount>
 0 | #0
 1 | #3
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

strb (immediate) - store register byte (immediate) - stores the least significant byte of a 32-bit register to memory. The address that is used for the store is calculated from a base register and an immediate offset. For information about addressing modes, see Load/Store addressing modes.
00111000000.........01..........
ze   R  pc imm9       Rn   Rt   
00111000000.........11..........
ze   R  pc imm9       Rn   Rt   
0011100100......................
ze   R  pcimm12       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.
 <pimm>:optional positive immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.

strb (register) - store register byte (register) - calculates an address from a base register value and an offset register value, and stores a byte from a 32-bit register to the calculated address. For information about addressing modes, see Load/Store addressing modes. The instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an offset register value. The offset can be optionally shifted and extended.
00111000001.........10..........
ze   R  pc Rm   ionS  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Wm>:When 
 <Xm>:When 
 <extend>
 option | <extend>
 010 | UXTW
 110 | SXTW
 111 | SXTX
 <amount>:index shift amount, it must be 

strh (immediate) - store register halfword (immediate) - stores the least significant halfword of a 32-bit register to memory. The address that is used for the store is calculated from a base register and an immediate offset. For information about addressing modes, see Load/Store addressing modes.
01111000000.........01..........
ze   R  pc imm9       Rn   Rt   
01111000000.........11..........
ze   R  pc imm9       Rn   Rt   
0111100100......................
ze   R  pcimm12       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.
 <pimm>:optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0 and encoded in the "imm12" field as <pimm>/2.

strh (register) - store register halfword (register) - calculates an address from a base register value and an offset register value, and stores a halfword from a 32-bit register to the calculated address. For information about addressing modes, see Load/Store addressing modes. The instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an offset register value. The offset can be optionally shifted and extended.
01111000001.........10..........
ze   R  pc Rm   ionS  Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Wm>:When 
 <Xm>:When 
 <extend>
 option | <extend>
 010 | UXTW
 011 | LSL
 110 | SXTW
 111 | SXTX
 <amount>
 S | <amount>
 0 | #0
 1 | #1

stset, stsetl - atomic bit set on word or doubleword in memory, without return - atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise OR with the value held in a register on it, and stores the result back to memory. For information about addressing modes, see Load/Store addressing modes.
1x1110000.1.....001100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

stsetb, stsetlb - atomic bit set on byte in memory, without return - atomically loads an 8-bit byte from memory, performs a bitwise OR with the value held in a register on it, and stores the result back to memory. For information about addressing modes, see Load/Store addressing modes.
001110000.1.....001100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stseth, stsetlh - atomic bit set on halfword in memory, without return - atomically loads a 16-bit halfword from memory, performs a bitwise OR with the value held in a register on it, and stores the result back to memory. For information about addressing modes, see Load/Store addressing modes.
011110000.1.....001100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stshh - store shared hint - signals to the memory system that if the next instruction in program order generates an explicit write effect, then it is to a location that one or more other threads of execution will observe, and there is a performance benefit to ensuring that the updated value from the write to that location propagates to those other observers with minimal latency. The thread of execution on the other observers might be polling the location using load or load-exclusive instructions, or may have executed a PRFM IR instruction targeting the location.
11010101000000110010011000x11111
                    CRm op2     
 <policy>
 op2<0> | <policy>
 0 | KEEP
 1 | STRM

stsmax, stsmaxl - atomic signed maximum on word or doubleword in memory, without return - atomically loads a 32-bit word or 64-bit doubleword from memory, compares it against the value held in a register, and stores the larger value back to memory, treating the values as signed numbers. For information about addressing modes, see Load/Store addressing modes.
1x1110000.1.....010000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

stsmaxb, stsmaxlb - atomic signed maximum on byte in memory, without return - atomically loads an 8-bit byte from memory, compares it against the value held in a register, and stores the larger value back to memory, treating the values as signed numbers. For information about addressing modes, see Load/Store addressing modes.
001110000.1.....010000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stsmaxh, stsmaxlh - atomic signed maximum on halfword in memory, without return - atomically loads a 16-bit halfword from memory, compares it against the value held in a register, and stores the larger value back to memory, treating the values as signed numbers. For information about addressing modes, see Load/Store addressing modes.
011110000.1.....010000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stsmin, stsminl - atomic signed minimum on word or doubleword in memory, without return - atomically loads a 32-bit word or 64-bit doubleword from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as signed numbers. For information about addressing modes, see Load/Store addressing modes.
1x1110000.1.....010100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

stsminb, stsminlb - atomic signed minimum on byte in memory, without return - atomically loads an 8-bit byte from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as signed numbers. For information about addressing modes, see Load/Store addressing modes.
001110000.1.....010100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stsminh, stsminlh - atomic signed minimum on halfword in memory, without return - atomically loads a 16-bit halfword from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as signed numbers. For information about addressing modes, see Load/Store addressing modes.
011110000.1.....010100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

sttadd, sttaddl - atomic add unprivileged, without return - atomically loads a 32-bit word or 64-bit doubleword from memory, adds the value held in a register to it, and stores the result back to memory. For information about addressing modes, see Load/Store addressing modes.
0.0110010.1.....000001.....11111
 z      AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

sttclr, sttclrl - atomic bit clear unprivileged, without return - atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. For information about addressing modes, see Load/Store addressing modes.
0.0110010.1.....000101.....11111
 z      AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

sttnp - store unprivileged pair of registers, with non-temporal hint - calculates an address from a base register value and an immediate offset, and stores two 64-bit doublewords to the calculated address, from two registers. For information about addressing modes, see Load/Store addressing modes. For information about non-temporal pair instructions, see Load/Store non-temporal pair. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
1110100000......................
pc   R   Limm7   Rt2  Rn   Rt   
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.

sttp - store unprivileged pair of registers - calculates an address from a base register value and an immediate offset, and stores two 64-bit doublewords to the calculated address, from two registers. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For information about addressing modes, see Load/Store addressing modes.
1110100010......................
pc   R   Limm7   Rt2  Rn   Rt   
1110100110......................
pc   R   Limm7   Rt2  Rn   Rt   
1110100100......................
pc   R   Limm7   Rt2  Rn   Rt   
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Post-index" and "Pre-index" variants: is the signed immediate byte offset, a multiple of 8 in the range -512 to 504, encoded in the "imm7" field as <imm>/8.
 <imm>:For the "Signed offset" variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.

sttr - store register (unprivileged) - stores a word or doubleword from a register to memory. The address that is used for the store is calculated from a base register and an immediate offset. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For information about addressing modes, see Load/Store addressing modes.
1x111000000.........10..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

sttrb - store register byte (unprivileged) - stores a byte from a 32-bit register to memory. The address that is used for the store is calculated from a base register and an immediate offset. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For information about addressing modes, see Load/Store addressing modes.
00111000000.........10..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

sttrh - store register halfword (unprivileged) - stores a halfword from a 32-bit register to memory. The address that is used for the store is calculated from a base register and an immediate offset. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For information about addressing modes, see Load/Store addressing modes.
01111000000.........10..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

sttset, sttsetl - atomic bit set unprivileged, without return - atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise OR with the value held in a register on it, and stores the result back to memory. For information about addressing modes, see Load/Store addressing modes.
0.0110010.1.....001101.....11111
 z      AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

sttxr - store unprivileged exclusive register - stores a 32-bit word or a 64-bit doubleword from a register to memory if the PE has exclusive access to the memory address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed. For information about addressing modes, see Load/Store addressing modes.
1.001001000.....011111..........
 z       L Rs   0Rt2  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register into which the status result of the store exclusive is written, encoded in the "Rs" field. The value returned is:
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

stumax, stumaxl - atomic unsigned maximum on word or doubleword in memory, without return - atomically loads a 32-bit word or 64-bit doubleword from memory, compares it against the value held in a register, and stores the larger value back to memory, treating the values as unsigned numbers. For information about addressing modes, see Load/Store addressing modes.
1x1110000.1.....011000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

stumaxb, stumaxlb - atomic unsigned maximum on byte in memory, without return - atomically loads an 8-bit byte from memory, compares it against the value held in a register, and stores the larger value back to memory, treating the values as unsigned numbers. For information about addressing modes, see Load/Store addressing modes.
001110000.1.....011000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stumaxh, stumaxlh - atomic unsigned maximum on halfword in memory, without return - atomically loads a 16-bit halfword from memory, compares it against the value held in a register, and stores the larger value back to memory, treating the values as unsigned numbers. For information about addressing modes, see Load/Store addressing modes.
011110000.1.....011000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stumin, stuminl - atomic unsigned minimum on word or doubleword in memory, without return - atomically loads a 32-bit word or 64-bit doubleword from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as unsigned numbers. For information about addressing modes, see Load/Store addressing modes.
1x1110000.1.....011100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

stuminb, stuminlb - atomic unsigned minimum on byte in memory, without return - atomically loads an 8-bit byte from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as unsigned numbers. For information about addressing modes, see Load/Store addressing modes.
001110000.1.....011100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stuminh, stuminlh - atomic unsigned minimum on halfword in memory, without return - atomically loads a 16-bit halfword from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as unsigned numbers. For information about addressing modes, see Load/Store addressing modes.
011110000.1.....011100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stur - store register (unscaled) - calculates an address from a base register value and an immediate offset, and stores a 32-bit word or a 64-bit doubleword to the calculated address, from a register. For information about addressing modes, see Load/Store addressing modes.
1x111000000.........00..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

sturb - store register byte (unscaled) - calculates an address from a base register value and an immediate offset, and stores a byte to the calculated address, from a 32-bit register. For information about addressing modes, see Load/Store addressing modes.
00111000000.........00..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

sturh - store register halfword (unscaled) - calculates an address from a base register value and an immediate offset, and stores a halfword to the calculated address, from a 32-bit register. For information about addressing modes, see Load/Store addressing modes.
01111000000.........00..........
ze   R  pc imm9       Rn   Rt   
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

stxp - store exclusive pair of registers - stores two 32-bit words or two 64-bit doublewords from two registers to a memory location if the PE has exclusive access to the memory address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores. For information on single-copy atomicity and alignment requirements, see Requirements for single-copy atomicity and Alignment of data accesses. If a 64-bit pair Store-Exclusive succeeds, it causes a single-copy atomic update of the 128-bit memory location being updated. For information about addressing modes, see Load/Store addressing modes.
1.001000001.....0...............
 z       L Rs   0Rt2  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register into which the status result of the store exclusive is written, encoded in the "Rs" field. The value returned is:
 <Wt1>:32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Wt2>:32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

stxr - store exclusive register - stores a 32-bit word or a 64-bit doubleword from a register to memory if the PE has exclusive access to the memory address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores. For information about addressing modes, see Load/Store addressing modes.
1x001000000.....011111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register into which the status result of the store exclusive is written, encoded in the "Rs" field. The value returned is:
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xt>:64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

stxrb - store exclusive register byte - stores a byte from a register to memory if the PE has exclusive access to the memory address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores. The memory access is atomic. For information about addressing modes, see Load/Store addressing modes.
00001000000.....011111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register into which the status result of the store exclusive is written, encoded in the "Rs" field. The value returned is:
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stxrh - store exclusive register halfword - stores a halfword from a register to memory if the PE has exclusive access to the memory address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores. The memory access is atomic. For information about addressing modes, see Load/Store addressing modes.
01001000000.....011111..........
ze       L Rs   0Rt2  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register into which the status result of the store exclusive is written, encoded in the "Rs" field. The value returned is:
 <Wt>:32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stz2g - store allocation tags, zeroing - stores an Allocation Tag to two Tag Granules of memory, zeroing the associated data locations. The address used for the store is calculated from the base register and an immediate signed offset scaled by the Tag Granule. The Allocation Tag is calculated from the Logical Address Tag in the source register. generates an Unchecked access.
11011001111.........01..........
        pc imm9     p2Rn   Rt   
11011001111.........11..........
        pc imm9     p2Rn   Rt   
11011001111.........10..........
        pc imm9     p2Rn   Rt   
 <Xt|SP>:64-bit name of the general-purpose source register or stack pointer, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0 and encoded in the "imm9" field.

stzg - store allocation tag, zeroing - stores an Allocation Tag to memory, zeroing the associated data location. The address used for the store is calculated from the base register and an immediate signed offset scaled by the Tag Granule. The Allocation Tag is calculated from the Logical Address Tag in the source register. generates an Unchecked access.
11011001011.........01..........
        pc imm9     p2Rn   Rt   
11011001011.........11..........
        pc imm9     p2Rn   Rt   
11011001011.........10..........
        pc imm9     p2Rn   Rt   
 <Xt|SP>:64-bit name of the general-purpose source register or stack pointer, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0 and encoded in the "imm9" field.

stzgm - store allocation tag and zero multiple - writes a naturally aligned block of N Allocation Tags and stores zero to the associated data locations, where the size of N is identified in DCZID_EL0.BS, and the Allocation Tag is taken from the source register bits<3:0>. is UNDEFINED at EL0. generates an Unchecked access.
1101100100100000000000..........
        pc imm9     p2Rn   Rt   
 <Xt>:64-bit name of the general-purpose source register, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

sub (extended register) - subtract extended and scaled register - subtracts a sign or zero-extended register value, followed by an optional left shift amount, from a register value, and writes the result to the destination register. The argument that is extended from the <Rm> register can be a byte, halfword, word, or doubleword.
.1001011001.....................
fpS     pt Rm   ionmm3Rn   Rd   
 <Wd|WSP>:32-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Wn|WSP>:32-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <extend>
 option | <extend>
 000 | UXTB
 001 | UXTH
 010 | LSL|UXTW
 011 | UXTX
 100 | SXTB
 101 | SXTH
 110 | SXTW
 111 | SXTX
 If "Rd" or "Rn" is '11111' (WSP) and "option" is '010' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTW when "option" is '010'.
 <extend>
 option | <extend>
 000 | UXTB
 001 | UXTH
 010 | UXTW
 011 | LSL|UXTX
 100 | SXTB
 101 | SXTH
 110 | SXTW
 111 | SXTX
 If "Rd" or "Rn" is '11111' (SP) and "option" is '011' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTX when "option" is '011'.
 <amount>:left shift amount to be applied after extension in the range 0 to 4, defaulting to 0, encoded in the "imm3" field. It must be absent when <extend> is absent, is required when <extend> is LSL, and is optional when <extend> is present but not LSL.
 <Xd|SP>:64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <R>
 option | <R>
 00x | W
 010 | W
 x11 | X
 10x | W
 110 | W
 <m>:number [0-30] of the second general-purpose source register or the name ZR (31), encoded in the "Rm" field.

sub (immediate) - subtract immediate value - subtracts an optionally-shifted immediate value from a register value, and writes the result to the destination register.
.10100010.......................
fpS      himm12       Rn   Rd   
 <Wd|WSP>:32-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Wn|WSP>:32-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.
 <imm>:Is an unsigned immediate, in the range 0 to 4095, encoded in the "imm12" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #12
 <Xd|SP>:64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.

sub (shifted register) - subtract optionally-shifted register - subtracts an optionally-shifted register value from a register value, and writes the result to the destination register.
.1001011..0.....................
fpS     ft Rm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | RESERVED
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

subg - subtract with tag - subtracts an immediate value scaled by the Tag Granule from the address in the source register, modifies the Logical Address Tag of the address using an immediate value, and writes the result to the destination register. Tags specified in GCR_EL1.Exclude are excluded from the possible outputs when modifying the Logical Address Tag.
1101000110......00..............
fpS       imm6  p3imm4Rn   Rd   
 <Xd|SP>:64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.
 <uimm6>:Is an unsigned immediate, a multiple of 16 in the range 0 to 1008, encoded in the "imm6" field.
 <uimm4>:Is an unsigned immediate, in the range 0 to 15, encoded in the "imm4" field.

subp - subtract pointer - subtracts the 56-bit address held in the second source register from the 56-bit address held in the first source register, sign-extends the result to 64 bits, and writes the result to the destination register.
10011010110.....000000..........
f S        Rm   opcodeRn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <Xm|SP>:64-bit name of the second general-purpose source register or stack pointer, encoded in the "Rm" field.

subps - subtract pointer, setting flags - subtracts the 56-bit address held in the second source register from the 56-bit address held in the first source register, sign-extends the result to 64 bits, and writes the result to the destination register. It updates the condition flags based on the result of the subtraction.
10111010110.....000000..........
f S        Rm   opcodeRn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <Xm|SP>:64-bit name of the second general-purpose source register or stack pointer, encoded in the "Rm" field.

subpt - subtract checked pointer - subtracts an optionally-shifted register value from a base address register value, and writes the result to the destination register. The optionally-shifted register value is treated as the offset. If the operation would have generated a result where the most significant 8 bits of the result register differ from the most significant 8 bits of the base register, then the result is modified such that it is likely to be non-canonical when used as an address.
11011010000.....001.............
fpS        Rm      mm3Rn   Rd   
 <Xd|SP>:64-bit name of the general-purpose destination register or stack pointer, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the first general-purpose source register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <amount>:left shift amount, in the range 0 to 7, defaulting to 0, encoded in the "imm3" field.

subs (extended register) - subtract extended and scaled register, setting flags - subtracts a sign or zero-extended register value, followed by an optional left shift amount, from a register value, and writes the result to the destination register. The argument that is extended from the <Rm> register can be a byte, halfword, word, or doubleword. It updates the condition flags based on the result.
.1101011001.....................
fpS     pt Rm   ionmm3Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn|WSP>:32-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <extend>
 option | <extend>
 000 | UXTB
 001 | UXTH
 010 | LSL|UXTW
 011 | UXTX
 100 | SXTB
 101 | SXTH
 110 | SXTW
 111 | SXTX
 If "Rn" is '11111' (WSP) and "option" is '010' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTW when "option" is '010'.
 <extend>
 option | <extend>
 000 | UXTB
 001 | UXTH
 010 | UXTW
 011 | LSL|UXTX
 100 | SXTB
 101 | SXTH
 110 | SXTW
 111 | SXTX
 If "Rn" is '11111' (SP) and "option" is '011' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTX when "option" is '011'.
 <amount>:left shift amount to be applied after extension in the range 0 to 4, defaulting to 0, encoded in the "imm3" field. It must be absent when <extend> is absent, is required when <extend> is LSL, and is optional when <extend> is present but not LSL.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
 <R>
 option | <R>
 00x | W
 010 | W
 x11 | X
 10x | W
 110 | W
 <m>:number [0-30] of the second general-purpose source register or the name ZR (31), encoded in the "Rm" field.

subs (immediate) - subtract immediate value, setting flags - subtracts an optionally-shifted immediate value from a register value, and writes the result to the destination register. It updates the condition flags based on the result.
.11100010.......................
fpS      himm12       Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn|WSP>:32-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.
 <imm>:Is an unsigned immediate, in the range 0 to 4095, encoded in the "imm12" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #12
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.

subs (shifted register) - subtract optionally-shifted register, setting flags - subtracts an optionally-shifted register value from a register value, and writes the result to the destination register. It updates the condition flags based on the result.
.1101011..0.....................
fpS     ft Rm   imm6  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | RESERVED
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

svc - supervisor call - causes an exception to be taken to EL1. On executing an SVC instruction, the PE records the exception as a Supervisor Call exception in ESR_ELx, using the EC value 0x15, and the value of the immediate argument.
11010100000................00001
        opcimm16           op2LL
 <imm>:Is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm16" field.

swp, swpa, swpal, swpl - swap word or doubleword in memory - atomically loads a 32-bit word or 64-bit doubleword from a memory location, and stores the value held in a register back to the same memory location. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
1x111000..1.....100000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register to be stored, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register to be stored, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

swpb, swpab, swpalb, swplb - swap byte in memory - atomically loads an 8-bit byte from a memory location, and stores the value held in a register back to the same memory location. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
00111000..1.....100000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register to be stored, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

swph, swpah, swpalh, swplh - swap halfword in memory - atomically loads a 16-bit halfword from a memory location, and stores the value held in a register back to the same memory location. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
01111000..1.....100000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register to be stored, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

swpp, swppa, swppal, swppl - swap quadword in memory - atomically loads a 128-bit quadword from a memory location, and stores the value held in a pair of registers back to the same memory location. The value initially loaded from memory is returned in the same pair of registers.
00011001..1.....100000..........
 S      AR Rt2  3opc  Rn   Rt   
 <Xt1>:64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
 <Xt2>:64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

swpt, swpta, swptal, swptl - swap unprivileged - atomically loads a 32-bit word or 64-bit doubleword from a memory location, and stores the value held in a register back to the same memory location. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
0.011001..1.....100001..........
 z      AR Rs   3opc  Rn   Rt   
 <Ws>:32-bit name of the general-purpose register to be stored, encoded in the "Rs" field.
 <Wt>:32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xs>:64-bit name of the general-purpose register to be stored, encoded in the "Rs" field.
 <Xt>:64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

sxtb - signed extend byte - extracts an 8-bit value from a register, sign-extends it to the size of the register, and writes the result to the destination register.
.00100110.000000000111..........
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.

sxth - sign extend halfword - extracts a 16-bit value, sign-extends it to the size of the register, and writes the result to the destination register.
.00100110.000000001111..........
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.

sxtw - sign extend word - sign-extends a word to the size of the register, and writes the result to the destination register.
1001001101000000011111..........
fpc      Nimmr  imms  Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.

sys - system instruction - For more information, see Op0 equals 0b01, cache maintenance, TLB maintenance, and address translation instructions for the encodings of System instructions.
1101010100001...................
          L  op1CRn CRm op2Rt   
 <op1>:Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.
 <Cn>:Is a name 'Cn', with 'n' in the range 0 to 15, encoded in the "CRn" field.
 <Cm>:Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.
 <op2>:Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.
 <Xt>:64-bit name of the optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field.

sysl - system instruction with result - For more information, see Op0 equals 0b01, cache maintenance, TLB maintenance, and address translation instructions for the encodings of System instructions.
1101010100101...................
          L  op1CRn CRm op2Rt   
 <Xt>:64-bit name of the general-purpose destination register, encoded in the "Rt" field.
 <op1>:Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.
 <Cn>:Is a name 'Cn', with 'n' in the range 0 to 15, encoded in the "CRn" field.
 <Cm>:Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.
 <op2>:Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.

sysp - 128-bit system instruction - 128-bit system instruction.
1101010101001...................
          L  op1CRn CRm op2Rt   
 <op1>:Is a 3-bit unsigned immediate, in the range 0 to 6, encoded in the "op1" field.
 <Cn>:Is a name 'Cn', with 'n' in the range 8 to 9, encoded in the "CRn" field.
 <Cm>:Is a name 'Cm', with 'm' in the range 0 to 7, encoded in the "CRm" field.
 <op2>:Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.
 <Xt1>:64-bit name of the first optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field.
 <Xt2>:64-bit name of the second optional general-purpose source register, defaulting to '11111', encoded as "Rt" +1. Defaults to '11111' if "Rt" = '11111'.

tbnz - test bit and branch if nonzero - compares the value of a bit in a general-purpose register with zero, and conditionally branches to a label at a PC-relative offset if the comparison is not equal. It provides a hint that this is not a subroutine call or return. does not affect condition flags.
.0110111........................
5      pb40  imm14         Rt   
 <R>
 b5 | <R>
 0 | W
 1 | X
 In assembler source code an 'X' specifier is always permitted, but a 'W' specifier is only permitted when the bit number is less than 32.
 <t>:number [0-30] of the general-purpose register to be tested or the name ZR (31), encoded in the "Rt" field.
 <imm>:bit number to be tested, in the range 0 to 63, encoded in "b5:b40".
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range +/-32KB, is encoded as "imm14" times 4.

tbz - test bit and branch if zero - compares the value of a test bit with zero, and conditionally branches to a label at a PC-relative offset if the comparison is equal. It provides a hint that this is not a subroutine call or return. does not affect condition flags.
.0110110........................
5      pb40  imm14         Rt   
 <R>
 b5 | <R>
 0 | W
 1 | X
 In assembler source code an 'X' specifier is always permitted, but a 'W' specifier is only permitted when the bit number is less than 32.
 <t>:number [0-30] of the general-purpose register to be tested or the name ZR (31), encoded in the "Rt" field.
 <imm>:bit number to be tested, in the range 0 to 63, encoded in "b5:b40".
 <label>:program label to be conditionally branched to. Its offset from the address of this instruction, in the range +/-32KB, is encoded as "imm14" times 4.

tcancel - cancel current transaction - exits Transactional state and discards all state modifications that were performed transactionally. Execution continues at the instruction that follows the TSTART instruction of the outer transaction. The destination register of the TSTART instruction of the outer transaction is written with the immediate operand of TCANCEL.
11010100011................00000
        opcimm16           op2LL
 <imm>:Is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm16" field.

tcommit - commit current transaction - commits the current transaction. If the current transaction is an outer transaction, then Transactional state is exited, and all state modifications performed transactionally are committed to the architectural state. TCOMMIT takes no inputs and returns no value. Execution of TCOMMIT is UNDEFINED in Non-transactional state.
11010101000000110011000001111111
                    CRm op2Rt   


tlbi - tlb invalidate operation - For more information, see op0==0b01, cache maintenance, TLB maintenance, and address translation instructions.
1101010100001...100x............
          L  op1CRn CRm op2Rt   
 <tlbi_op>
 op1 | CRn | CRm | op2 | <tlbi_op> | Architectural Feature
 000 | 1000 | 0001 | 000 | VMALLE1OS | 
                  
 000 | 1000 | 0001 | 001 | VAE1OS | 
                  
 000 | 1000 | 0001 | 010 | ASIDE1OS | 
                  
 000 | 1000 | 0001 | 011 | VAAE1OS | 
                  
 000 | 1000 | 0001 | 101 | VALE1OS | 
                  
 000 | 1000 | 0001 | 111 | VAALE1OS | 
                  
 000 | 1000 | 0010 | 001 | RVAE1IS | 
                  
 000 | 1000 | 0010 | 011 | RVAAE1IS | 
                  
 000 | 1000 | 0010 | 101 | RVALE1IS | 
                  
 000 | 1000 | 0010 | 111 | RVAALE1IS | 
                  
 000 | 1000 | 0011 | 000 | VMALLE1IS | 
 000 | 1000 | 0011 | 001 | VAE1IS | 
 000 | 1000 | 0011 | 010 | ASIDE1IS | 
 000 | 1000 | 0011 | 011 | VAAE1IS | 
 000 | 1000 | 0011 | 101 | VALE1IS | 
 000 | 1000 | 0011 | 111 | VAALE1IS | 
 000 | 1000 | 0101 | 001 | RVAE1OS | 
                  
 000 | 1000 | 0101 | 011 | RVAAE1OS | 
                  
 000 | 1000 | 0101 | 101 | RVALE1OS | 
                  
 000 | 1000 | 0101 | 111 | RVAALE1OS | 
                  
 000 | 1000 | 0110 | 001 | RVAE1 | 
                  
 000 | 1000 | 0110 | 011 | RVAAE1 | 
                  
 000 | 1000 | 0110 | 101 | RVALE1 | 
                  
 000 | 1000 | 0110 | 111 | RVAALE1 | 
                  
 000 | 1000 | 0111 | 000 | VMALLE1 | 
 000 | 1000 | 0111 | 001 | VAE1 | 
 000 | 1000 | 0111 | 010 | ASIDE1 | 
 000 | 1000 | 0111 | 011 | VAAE1 | 
 000 | 1000 | 0111 | 101 | VALE1 | 
 000 | 1000 | 0111 | 111 | VAALE1 | 
 000 | 1001 | 0001 | 000 | VMALLE1OSNXS | 
                  
 000 | 1001 | 0001 | 001 | VAE1OSNXS | 
                  
 000 | 1001 | 0001 | 010 | ASIDE1OSNXS | 
                  
 000 | 1001 | 0001 | 011 | VAAE1OSNXS | 
                  
 000 | 1001 | 0001 | 101 | VALE1OSNXS | 
                  
 000 | 1001 | 0001 | 111 | VAALE1OSNXS | 
                  
 000 | 1001 | 0010 | 001 | RVAE1ISNXS | 
                  
 000 | 1001 | 0010 | 011 | RVAAE1ISNXS | 
                  
 000 | 1001 | 0010 | 101 | RVALE1ISNXS | 
                  
 000 | 1001 | 0010 | 111 | RVAALE1ISNXS | 
                  
 000 | 1001 | 0011 | 000 | VMALLE1ISNXS | 
                  
 000 | 1001 | 0011 | 001 | VAE1ISNXS | 
                  
 000 | 1001 | 0011 | 010 | ASIDE1ISNXS | 
                  
 000 | 1001 | 0011 | 011 | VAAE1ISNXS | 
                  
 000 | 1001 | 0011 | 101 | VALE1ISNXS | 
                  
 000 | 1001 | 0011 | 111 | VAALE1ISNXS | 
                  
 000 | 1001 | 0101 | 001 | RVAE1OSNXS | 
                  
 000 | 1001 | 0101 | 011 | RVAAE1OSNXS | 
                  
 000 | 1001 | 0101 | 101 | RVALE1OSNXS | 
                  
 000 | 1001 | 0101 | 111 | RVAALE1OSNXS | 
                  
 000 | 1001 | 0110 | 001 | RVAE1NXS | 
                  
 000 | 1001 | 0110 | 011 | RVAAE1NXS | 
                  
 000 | 1001 | 0110 | 101 | RVALE1NXS | 
                  
 000 | 1001 | 0110 | 111 | RVAALE1NXS | 
                  
 000 | 1001 | 0111 | 000 | VMALLE1NXS | 
                  
 000 | 1001 | 0111 | 001 | VAE1NXS | 
                  
 000 | 1001 | 0111 | 010 | ASIDE1NXS | 
                  
 000 | 1001 | 0111 | 011 | VAAE1NXS | 
                  
 000 | 1001 | 0111 | 101 | VALE1NXS | 
                  
 000 | 1001 | 0111 | 111 | VAALE1NXS | 
                  
 100 | 1000 | 0000 | 001 | IPAS2E1IS | 
 100 | 1000 | 0000 | 010 | RIPAS2E1IS | 
                  
 100 | 1000 | 0000 | 101 | IPAS2LE1IS | 
 100 | 1000 | 0000 | 110 | RIPAS2LE1IS | 
                  
 100 | 1000 | 0001 | 000 | ALLE2OS | 
                  
 100 | 1000 | 0001 | 001 | VAE2OS | 
                  
 100 | 1000 | 0001 | 100 | ALLE1OS | 
                  
 100 | 1000 | 0001 | 101 | VALE2OS | 
                  
 100 | 1000 | 0001 | 110 | VMALLS12E1OS | 
                  
 100 | 1000 | 0010 | 001 | RVAE2IS | 
                  
 100 | 1000 | 0010 | 010 | VMALLWS2E1IS | 
                  
 100 | 1000 | 0010 | 101 | RVALE2IS | 
                  
 100 | 1000 | 0011 | 000 | ALLE2IS | 
 100 | 1000 | 0011 | 001 | VAE2IS | 
 100 | 1000 | 0011 | 100 | ALLE1IS | 
 100 | 1000 | 0011 | 101 | VALE2IS | 
 100 | 1000 | 0011 | 110 | VMALLS12E1IS | 
 100 | 1000 | 0100 | 000 | IPAS2E1OS | 
                  
 100 | 1000 | 0100 | 001 | IPAS2E1 | 
 100 | 1000 | 0100 | 010 | RIPAS2E1 | 
                  
 100 | 1000 | 0100 | 011 | RIPAS2E1OS | 
                  
 100 | 1000 | 0100 | 100 | IPAS2LE1OS | 
                  
 100 | 1000 | 0100 | 101 | IPAS2LE1 | 
 100 | 1000 | 0100 | 110 | RIPAS2LE1 | 
                  
 100 | 1000 | 0100 | 111 | RIPAS2LE1OS | 
                  
 100 | 1000 | 0101 | 001 | RVAE2OS | 
                  
 100 | 1000 | 0101 | 010 | VMALLWS2E1OS | 
                  
 100 | 1000 | 0101 | 101 | RVALE2OS | 
                  
 100 | 1000 | 0110 | 001 | RVAE2 | 
                  
 100 | 1000 | 0110 | 010 | VMALLWS2E1 | 
                  
 100 | 1000 | 0110 | 101 | RVALE2 | 
                  
 100 | 1000 | 0111 | 000 | ALLE2 | 
 100 | 1000 | 0111 | 001 | VAE2 | 
 100 | 1000 | 0111 | 100 | ALLE1 | 
 100 | 1000 | 0111 | 101 | VALE2 | 
 100 | 1000 | 0111 | 110 | VMALLS12E1 | 
 100 | 1001 | 0000 | 001 | IPAS2E1ISNXS | 
                  
 100 | 1001 | 0000 | 010 | RIPAS2E1ISNXS | 
                  
 100 | 1001 | 0000 | 101 | IPAS2LE1ISNXS | 
                  
 100 | 1001 | 0000 | 110 | RIPAS2LE1ISNXS | 
                  
 100 | 1001 | 0001 | 000 | ALLE2OSNXS | 
                  
 100 | 1001 | 0001 | 001 | VAE2OSNXS | 
                  
 100 | 1001 | 0001 | 100 | ALLE1OSNXS | 
                  
 100 | 1001 | 0001 | 101 | VALE2OSNXS | 
                  
 100 | 1001 | 0001 | 110 | VMALLS12E1OSNXS | 
                  
 100 | 1001 | 0010 | 001 | RVAE2ISNXS | 
                  
 100 | 1001 | 0010 | 010 | VMALLWS2E1ISNXS | 
                  
 100 | 1001 | 0010 | 101 | RVALE2ISNXS | 
                  
 100 | 1001 | 0011 | 000 | ALLE2ISNXS | 
                  
 100 | 1001 | 0011 | 001 | VAE2ISNXS | 
                  
 100 | 1001 | 0011 | 100 | ALLE1ISNXS | 
                  
 100 | 1001 | 0011 | 101 | VALE2ISNXS | 
                  
 100 | 1001 | 0011 | 110 | VMALLS12E1ISNXS | 
                  
 100 | 1001 | 0100 | 000 | IPAS2E1OSNXS | 
                  
 100 | 1001 | 0100 | 001 | IPAS2E1NXS | 
                  
 100 | 1001 | 0100 | 010 | RIPAS2E1NXS | 
                  
 100 | 1001 | 0100 | 011 | RIPAS2E1OSNXS | 
                  
 100 | 1001 | 0100 | 100 | IPAS2LE1OSNXS | 
                  
 100 | 1001 | 0100 | 101 | IPAS2LE1NXS | 
                  
 100 | 1001 | 0100 | 110 | RIPAS2LE1NXS | 
                  
 100 | 1001 | 0100 | 111 | RIPAS2LE1OSNXS | 
                  
 100 | 1001 | 0101 | 001 | RVAE2OSNXS | 
                  
 100 | 1001 | 0101 | 010 | VMALLWS2E1OSNXS | 
                  
 100 | 1001 | 0101 | 101 | RVALE2OSNXS | 
                  
 100 | 1001 | 0110 | 001 | RVAE2NXS | 
                  
 100 | 1001 | 0110 | 010 | VMALLWS2E1NXS | 
                  
 100 | 1001 | 0110 | 101 | RVALE2NXS | 
                  
 100 | 1001 | 0111 | 000 | ALLE2NXS | 
                  
 100 | 1001 | 0111 | 001 | VAE2NXS | 
                  
 100 | 1001 | 0111 | 100 | ALLE1NXS | 
                  
 100 | 1001 | 0111 | 101 | VALE2NXS | 
                  
 100 | 1001 | 0111 | 110 | VMALLS12E1NXS | 
                  
 110 | 1000 | 0001 | 000 | ALLE3OS | 
                  
 110 | 1000 | 0001 | 001 | VAE3OS | 
                  
 110 | 1000 | 0001 | 100 | PAALLOS | 
                  
 110 | 1000 | 0001 | 101 | VALE3OS | 
                  
 110 | 1000 | 0010 | 001 | RVAE3IS | 
                  
 110 | 1000 | 0010 | 101 | RVALE3IS | 
                  
 110 | 1000 | 0011 | 000 | ALLE3IS | 
 110 | 1000 | 0011 | 001 | VAE3IS | 
 110 | 1000 | 0011 | 101 | VALE3IS | 
 110 | 1000 | 0100 | 011 | RPAOS | 
                  
 110 | 1000 | 0100 | 111 | RPALOS | 
                  
 110 | 1000 | 0101 | 001 | RVAE3OS | 
                  
 110 | 1000 | 0101 | 101 | RVALE3OS | 
                  
 110 | 1000 | 0110 | 001 | RVAE3 | 
                  
 110 | 1000 | 0110 | 101 | RVALE3 | 
                  
 110 | 1000 | 0111 | 000 | ALLE3 | 
 110 | 1000 | 0111 | 001 | VAE3 | 
 110 | 1000 | 0111 | 100 | PAALL | 
                  
 110 | 1000 | 0111 | 101 | VALE3 | 
 110 | 1001 | 0001 | 000 | ALLE3OSNXS | 
                  
 110 | 1001 | 0001 | 001 | VAE3OSNXS | 
                  
 110 | 1001 | 0001 | 101 | VALE3OSNXS | 
                  
 110 | 1001 | 0010 | 001 | RVAE3ISNXS | 
                  
 110 | 1001 | 0010 | 101 | RVALE3ISNXS | 
                  
 110 | 1001 | 0011 | 000 | ALLE3ISNXS | 
                  
 110 | 1001 | 0011 | 001 | VAE3ISNXS | 
                  
 110 | 1001 | 0011 | 101 | VALE3ISNXS | 
                  
 110 | 1001 | 0101 | 001 | RVAE3OSNXS | 
                  
 110 | 1001 | 0101 | 101 | RVALE3OSNXS | 
                  
 110 | 1001 | 0110 | 001 | RVAE3NXS | 
                  
 110 | 1001 | 0110 | 101 | RVALE3NXS | 
                  
 110 | 1001 | 0111 | 000 | ALLE3NXS | 
                  
 110 | 1001 | 0111 | 001 | VAE3NXS | 
                  
 110 | 1001 | 0111 | 101 | VALE3NXS | 
                  
 <Xt>:64-bit name of the optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field.

tlbip - tlb invalidate pair operation - TLB invalidate pair operation.
1101010101001...100x............
          L  op1CRn CRm op2Rt   
 <tlbip_op>
 op1 | CRn | CRm | op2 | <tlbip_op> | Architectural Feature
 000 | 1000 | 0001 | 001 | VAE1OS | 
                  
 000 | 1000 | 0001 | 011 | VAAE1OS | 
                  
 000 | 1000 | 0001 | 101 | VALE1OS | 
                  
 000 | 1000 | 0001 | 111 | VAALE1OS | 
                  
 000 | 1000 | 0010 | 001 | RVAE1IS | 
                  
 000 | 1000 | 0010 | 011 | RVAAE1IS | 
                  
 000 | 1000 | 0010 | 101 | RVALE1IS | 
                  
 000 | 1000 | 0010 | 111 | RVAALE1IS | 
                  
 000 | 1000 | 0011 | 001 | VAE1IS | 
 000 | 1000 | 0011 | 011 | VAAE1IS | 
 000 | 1000 | 0011 | 101 | VALE1IS | 
 000 | 1000 | 0011 | 111 | VAALE1IS | 
 000 | 1000 | 0101 | 001 | RVAE1OS | 
                  
 000 | 1000 | 0101 | 011 | RVAAE1OS | 
                  
 000 | 1000 | 0101 | 101 | RVALE1OS | 
                  
 000 | 1000 | 0101 | 111 | RVAALE1OS | 
                  
 000 | 1000 | 0110 | 001 | RVAE1 | 
                  
 000 | 1000 | 0110 | 011 | RVAAE1 | 
                  
 000 | 1000 | 0110 | 101 | RVALE1 | 
                  
 000 | 1000 | 0110 | 111 | RVAALE1 | 
                  
 000 | 1000 | 0111 | 001 | VAE1 | 
 000 | 1000 | 0111 | 011 | VAAE1 | 
 000 | 1000 | 0111 | 101 | VALE1 | 
 000 | 1000 | 0111 | 111 | VAALE1 | 
 000 | 1001 | 0001 | 001 | VAE1OSNXS | 
                  
 000 | 1001 | 0001 | 011 | VAAE1OSNXS | 
                  
 000 | 1001 | 0001 | 101 | VALE1OSNXS | 
                  
 000 | 1001 | 0001 | 111 | VAALE1OSNXS | 
                  
 000 | 1001 | 0010 | 001 | RVAE1ISNXS | 
                  
 000 | 1001 | 0010 | 011 | RVAAE1ISNXS | 
                  
 000 | 1001 | 0010 | 101 | RVALE1ISNXS | 
                  
 000 | 1001 | 0010 | 111 | RVAALE1ISNXS | 
                  
 000 | 1001 | 0011 | 001 | VAE1ISNXS | 
                  
 000 | 1001 | 0011 | 011 | VAAE1ISNXS | 
                  
 000 | 1001 | 0011 | 101 | VALE1ISNXS | 
                  
 000 | 1001 | 0011 | 111 | VAALE1ISNXS | 
                  
 000 | 1001 | 0101 | 001 | RVAE1OSNXS | 
                  
 000 | 1001 | 0101 | 011 | RVAAE1OSNXS | 
                  
 000 | 1001 | 0101 | 101 | RVALE1OSNXS | 
                  
 000 | 1001 | 0101 | 111 | RVAALE1OSNXS | 
                  
 000 | 1001 | 0110 | 001 | RVAE1NXS | 
                  
 000 | 1001 | 0110 | 011 | RVAAE1NXS | 
                  
 000 | 1001 | 0110 | 101 | RVALE1NXS | 
                  
 000 | 1001 | 0110 | 111 | RVAALE1NXS | 
                  
 000 | 1001 | 0111 | 001 | VAE1NXS | 
                  
 000 | 1001 | 0111 | 011 | VAAE1NXS | 
                  
 000 | 1001 | 0111 | 101 | VALE1NXS | 
                  
 000 | 1001 | 0111 | 111 | VAALE1NXS | 
                  
 100 | 1000 | 0000 | 001 | IPAS2E1IS | 
 100 | 1000 | 0000 | 010 | RIPAS2E1IS | 
                  
 100 | 1000 | 0000 | 101 | IPAS2LE1IS | 
 100 | 1000 | 0000 | 110 | RIPAS2LE1IS | 
                  
 100 | 1000 | 0001 | 001 | VAE2OS | 
                  
 100 | 1000 | 0001 | 101 | VALE2OS | 
                  
 100 | 1000 | 0010 | 001 | RVAE2IS | 
                  
 100 | 1000 | 0010 | 101 | RVALE2IS | 
                  
 100 | 1000 | 0011 | 001 | VAE2IS | 
 100 | 1000 | 0011 | 101 | VALE2IS | 
 100 | 1000 | 0100 | 000 | IPAS2E1OS | 
                  
 100 | 1000 | 0100 | 001 | IPAS2E1 | 
 100 | 1000 | 0100 | 010 | RIPAS2E1 | 
                  
 100 | 1000 | 0100 | 011 | RIPAS2E1OS | 
                  
 100 | 1000 | 0100 | 100 | IPAS2LE1OS | 
                  
 100 | 1000 | 0100 | 101 | IPAS2LE1 | 
 100 | 1000 | 0100 | 110 | RIPAS2LE1 | 
                  
 100 | 1000 | 0100 | 111 | RIPAS2LE1OS | 
                  
 100 | 1000 | 0101 | 001 | RVAE2OS | 
                  
 100 | 1000 | 0101 | 101 | RVALE2OS | 
                  
 100 | 1000 | 0110 | 001 | RVAE2 | 
                  
 100 | 1000 | 0110 | 101 | RVALE2 | 
                  
 100 | 1000 | 0111 | 001 | VAE2 | 
 100 | 1000 | 0111 | 101 | VALE2 | 
 100 | 1001 | 0000 | 001 | IPAS2E1ISNXS | 
                  
 100 | 1001 | 0000 | 010 | RIPAS2E1ISNXS | 
                  
 100 | 1001 | 0000 | 101 | IPAS2LE1ISNXS | 
                  
 100 | 1001 | 0000 | 110 | RIPAS2LE1ISNXS | 
                  
 100 | 1001 | 0001 | 001 | VAE2OSNXS | 
                  
 100 | 1001 | 0001 | 101 | VALE2OSNXS | 
                  
 100 | 1001 | 0010 | 001 | RVAE2ISNXS | 
                  
 100 | 1001 | 0010 | 101 | RVALE2ISNXS | 
                  
 100 | 1001 | 0011 | 001 | VAE2ISNXS | 
                  
 100 | 1001 | 0011 | 101 | VALE2ISNXS | 
                  
 100 | 1001 | 0100 | 000 | IPAS2E1OSNXS | 
                  
 100 | 1001 | 0100 | 001 | IPAS2E1NXS | 
                  
 100 | 1001 | 0100 | 010 | RIPAS2E1NXS | 
                  
 100 | 1001 | 0100 | 011 | RIPAS2E1OSNXS | 
                  
 100 | 1001 | 0100 | 100 | IPAS2LE1OSNXS | 
                  
 100 | 1001 | 0100 | 101 | IPAS2LE1NXS | 
                  
 100 | 1001 | 0100 | 110 | RIPAS2LE1NXS | 
                  
 100 | 1001 | 0100 | 111 | RIPAS2LE1OSNXS | 
                  
 100 | 1001 | 0101 | 001 | RVAE2OSNXS | 
                  
 100 | 1001 | 0101 | 101 | RVALE2OSNXS | 
                  
 100 | 1001 | 0110 | 001 | RVAE2NXS | 
                  
 100 | 1001 | 0110 | 101 | RVALE2NXS | 
                  
 100 | 1001 | 0111 | 001 | VAE2NXS | 
                  
 100 | 1001 | 0111 | 101 | VALE2NXS | 
                  
 110 | 1000 | 0001 | 001 | VAE3OS | 
                  
 110 | 1000 | 0001 | 101 | VALE3OS | 
                  
 110 | 1000 | 0010 | 001 | RVAE3IS | 
                  
 110 | 1000 | 0010 | 101 | RVALE3IS | 
                  
 110 | 1000 | 0011 | 001 | VAE3IS | 
 110 | 1000 | 0011 | 101 | VALE3IS | 
 110 | 1000 | 0101 | 001 | RVAE3OS | 
                  
 110 | 1000 | 0101 | 101 | RVALE3OS | 
                  
 110 | 1000 | 0110 | 001 | RVAE3 | 
                  
 110 | 1000 | 0110 | 101 | RVALE3 | 
                  
 110 | 1000 | 0111 | 001 | VAE3 | 
 110 | 1000 | 0111 | 101 | VALE3 | 
 110 | 1001 | 0001 | 001 | VAE3OSNXS | 
                  
 110 | 1001 | 0001 | 101 | VALE3OSNXS | 
                  
 110 | 1001 | 0010 | 001 | RVAE3ISNXS | 
                  
 110 | 1001 | 0010 | 101 | RVALE3ISNXS | 
                  
 110 | 1001 | 0011 | 001 | VAE3ISNXS | 
                  
 110 | 1001 | 0011 | 101 | VALE3ISNXS | 
                  
 110 | 1001 | 0101 | 001 | RVAE3OSNXS | 
                  
 110 | 1001 | 0101 | 101 | RVALE3OSNXS | 
                  
 110 | 1001 | 0110 | 001 | RVAE3NXS | 
                  
 110 | 1001 | 0110 | 101 | RVALE3NXS | 
                  
 110 | 1001 | 0111 | 001 | VAE3NXS | 
                  
 110 | 1001 | 0111 | 101 | VALE3NXS | 
                  
 <Xt1>:64-bit name of the first optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field.
 <Xt2>:64-bit name of the second optional general-purpose source register, defaulting to '11111', encoded as "Rt" +1. Defaults to '11111' if "Rt" = '11111'.

trcit - trace instrumentation - generates an instrumentation trace packet that contains the value of the provided register.
110101010000101101110010111.....
          L  op1CRn CRm op2Rt   
 <Xt>:64-bit name of the general-purpose source register, encoded in the "Rt" field.

tsb - trace synchronization barrier - is a barrier that synchronizes the trace operations of instructions, see Trace Synchronization Barrier (TSB). If FEAT_TRF is not implemented, this instruction executes as a NOP.
11010101000000110010001001011111
                    CRm op2     


tst (immediate) - test bits (immediate) - performs a bitwise AND of a register value and an immediate value, and discards the results. It updates the condition flags based on the result.
.11100100..................11111
fpc      Nimmr  imms  Rn   Rd   
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <imm>:For the "32-bit" variant: is the bitmask immediate, encoded in "imms:immr".
 <imm>:For the "64-bit" variant: is the bitmask immediate, encoded in "N:imms:immr".
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

tst (shifted register) - test (shifted register) - performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result.
.1101010..0................11111
fpc     ftNRm   imm6  Rn   Rd   
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <shift>
 shift | <shift>
 00 | LSL
 01 | LSR
 10 | ASR
 11 | ROR
 <amount>:For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
 <amount>:For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

tstart - start transaction - starts a new transaction. If the transaction started successfully, the destination register is set to zero. If the transaction failed or was canceled, then all state modifications that were performed transactionally are discarded and the destination register is written with a nonzero value that encodes the cause of the failure.
110101010010001100110000011.....
             op1CRn CRm op2Rt   
 <Xt>:64-bit name of the general-purpose destination register, encoded in the "Rt" field.

ttest - test transaction state - writes the depth of the transaction to the destination register, or the value 0 otherwise.
110101010010001100110001011.....
             op1CRn CRm op2Rt   
 <Xt>:64-bit name of the general-purpose destination register, encoded in the "Rt" field.

ubfiz - unsigned bitfield insert in zeros - copies a bitfield of <width> bits from the least significant bits of the source register to bit position <lsb> of the destination register, setting the destination bits above and below the bitfield to zero.
.10100110.......................
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <lsb>:For the "32-bit" variant: is the bit number of the lsb of the destination bitfield, in the range 0 to 31.
 <lsb>:For the "64-bit" variant: is the bit number of the lsb of the destination bitfield, in the range 0 to 63.
 <width>:For the "32-bit" variant: is the width of the bitfield, in the range 1 to 32-<lsb>.
 <width>:For the "64-bit" variant: is the width of the bitfield, in the range 1 to 64-<lsb>.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

ubfm - unsigned bitfield move - is usually accessed via one of its aliases, which are always preferred for disassembly. If <imms> is greater than or equal to <immr>, this copies a bitfield of (<imms>-<immr>+1) bits starting from bit position <immr> in the source register to the least significant bits of the destination register. If <imms> is less than <immr>, this copies a bitfield of (<imms>+1) bits from the least significant bits of the source register to bit position (regsize-<immr>) of the destination register, where regsize is the destination register size of 32 or 64 bits. In both cases, the destination bits below and above the bitfield are set to zero.
.10100110.......................
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <immr>:For the "32-bit" variant: is the right rotate amount, in the range 0 to 31, encoded in the "immr" field.
 <immr>:For the "64-bit" variant: is the right rotate amount, in the range 0 to 63, encoded in the "immr" field.
 <imms>:For the "32-bit" variant: is the leftmost bit number to be moved from the source, in the range 0 to 31, encoded in the "imms" field.
 <imms>:For the "64-bit" variant: is the leftmost bit number to be moved from the source, in the range 0 to 63, encoded in the "imms" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

ubfx - unsigned bitfield extract - copies a bitfield of <width> bits starting from bit position <lsb> in the source register to the least significant bits of the destination register, and sets destination bits above the bitfield to zero.
.10100110.......................
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <lsb>:For the "32-bit" variant: is the bit number of the lsb of the source bitfield, in the range 0 to 31.
 <lsb>:For the "64-bit" variant: is the bit number of the lsb of the source bitfield, in the range 0 to 63.
 <width>:For the "32-bit" variant: is the width of the bitfield, in the range 1 to 32-<lsb>.
 <width>:For the "64-bit" variant: is the width of the bitfield, in the range 1 to 64-<lsb>.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

udf - permanently undefined - generates an Undefined Instruction exception (ESR_ELx.EC = 0b000000). The encodings for UDF used in this section are defined as permanently UNDEFINED.
0000000000000000................
                imm16           
 <imm>:is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm16" field. The PE ignores the value of this constant.

udiv - unsigned divide - divides the first unsigned source register value by the second unsigned source register value, and writes the result to the destination register. Dividing by zero writes the value zero to the destination register. The condition flags are not affected.
.0011010110.....000010..........
f S        Rm        1Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

umaddl - unsigned multiply-add long - multiplies two 32-bit register values, adds a 64-bit register value, and writes the result to the 64-bit destination register.
10011011101.....0...............
f54     U  Rm   0Ra   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.
 <Xa>:64-bit name of the third general-purpose source register holding the addend, encoded in the "Ra" field.

umax (immediate) - unsigned maximum (immediate) - determines the unsigned maximum of the source register value and immediate, and writes the result to the destination register.
.0010001110001..................
fpS       opc imm8    Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <uimm>:Is an unsigned immediate, in the range 0 to 255, encoded in the "imm8" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

umax (register) - unsigned maximum (register) - determines the unsigned maximum of the two source register values and writes the result to the destination register.
.0011010110.....011001..........
f S        Rm   opcodeRn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

umin (immediate) - unsigned minimum (immediate) - determines the unsigned minimum of the source register value and immediate, and writes the result to the destination register.
.0010001110011..................
fpS       opc imm8    Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <uimm>:Is an unsigned immediate, in the range 0 to 255, encoded in the "imm8" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

umin (register) - unsigned minimum (register) - determines the unsigned minimum of the two source register values and writes the result to the destination register.
.0011010110.....011011..........
f S        Rm   opcodeRn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register, encoded in the "Rm" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register, encoded in the "Rm" field.

umnegl - unsigned multiply-negate long - multiplies two 32-bit register values, negates the product, and writes the result to the 64-bit destination register.
10011011101.....111111..........
f54     U  Rm   0Ra   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.

umsubl - unsigned multiply-subtract long - multiplies two 32-bit register values, subtracts the product from a 64-bit register value, and writes the result to the 64-bit destination register.
10011011101.....1...............
f54     U  Rm   0Ra   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.
 <Xa>:64-bit name of the third general-purpose source register holding the minuend, encoded in the "Ra" field.

umulh - unsigned multiply high - multiplies two 64-bit register values, and writes bits[127:64] of the 128-bit result to the 64-bit destination register.
10011011110.....011111..........
f54     U  Rm   0Ra   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Xm>:64-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.

umull - unsigned multiply long - multiplies two 32-bit register values, and writes the result to the 64-bit destination register.
10011011101.....011111..........
f54     U  Rm   0Ra   Rn   Rd   
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.
 <Wm>:32-bit name of the second general-purpose source register holding the multiplier, encoded in the "Rm" field.

uxtb - unsigned extend byte - extracts an 8-bit value from a register, zero-extends it to the size of the register, and writes the result to the destination register.
0101001100000000000111..........
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.

uxth - unsigned extend halfword - extracts a 16-bit value from a register, zero-extends it to the size of the register, and writes the result to the destination register.
0101001100000000001111..........
fpc      Nimmr  imms  Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.

wfe - wait for event - is a hint instruction that indicates that the PE can enter a low-power state and remain there until a wakeup event occurs. Wakeup events include the event signaled as a result of executing the SEV instruction on any PE in the multiprocessor system. For more information, see Wait For Event mechanism and Send event. As described in Wait For Event mechanism and Send event, the execution of a WFE instruction that would otherwise cause entry to a low-power state can be trapped to a higher Exception level.
11010101000000110010000001011111
                    CRm op2     


wfet - wait for event with timeout - is a hint instruction that indicates that the PE can enter a low-power state and remain there until either a local timeout event or a wakeup event occurs. Wakeup events include the event signaled as a result of executing the SEV instruction on any PE in the multiprocessor system. For more information, see Wait For Event mechanism and Send event. As described in Wait For Event mechanism and Send event, the execution of a WFET instruction that would otherwise cause entry to a low-power state can be trapped to a higher Exception level.
110101010000001100010000000.....
                    CRm op2Rd   
 <Xt>:64-bit name of the general-purpose source register, encoded in the "Rd" field.

wfi - wait for interrupt - is a hint instruction that indicates that the PE can enter a low-power state and remain there until a wakeup event occurs. For more information, see Wait For Interrupt. As described in Wait For Interrupt, the execution of a WFI instruction that would otherwise cause entry to a low-power state can be trapped to a higher Exception level.
11010101000000110010000001111111
                    CRm op2     


wfit - wait for interrupt with timeout - is a hint instruction that indicates that the PE can enter a low-power state and remain there until either a local timeout event or a wakeup event occurs. For more information, see Wait For Interrupt. As described in Wait For Interrupt, the execution of a WFIT instruction that would otherwise cause entry to a low-power state can be trapped to a higher Exception level.
110101010000001100010000001.....
                    CRm op2Rd   
 <Xt>:64-bit name of the general-purpose source register, encoded in the "Rd" field.

xaflag - convert floating-point condition flags from external format to arm format - converts the state of the PSTATE.{N,Z,C,V} flags from an alternative representation required by some software to a form representing the result of an Arm floating-point scalar compare instruction.
11010101000000000100000000111111
             op1    CRm op2Rt   


xpacd, xpaci, xpaclri - strip pointer authentication code - removes the Pointer Authentication Code from an address. The address is in the specified general-purpose register for XPACI and XPACD, and is in LR for XPACLRI. The XPACD instruction is used for data addresses, and XPACI and XPACLRI are used for instruction addresses.
110110101100000101000.11111.....
f S        code2     DRn   Rd   
11010101000000110010000011111111
                    CRm op2     
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.

yield - yield - is a hint instruction. Software with a multithreading capability can use a YIELD instruction to indicate to the PE that it is performing a task, for example a spin-lock, that could be swapped out to improve overall system performance. The PE can use this hint to suspend and resume multiple software threads if it supports the capability. For more information about the recommended use of this instruction, see The YIELD instruction.
11010101000000110010000000111111
                    CRm op2     


abs - absolute value (vector) - calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111011100000101110..........
  U     ze     pcode  Rn   Rd   
0.001110..100000101110..........
 QU     ze     pcode  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

add (vector) - add (vector) - adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110111.....100001..........
  U     ze Rm   pcode Rn   Rd   
0.001110..1.....100001..........
 QU     ze Rm   pcode Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

addhn, addhn2 - add returning high narrow - adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The results are truncated. For rounded results, see RADDHN. The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half. The ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....010000..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

addp (scalar) - add pair of elements (scalar) - adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111011110001101110..........
  U     ze     pcode  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

addp (vector) - add pairwise (vector) - creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....101111..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

addv - add across vector - adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..110001101110..........
 QU     ze     pcode  Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | RESERVED
 10 | 1 | 4S
 11 | x | RESERVED

aesd - aes single round decryption - AES single round decryption.
0100111000101000010110..........
        ze         D  Rn   Rd   
 <Vd>:name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Vn>:name of the second SIMD&FP source register, encoded in the "Rn" field.

aese - aes single round encryption - AES single round encryption.
0100111000101000010010..........
        ze         D  Rn   Rd   
 <Vd>:name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Vn>:name of the second SIMD&FP source register, encoded in the "Rn" field.

aesimc - aes inverse mix columns - AES inverse mix columns.
0100111000101000011110..........
        ze         D  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

aesmc - aes mix columns - AES mix columns.
0100111000101000011010..........
        ze         D  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

and (vector) - bitwise and (vector) - performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110001.....000111..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 8B
 1 | 16B
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

bcax - bit clear and exclusive-or - performs a bitwise AND of the 128-bit vector in a source SIMD&FP register and the complement of the vector in another source SIMD&FP register, then performs a bitwise exclusive-OR of the resulting vector and the vector in a third source SIMD&FP register, and writes the result to the destination SIMD&FP register.
11001110001.....0...............
         p0Rm    Ra   Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Va>:name of the third SIMD&FP source register, encoded in the "Ra" field.

bf1cvtl, bf1cvtl2, bf2cvtl, bf2cvtl2 - 8-bit floating-point convert to bfloat16 (vector) - converts each 8-bit floating-point element from the lower or upper half of the source vector to BFloat16 while downscaling the value, and places the results in the 16-bit elements of the destination vector. BF1CVTL and BF2CVTL convert the elements from the lower half of the source vector while scaling the values by 2-UInt(FPMR.LSCALE[5:0]) and 2-UInt(FPMR.LSCALE2[5:0]), respectively. BF1CVTL2 and BF2CVTL2 convert the elements from the upper half of the source vector while scaling the values by 2-UInt(FPMR.LSCALE[5:0]) and 2-UInt(FPMR.LSCALE2[5:0]), respectively. The 8-bit floating-point encoding format for BF1CVTL and BF1CVTL2 is selected by FPMR.F8S1. The 8-bit floating-point encoding format for BF2CVTL and BF2CVTL2 is selected by FPMR.F8S2.
0.1011101x100001011110..........
 QU     ze     pcode  Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 Q | <Ta>
 0 | 8B
 1 | 16B

bfcvt - floating-point convert from single-precision to bfloat16 format (scalar) - converts the single-precision floating-point value in the 32-bit SIMD&FP source register to BFloat16 format and writes the result in the 16-bit SIMD&FP destination register. ID_AA64ISAR1_EL1.BF16 indicates whether this instruction is supported.
0001111001100011010000..........
M S     pe opcode     Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.

bfcvtn, bfcvtn2 - floating-point convert from single-precision to bfloat16 format (vector) - reads each single-precision element in the SIMD&FP source vector, converts each value to BFloat16 format, and writes the results in the lower or upper half of the SIMD&FP destination vector. The result elements are half the width of the source elements. The BFCVTN instruction writes the half-width results to the lower half of the destination vector and clears the upper half to zero. The BFCVTN2 instruction writes the results to the upper half of the destination vector without affecting the other bits in the register.
0.00111010100001011010..........
 QU     ze     pcode  Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 4H
 1 | 8H
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

bfdot (by element) - bfloat16 floating-point dot product (vector, by element) - delimits the source vectors into pairs of BFloat16 elements. The BFloat16 pair within the second source vector is specified using an immediate index. The index range is from 0 to 3 inclusive. If FEAT_EBF16 is not implemented or FPCR.EBF is 0, this instruction: If FEAT_EBF16 is implemented and FPCR.EBF is 1, then this instruction: Irrespective of FEAT_EBF16 and FPCR.EBF, this instruction: ID_AA64ISAR1_EL1.BF16 indicates whether this instruction is supported.
0.00111101......1111.0..........
 QU     zeLMRm  codeH Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 2S
 1 | 4S
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 4H
 1 | 8H
 <Vm>:name of the second SIMD&FP source register, encoded in the "M:Rm" fields.
 <index>:immediate index of a pair of 16-bit elements in the range 0 to 3, encoded in the "H:L" fields.

bfdot (vector) - bfloat16 floating-point dot product (vector) - delimits the source vectors into pairs of BFloat16 elements. If FEAT_EBF16 is not implemented or FPCR.EBF is 0, this instruction: If FEAT_EBF16 is implemented and FPCR.EBF is 1, then this instruction: Irrespective of FEAT_EBF16 and FPCR.EBF, this instruction: ID_AA64ISAR1_EL1.BF16 indicates whether this instruction is supported.
0.101110010.....111111..........
 QU     ze Rm    code Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 2S
 1 | 4S
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 4H
 1 | 8H
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

bfmlalb, bfmlalt (by element) - bfloat16 floating-point widening multiply-add long (by element) - widens the even-numbered (bottom) or odd-numbered (top) 16-bit elements in the first source vector, and the indexed element in the second source vector from Bfloat16 to single-precision format. The instruction then multiplies and adds these values without intermediate rounding to single-precision elements of the destination vector that overlap with the corresponding BFloat16 elements in the first source vector. ID_AA64ISAR1_EL1.BF16 indicates whether this instruction is supported.
0.00111111......1111.0..........
 QU     zeLMRm  codeH Rn   Rd   
 <bt>
 Q | <bt>
 0 | B
 1 | T
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, in the range V0 to V15, encoded in the "Rm" field.
 <index>:element index, in the range 0 to 7, encoded in the "H:L:M" fields.

bfmlalb, bfmlalt (vector) - bfloat16 floating-point widening multiply-add long (vector) - widens the even-numbered (bottom) or odd-numbered (top) 16-bit elements in the first and second source vectors from Bfloat16 to single-precision format. The instruction then multiplies and adds these values without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding BFloat16 elements in the source vectors. ID_AA64ISAR1_EL1.BF16 indicates whether this instruction is supported.
0.101110110.....111111..........
 QU     ze Rm    code Rn   Rd   
 <bt>
 Q | <bt>
 0 | B
 1 | T
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

bfmmla - bfloat16 floating-point matrix multiply-accumulate into 2x2 matrix - If FEAT_EBF16 is not implemented or FPCR.EBF is 0, this instruction: If FEAT_EBF16 is implemented and FPCR.EBF is 1, then this instruction: Irrespective of FEAT_EBF16 and FPCR.EBF, this instruction: ID_AA64ISAR1_EL1.BF16 indicates whether this instruction is supported.
01101110010.....111011..........
 QU     ze Rm    code Rn   Rd   
 <Vd>:name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

bic (vector, immediate) - bitwise bit clear (vector, immediate) - reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.10111100000...xxx101..........
 Qp          abcmode2 defghRd   
 <Vd>:name of the SIMD&FP register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 Q | <T>
 0 | 2S
 1 | 4S
 <imm8>:Is an 8-bit immediate encoded in "a:b:c:d:e:f:g:h".
 <amount>
 cmode<1> | <amount>
 0 | 0
 1 | 8
 defaulting to 0 if LSL is omitted.
 <amount>
 cmode<2:1> | <amount>
 00 | 0
 01 | 8
 10 | 16
 11 | 24
 defaulting to 0 if LSL is omitted.

bic (vector, register) - bitwise bit clear (vector, register) - performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110011.....000111..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 8B
 1 | 16B
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

bif - bitwise insert if false - inserts each bit from the first source SIMD&FP register into the destination SIMD&FP register if the corresponding bit of the second source SIMD&FP register is 0, otherwise leaves the bit in the destination register unchanged. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110111.....000111..........
 QU     c2 Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 8B
 1 | 16B
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

bit - bitwise insert if true - inserts each bit from the first source SIMD&FP register into the SIMD&FP destination register if the corresponding bit of the second source SIMD&FP register is 1, otherwise leaves the bit in the destination register unchanged. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110101.....000111..........
 QU     c2 Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 8B
 1 | 16B
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

bsl - bitwise select - sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110011.....000111..........
 QU     c2 Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 8B
 1 | 16B
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

cls (vector) - count leading sign bits (vector) - counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..100000010010..........
 QU     ze     pcode  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

clz (vector) - count leading zero bits (vector) - counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..100000010010..........
 QU     ze     pcode  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

cmeq (register) - compare bitwise equal (vector) - compares each vector element from the first source SIMD&FP register with the corresponding vector element from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110111.....100011..........
  U     ze Rm   pcode Rn   Rd   
0.101110..1.....100011..........
 QU     ze Rm   pcode Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

cmeq (zero) - compare bitwise equal to zero (vector) - reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111011100000100110..........
  U     ze         p  Rn   Rd   
0.001110..100000100110..........
 QU     ze         p  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

cmge (register) - compare signed greater than or equal (vector) - compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than or equal to the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110111.....001111..........
  U     ze Rm       q Rn   Rd   
0.001110..1.....001111..........
 QU     ze Rm       q Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

cmge (zero) - compare signed greater than or equal to zero (vector) - reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111011100000100010..........
  U     ze         p  Rn   Rd   
0.101110..100000100010..........
 QU     ze         p  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

cmgt (register) - compare signed greater than (vector) - compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is greater than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110111.....001101..........
  U     ze Rm       q Rn   Rd   
0.001110..1.....001101..........
 QU     ze Rm       q Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

cmgt (zero) - compare signed greater than zero (vector) - reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111011100000100010..........
  U     ze         p  Rn   Rd   
0.001110..100000100010..........
 QU     ze         p  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

cmhi (register) - compare unsigned higher (vector) - compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110111.....001101..........
  U     ze Rm       q Rn   Rd   
0.101110..1.....001101..........
 QU     ze Rm       q Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

cmhs (register) - compare unsigned higher or same (vector) - compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110111.....001111..........
  U     ze Rm       q Rn   Rd   
0.101110..1.....001111..........
 QU     ze Rm       q Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

cmle (zero) - compare signed less than or equal to zero (vector) - reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111011100000100110..........
  U     ze         p  Rn   Rd   
0.101110..100000100110..........
 QU     ze         p  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

cmlt (zero) - compare signed less than zero (vector) - reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111011100000101010..........
  U     ze     pcode  Rn   Rd   
0.001110..100000101010..........
 QU     ze     pcode  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

cmtst - compare bitwise test bits nonzero (vector) - reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110111.....100011..........
  U     ze Rm   pcode Rn   Rd   
0.001110..1.....100011..........
 QU     ze Rm   pcode Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

cnt - population count per byte - counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..100000010110..........
 QU     ze     pcode  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | x | RESERVED
 1x | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

dup (element) - duplicate vector element to vector or scalar - duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110000.....000001..........
  p        imm5  imm4 Rn   Rd   
0.001110000.....000001..........
 Qp        imm5  imm4 Rn   Rd   
 <V>
 imm5 | <V>
 x0000 | RESERVED
 xxxx1 | B
 xxx10 | H
 xx100 | S
 x1000 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <T>
 imm5 | <T>
 x0000 | RESERVED
 xxxx1 | B
 xxx10 | H
 xx100 | S
 x1000 | D
 <T>
 imm5 | Q | <T>
 x0000 | x | RESERVED
 xxxx1 | 0 | 8B
 xxxx1 | 1 | 16B
 xxx10 | 0 | 4H
 xxx10 | 1 | 8H
 xx100 | 0 | 2S
 xx100 | 1 | 4S
 x1000 | 0 | RESERVED
 x1000 | 1 | 2D
 <index>
 imm5 | <index>
 x0000 | RESERVED
 xxxx1 | UInt(imm5<4:1>)
 xxx10 | UInt(imm5<4:2>)
 xx100 | UInt(imm5<4:3>)
 x1000 | UInt(imm5<4>)
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ts>
 imm5 | <Ts>
 x0000 | RESERVED
 xxxx1 | B
 xxx10 | H
 xx100 | S
 x1000 | D

dup (general) - duplicate general-purpose register to vector - duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110000.....000011..........
 Qp        imm5  imm4 Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 imm5 | Q | <T>
 x0000 | x | RESERVED
 xxxx1 | 0 | 8B
 xxxx1 | 1 | 16B
 xxx10 | 0 | 4H
 xxx10 | 1 | 8H
 xx100 | 0 | 2S
 xx100 | 1 | 4S
 x1000 | 0 | RESERVED
 x1000 | 1 | 2D
 <R>
 imm5 | <R>
 x0000 | RESERVED
 xxxx1 | W
 xxx10 | W
 xx100 | W
 x1000 | X
 Unspecified bits in "imm5" are ignored but should be set to zero by an assembler.
 <n>:number [0-30] of the general-purpose source register or ZR (31), encoded in the "Rn" field.

eor (vector) - bitwise exclusive-or (vector) - performs a bitwise exclusive-OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110001.....000111..........
 QU     c2 Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 8B
 1 | 16B
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

eor3 - three-way exclusive-or - performs a three-way exclusive-OR of the values in the three source SIMD&FP registers, and writes the result to the destination SIMD&FP register.
11001110000.....0...............
         p0Rm    Ra   Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Va>:name of the third SIMD&FP source register, encoded in the "Ra" field.

ext - extract vector from pair of vectors - extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.  Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110000.....0....0..........
 Q      p2 Rm    imm4 Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 8B
 1 | 16B
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.
 <index>
 Q | imm4<3> | <index>
 0 | 0 | UInt(imm4<2:0>)
 0 | 1 | RESERVED
 1 | x | UInt(imm4)

f1cvtl, f1cvtl2, f2cvtl, f2cvtl2 - 8-bit floating-point convert to half-precision (vector) - converts each 8-bit floating-point element from the lower or upper half of the source vector to half-precision while downscaling the value, and places the results in the 16-bit elements of the destination vector. F1CVTL and F2CVTL convert the elements from the lower half of the source vector while scaling the values by 2-UInt(FPMR.LSCALE[3:0]) and 2-UInt(FPMR.LSCALE2[3:0]), respectively. F1CVTL2 and F2CVTL2 convert the elements from the upper half of the source vector while scaling the values by 2-UInt(FPMR.LSCALE[3:0]) and 2-UInt(FPMR.LSCALE2[3:0]), respectively. The 8-bit floating-point encoding format for F1CVTL and F1CVTL2 is selected by FPMR.F8S1. The 8-bit floating-point encoding format for F2CVTL and F2CVTL2 is selected by FPMR.F8S2.
0.1011100x100001011110..........
 QU     ze     pcode  Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 Q | <Ta>
 0 | 8B
 1 | 16B

fabd - floating-point absolute difference (vector) - subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110110.....000101..........
  U     a  Rm     ode Rn   Rd   
011111101.1.....110101..........
  U      z Rm   pcode Rn   Rd   
0.101110110.....000101..........
 QU     a  Rm     ode Rn   Rd   
0.1011101.1.....110101..........
 QU      z Rm   pcode Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fabs (scalar) - floating-point absolute value (scalar) - calculates the absolute value in the SIMD&FP source register and writes the result to the SIMD&FP destination register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..100000110000..........
M S     pe     pc     Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fabs (vector) - floating-point absolute value (vector) - calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00111011111000111110..........
 QU     a      pcode  Rn   Rd   
0.0011101.100000111110..........
 QU      z     pcode  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

facge - floating-point absolute compare greater than or equal (vector) - compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110010.....001011..........
  U     E  Rm       c Rn   Rd   
011111100.1.....111011..........
  U     Ez Rm       c Rn   Rd   
0.101110010.....001011..........
 QU     E  Rm       c Rn   Rd   
0.1011100.1.....111011..........
 QU     Ez Rm       c Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

facgt - floating-point absolute compare greater than (vector) - compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110110.....001011..........
  U     E  Rm       c Rn   Rd   
011111101.1.....111011..........
  U     Ez Rm       c Rn   Rd   
0.101110110.....001011..........
 QU     E  Rm       c Rn   Rd   
0.1011101.1.....111011..........
 QU     Ez Rm       c Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fadd (scalar) - floating-point add (scalar) - adds the floating-point values of the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..1.....001010..........
M S     pe Rm      p  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

fadd (vector) - floating-point add (vector) - adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110010.....000101..........
 QU     a  Rm     ode Rn   Rd   
0.0011100.1.....110101..........
 QU      z Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

faddp (scalar) - floating-point add pair of elements (scalar) - adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111000110000110110..........
  U      z     pcode  Rn   Rd   
011111100.110000110110..........
  U      z     pcode  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <T>
 sz | <T>
 0 | 2S
 1 | 2D

faddp (vector) - floating-point add pairwise (vector) - creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110010.....000101..........
 QU     a  Rm     ode Rn   Rd   
0.1011100.1.....110101..........
 QU      z Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

famax - floating-point absolute maximum - determines the maximum absolute value from floating-point elements of the first source vector and the corresponding floating-point elements of the second source vector, and places the results in the corresponding elements of the destination vector. Regardless of the value of FPCR.AH, the behavior is as follows:
0.001110110.....000111..........
 QU     a  Rm     ode Rn   Rd   
0.0011101x1.....110111..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 size<0> | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

famin - floating-point absolute minimum - determines the minimum absolute value from floating-point elements of the first source vector and the corresponding floating-point elements of the second source vector, and places the results in the corresponding elements of the destination vector. Regardless of the value of FPCR.AH, the behavior is as follows:
0.101110110.....000111..........
 QU     a  Rm     ode Rn   Rd   
0.1011101x1.....110111..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 size<0> | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fcadd - floating-point complex add - operates on complex numbers that are represented in SIMD&FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on the corresponding complex number element pairs from the two source registers: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..0.....111.01..........
 QU     ze Rm      t  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.
 <rotate>
 rot | <rotate>
 0 | 90
 1 | 270

fccmp - floating-point conditional quiet compare (scalar) - compares the two SIMD&FP source register values and writes the result to the PSTATE.{N, Z, C, V} flags. If the condition does not pass, then the PSTATE.{N, Z, C, V} flags are set to the flag bit specifier. raises an Invalid Operation floating-point exception if either or both of the operands is a signaling NaN. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..1.........01.....0....
M S     pe Rm   cond  Rn   pnzcv
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <nzcv>:flag bit specifier, an immediate in the range 0 to 15, giving the alternative state for the 4-bit NZCV condition flags, encoded in the "nzcv" field.
 <cond>
 cond | <cond>
 0000 | EQ
 0001 | NE
 0010 | CS
 0011 | CC
 0100 | MI
 0101 | PL
 0110 | VS
 0111 | VC
 1000 | HI
 1001 | LS
 1010 | GE
 1011 | LT
 1100 | GT
 1101 | LE
 1110 | AL
 1111 | NV
 <Sn>:32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Dn>:64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

fccmpe - floating-point conditional signaling compare (scalar) - compares the two SIMD&FP source register values and writes the result to the PSTATE.{N, Z, C, V} flags. If the condition does not pass, then the PSTATE.{N, Z, C, V} flags are set to the flag bit specifier. raises an Invalid Operation floating-point exception if either or both of the operands is any type of NaN. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..1.........01.....1....
M S     pe Rm   cond  Rn   pnzcv
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <nzcv>:flag bit specifier, an immediate in the range 0 to 15, giving the alternative state for the 4-bit NZCV condition flags, encoded in the "nzcv" field.
 <cond>
 cond | <cond>
 0000 | EQ
 0001 | NE
 0010 | CS
 0011 | CC
 0100 | MI
 0101 | PL
 0110 | VS
 0111 | VC
 1000 | HI
 1001 | LS
 1010 | GE
 1011 | LT
 1100 | GT
 1101 | LE
 1110 | AL
 1111 | NV
 <Sn>:32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Dn>:64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

fcmeq (register) - floating-point compare equal (vector) - compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110010.....001001..........
  U     E  Rm       c Rn   Rd   
010111100.1.....111001..........
  U     Ez Rm       c Rn   Rd   
0.001110010.....001001..........
 QU     E  Rm       c Rn   Rd   
0.0011100.1.....111001..........
 QU     Ez Rm       c Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fcmeq (zero) - floating-point compare equal to zero (vector) - reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111011111000110110..........
  U     a          p  Rn   Rd   
010111101.100000110110..........
  U      z         p  Rn   Rd   
0.00111011111000110110..........
 QU     a          p  Rn   Rd   
0.0011101.100000110110..........
 QU      z         p  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcmge (register) - floating-point compare greater than or equal (vector) - reads each floating-point value in the first source SIMD&FP register and if the value is greater than or equal to the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110010.....001001..........
  U     E  Rm       c Rn   Rd   
011111100.1.....111001..........
  U     Ez Rm       c Rn   Rd   
0.101110010.....001001..........
 QU     E  Rm       c Rn   Rd   
0.1011100.1.....111001..........
 QU     Ez Rm       c Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fcmge (zero) - floating-point compare greater than or equal to zero (vector) - reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111011111000110010..........
  U     a          p  Rn   Rd   
011111101.100000110010..........
  U      z         p  Rn   Rd   
0.10111011111000110010..........
 QU     a          p  Rn   Rd   
0.1011101.100000110010..........
 QU      z         p  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcmgt (register) - floating-point compare greater than (vector) - reads each floating-point value in the first source SIMD&FP register and if the value is greater than the corresponding floating-point value in the second source SIMD&FP register sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110110.....001001..........
  U     E  Rm       c Rn   Rd   
011111101.1.....111001..........
  U     Ez Rm       c Rn   Rd   
0.101110110.....001001..........
 QU     E  Rm       c Rn   Rd   
0.1011101.1.....111001..........
 QU     Ez Rm       c Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fcmgt (zero) - floating-point compare greater than zero (vector) - reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111011111000110010..........
  U     a          p  Rn   Rd   
010111101.100000110010..........
  U      z         p  Rn   Rd   
0.00111011111000110010..........
 QU     a          p  Rn   Rd   
0.0011101.100000110010..........
 QU      z         p  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcmla - floating-point complex multiply accumulate - operates on complex numbers that are represented in SIMD&FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on the corresponding complex number element pairs from the two source registers and the destination register: The multiplication and addition operations are performed as a fused multiply-add, without any intermediate rounding. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..0.....110..1..........
 QU     ze Rm      ot Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.
 <rotate>
 rot | <rotate>
 00 | 0
 01 | 90
 10 | 180
 11 | 270

fcmla (by element) - floating-point complex multiply accumulate (by element) - operates on complex numbers that are represented in SIMD&FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on complex numbers from the first source register and the destination register with the specified complex number from the second source register: The multiplication and addition operations are performed as a fused multiply-add, without any intermediate rounding. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101111........0..1.0..........
 QU     zeLMRm   ot H Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | RESERVED
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "M:Rm" fields.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L)
 10 | UInt(H)
 11 | RESERVED
 <rotate>
 rot | <rotate>
 00 | 0
 01 | 90
 10 | 180
 11 | 270

fcmle (zero) - floating-point compare less than or equal to zero (vector) - reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111011111000110110..........
  U     a          p  Rn   Rd   
011111101.100000110110..........
  U      z         p  Rn   Rd   
0.10111011111000110110..........
 QU     a          p  Rn   Rd   
0.1011101.100000110110..........
 QU      z         p  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcmlt (zero) - floating-point compare less than zero (vector) - reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111011111000111010..........
  U     a      pcode  Rn   Rd   
010111101.100000111010..........
  U      z     pcode  Rn   Rd   
0.00111011111000111010..........
 QU     a      pcode  Rn   Rd   
0.0011101.100000111010..........
 QU      z     pcode  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcmp - floating-point quiet compare (scalar) - compares the two SIMD&FP source register values, or the first SIMD&FP source register value and zero. It writes the result to the PSTATE.{N, Z, C, V} flags. raises an Invalid Operation floating-point exception if either or both of the operands is a signaling NaN. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..1.....001000.....0x000
M S     pe Rm   op    Rn   pc   
 <Hn>:For the "Half-precision" variant: is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hn>:For the "Half-precision, zero" variant: is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Sn>:For the "Single-precision" variant: is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Sn>:For the "Single-precision, zero" variant: is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Dn>:For the "Double-precision" variant: is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:For the "Double-precision, zero" variant: is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

fcmpe - floating-point signaling compare (scalar) - compares the two SIMD&FP source register values, or the first SIMD&FP source register value and zero. It writes the result to the PSTATE.{N, Z, C, V} flags. raises an Invalid Operation floating-point exception if either or both of the operands is any type of NaN. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..1.....001000.....1x000
M S     pe Rm   op    Rn   pc   
 <Hn>:For the "Half-precision" variant: is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hn>:For the "Half-precision, zero" variant: is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Sn>:For the "Single-precision" variant: is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Sn>:For the "Single-precision, zero" variant: is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Dn>:For the "Double-precision" variant: is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:For the "Double-precision, zero" variant: is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

fcsel - floating-point conditional select (scalar) - allows the SIMD&FP destination register to take the value from either one or the other of two SIMD&FP source registers. If the condition passes, the first SIMD&FP source register value is taken, otherwise the second SIMD&FP source register value is taken. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..1.........11..........
M S     pe Rm   cond  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <cond>
 cond | <cond>
 0000 | EQ
 0001 | NE
 0010 | CS
 0011 | CC
 0100 | MI
 0101 | PL
 0110 | VS
 0111 | VC
 1000 | HI
 1001 | LS
 1010 | GE
 1011 | LT
 1100 | GT
 1101 | LE
 1110 | AL
 1111 | NV
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

fcvt - floating-point convert precision (scalar) - converts the floating-point value in the SIMD&FP source register to the precision for the destination register data type using the rounding mode that is determined by the FPCR and writes the result to the SIMD&FP destination register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..10001..10000..........
M S     pe     pc     Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtas (scalar simd&fp) - floating-point convert to signed integer, rounding to nearest with ties to away (scalar simd&fp) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..111010000000..........
f S     pe deode      Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtas (scalar) - floating-point convert to signed integer, rounding to nearest with ties to away (scalar) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round to Nearest with Ties to Away rounding mode, and writes the result to the general-purpose destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..100100000000..........
f S     pe deode      Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtas (vector) - floating-point convert to signed integer, rounding to nearest with ties to away (vector) - converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111001111001110010..........
  U     a      pcode  Rn   Rd   
010111100.100001110010..........
  U      z     pcode  Rn   Rd   
0.00111001111001110010..........
 QU     a      pcode  Rn   Rd   
0.0011100.100001110010..........
 QU      z     pcode  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtau (scalar simd&fp) - floating-point convert to unsigned integer, rounding to nearest with ties to away (scalar simd&fp) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..111011000000..........
f S     pe deode      Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtau (scalar) - floating-point convert to unsigned integer, rounding to nearest with ties to away (scalar) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round to Nearest with Ties to Away rounding mode, and writes the result to the general-purpose destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..100101000000..........
f S     pe deode      Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtau (vector) - floating-point convert to unsigned integer, rounding to nearest with ties to away (vector) - converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111001111001110010..........
  U     a      pcode  Rn   Rd   
011111100.100001110010..........
  U      z     pcode  Rn   Rd   
0.10111001111001110010..........
 QU     a      pcode  Rn   Rd   
0.1011100.100001110010..........
 QU      z     pcode  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtl, fcvtl2 - floating-point convert to higher precision long (vector) - reads each element in a vector in the SIMD&FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the FPCR, and writes each result to the equivalent element of the vector in the SIMD&FP destination register. Where the operation lengthens a 64-bit vector to a 128-bit vector, the FCVTL2 variant operates on the elements in the top 64 bits of the source register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.0011100.100001011110..........
 QU      z     pcode  Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 sz | <Ta>
 0 | 4S
 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 sz | Q | <Tb>
 0 | 0 | 4H
 0 | 1 | 8H
 1 | 0 | 2S
 1 | 1 | 4S

fcvtms (scalar simd&fp) - floating-point convert to signed integer, rounding toward minus infinity (scalar simd&fp) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round toward Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..110100000000..........
f S     pe deode      Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtms (scalar) - floating-point convert to signed integer, rounding toward minus infinity (scalar) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round towards Minus Infinity rounding mode, and writes the result to the general-purpose destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..110000000000..........
f S     pe deode      Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtms (vector) - floating-point convert to signed integer, rounding toward minus infinity (vector) - converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111001111001101110..........
  U     2          1  Rn   Rd   
010111100.100001101110..........
  U     2z         1  Rn   Rd   
0.00111001111001101110..........
 QU     2          1  Rn   Rd   
0.0011100.100001101110..........
 QU     2z         1  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtmu (scalar simd&fp) - floating-point convert to unsigned integer, rounding toward minus infinity (scalar simd&fp) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round toward Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..110101000000..........
f S     pe deode      Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtmu (scalar) - floating-point convert to unsigned integer, rounding toward minus infinity (scalar) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round towards Minus Infinity rounding mode, and writes the result to the general-purpose destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..110001000000..........
f S     pe deode      Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtmu (vector) - floating-point convert to unsigned integer, rounding toward minus infinity (vector) - converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111001111001101110..........
  U     2          1  Rn   Rd   
011111100.100001101110..........
  U     2z         1  Rn   Rd   
0.10111001111001101110..........
 QU     2          1  Rn   Rd   
0.1011100.100001101110..........
 QU     2z         1  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtn (half-precision to 8-bit floating-point) - half-precision to 8-bit floating-point convert and narrow (vector) - converts half-precision elements of the two source vectors to 8-bit floating-point while scaling the values by 2SInt(FPMR.NSCALE[4:0]), and places the in-order results in the 8-bit elements of the destination vector. The 8-bit floating-point encoding format is selected by FPMR.F8D.
0.001110010.....111101..........
 QU     ze Rm    code Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 8B
 1 | 16B
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 4H
 1 | 8H
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fcvtn, fcvtn2 (double to single-precision, single to half-precision) - floating-point convert to lower precision narrow (vector) - reads each vector element in the SIMD&FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the FPCR. FCVTN writes the vector to the lower half of the destination register and clears the upper half. FCVTN2 writes the vector to the upper half of the destination register without affecting the other bits of the register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.0011100.100001011010..........
 QU      z     pcode  Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 sz | Q | <Tb>
 0 | 0 | 4H
 0 | 1 | 8H
 1 | 0 | 2S
 1 | 1 | 4S
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 sz | <Ta>
 0 | 4S
 1 | 2D

fcvtn, fcvtn2 (single-precision to 8-bit floating-point) - single-precision to 8-bit floating-point convert and narrow (vector) - converts each single-precision element of the two source vectors to 8-bit floating-point while scaling the value by 2SInt(FPMR.NSCALE), and places the in-order results in the 8-bit elements of the lower or upper half of the destination vector. FCVTN writes the results to the lower half of the destination vector and clears the upper half. FCVTN2 writes the results to the upper half of the destination vector without affecting the other bits of the vector. The 8-bit floating-point encoding format is selected by FPMR.F8D.
0.001110000.....111101..........
 QU     ze Rm    code Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 8B
 1 | 16B
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fcvtns (scalar simd&fp) - floating-point convert to signed integer, rounding to nearest with ties to even (scalar simd&fp) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round to Nearest with Ties to Even rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..101010000000..........
f S     pe deode      Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtns (scalar) - floating-point convert to signed integer, rounding to nearest with ties to even (scalar) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round to Nearest rounding mode, and writes the result to the general-purpose destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..100000000000..........
f S     pe deode      Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtns (vector) - floating-point convert to signed integer, rounding to nearest with ties to even (vector) - converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111001111001101010..........
  U     2          1  Rn   Rd   
010111100.100001101010..........
  U     2z         1  Rn   Rd   
0.00111001111001101010..........
 QU     2          1  Rn   Rd   
0.0011100.100001101010..........
 QU     2z         1  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtnu (scalar simd&fp) - floating-point convert to unsigned integer, rounding to nearest with ties to even (scalar simd&fp) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round to Nearest with Ties to Even rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..101011000000..........
f S     pe deode      Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtnu (scalar) - floating-point convert to unsigned integer, rounding to nearest with ties to even (scalar) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round to Nearest rounding mode, and writes the result to the general-purpose destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..100001000000..........
f S     pe deode      Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtnu (vector) - floating-point convert to unsigned integer, rounding to nearest with ties to even (vector) - converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111001111001101010..........
  U     2          1  Rn   Rd   
011111100.100001101010..........
  U     2z         1  Rn   Rd   
0.10111001111001101010..........
 QU     2          1  Rn   Rd   
0.1011100.100001101010..........
 QU     2z         1  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtps (scalar simd&fp) - floating-point convert to signed integer, rounding toward plus infinity (scalar simd&fp) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round toward Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..110010000000..........
f S     pe deode      Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtps (scalar) - floating-point convert to signed integer, rounding toward plus infinity (scalar) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round towards Plus Infinity rounding mode, and writes the result to the general-purpose destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..101000000000..........
f S     pe deode      Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtps (vector) - floating-point convert to signed integer, rounding toward plus infinity (vector) - converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111011111001101010..........
  U     2          1  Rn   Rd   
010111101.100001101010..........
  U     2z         1  Rn   Rd   
0.00111011111001101010..........
 QU     2          1  Rn   Rd   
0.0011101.100001101010..........
 QU     2z         1  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtpu (scalar simd&fp) - floating-point convert to unsigned integer, rounding toward plus infinity (scalar simd&fp) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round toward Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..110011000000..........
f S     pe deode      Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtpu (scalar) - floating-point convert to unsigned integer, rounding toward plus infinity (scalar) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round towards Plus Infinity rounding mode, and writes the result to the general-purpose destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..101001000000..........
f S     pe deode      Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtpu (vector) - floating-point convert to unsigned integer, rounding toward plus infinity (vector) - converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111011111001101010..........
  U     2          1  Rn   Rd   
011111101.100001101010..........
  U     2z         1  Rn   Rd   
0.10111011111001101010..........
 QU     2          1  Rn   Rd   
0.1011101.100001101010..........
 QU     2z         1  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtxn, fcvtxn2 - floating-point convert to lower precision narrow, rounding to odd (vector) - reads each vector element in the source SIMD&FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&FP register. The FCVTXN instruction writes the vector to the lower half of the destination register and clears the upper half. The FCVTXN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111001100001011010..........
  U     ze     pcode  Rn   Rd   
0.10111001100001011010..........
 QU     ze     pcode  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 Q | <Tb>
 0 | 2S
 1 | 4S
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtzs (scalar simd&fp) - floating-point convert to signed integer, rounding toward zero (scalar simd&fp) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round toward Zero rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..110110000000..........
f S     pe deode      Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtzs (scalar, fixed-point) - floating-point convert to signed fixed-point, rounding toward zero (scalar) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..011000................
f S     pe deodescale Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <fbits>:For the "Double-precision to 32-bit", "Half-precision to 32-bit", and "Single-precision to 32-bit" variants: is the number of bits after the binary point in the fixed-point destination, in the range 1 to 32, encoded as 64 minus "scale".
 <fbits>:For the "Double-precision to 64-bit", "Half-precision to 64-bit", and "Single-precision to 64-bit" variants: is the number of bits after the binary point in the fixed-point destination, in the range 1 to 64, encoded as 64 minus "scale".
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtzs (scalar, integer) - floating-point convert to signed integer, rounding toward zero (scalar) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..111000000000..........
f S     pe deode      Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtzs (vector, fixed-point) - floating-point convert to signed fixed-point, rounding toward zero (vector) - converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
010111110!= 0000!= 0000!= 0000!= 0000...111111..........
  U      immhmmbpcode Rn   Rd   
0.0011110!= 0000!= 0000!= 0000!= 0000...111111..........
 QU      immhmmbpcode Rn   Rd   
 <V>
 immh | <V>
 0001 | RESERVED
 001x | H
 01xx | S
 1xxx | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <fbits>
 immh | <fbits>
 0001 | RESERVED
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <fbits>
 immh | <fbits>
 0001 | RESERVED
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | x | RESERVED
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtzs (vector, integer) - floating-point convert to signed integer, rounding toward zero (vector) - converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111011111001101110..........
  U     2          1  Rn   Rd   
010111101.100001101110..........
  U     2z         1  Rn   Rd   
0.00111011111001101110..........
 QU     2          1  Rn   Rd   
0.0011101.100001101110..........
 QU     2z         1  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtzu (scalar simd&fp) - floating-point convert to unsigned integer, rounding toward zero (scalar simd&fp) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round toward Zero rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..110111000000..........
f S     pe deode      Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtzu (scalar, fixed-point) - floating-point convert to unsigned fixed-point, rounding toward zero (scalar) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..011001................
f S     pe deodescale Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <fbits>:For the "Double-precision to 32-bit", "Half-precision to 32-bit", and "Single-precision to 32-bit" variants: is the number of bits after the binary point in the fixed-point destination, in the range 1 to 32, encoded as 64 minus "scale".
 <fbits>:For the "Double-precision to 64-bit", "Half-precision to 64-bit", and "Single-precision to 64-bit" variants: is the number of bits after the binary point in the fixed-point destination, in the range 1 to 64, encoded as 64 minus "scale".
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtzu (scalar, integer) - floating-point convert to unsigned integer, rounding toward zero (scalar) - converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..111001000000..........
f S     pe deode      Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtzu (vector, fixed-point) - floating-point convert to unsigned fixed-point, rounding toward zero (vector) - converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
011111110!= 0000!= 0000!= 0000!= 0000...111111..........
  U      immhmmbpcode Rn   Rd   
0.1011110!= 0000!= 0000!= 0000!= 0000...111111..........
 QU      immhmmbpcode Rn   Rd   
 <V>
 immh | <V>
 0001 | RESERVED
 001x | H
 01xx | S
 1xxx | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <fbits>
 immh | <fbits>
 0001 | RESERVED
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <fbits>
 immh | <fbits>
 0001 | RESERVED
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | x | RESERVED
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fcvtzu (vector, integer) - floating-point convert to unsigned integer, rounding toward zero (vector) - converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111011111001101110..........
  U     2          1  Rn   Rd   
011111101.100001101110..........
  U     2z         1  Rn   Rd   
0.10111011111001101110..........
 QU     2          1  Rn   Rd   
0.1011101.100001101110..........
 QU     2z         1  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fdiv (scalar) - floating-point divide (scalar) - divides the floating-point value of the first source SIMD&FP register by the floating-point value of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..1.....000110..........
M S     pe Rm   code  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

fdiv (vector) - floating-point divide (vector) - divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110010.....001111..........
 QU     a  Rm     ode Rn   Rd   
0.1011100.1.....111111..........
 QU      z Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fdot (8-bit floating-point to half-precision, by element) - 8-bit floating-point dot product to half-precision (vector, by element) - computes the fused sum-of-products of a group of two 8-bit floating-point values held in each 16-bit element of the first source vector and a group of two 8-bit floating-point values in an indexed 16-bit element of the second source vector. The half-precision sum-of-products are scaled by 2-UInt(FPMR.LSCALE[3:0]), before being destructively added without intermediate rounding to the corresponding half-precision elements of the destination vector. The 8-bit floating-point groups within the second source vector are specified using an immediate index. The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.
0.00111101......0000.0..........
 QU     zeLMRm  codeH Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 4H
 1 | 8H
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 8B
 1 | 16B
 <Vm>:name of the second SIMD&FP source register, in the range V0 to V15, encoded in the "Rm" field.
 <index>:immediate index of a group of two 8-bit elements, in the range 0 to 7, encoded in the "H:L:M" fields.

fdot (8-bit floating-point to half-precision, vector) - 8-bit floating-point dot product to half-precision (vector) - computes the fused sum-of-products of a group of two 8-bit floating-point values held in each 16-bit element of the first and second source vectors. The half-precision sum-of-products are scaled by 2-UInt(FPMR.LSCALE[3:0]), before being destructively added without intermediate rounding to the corresponding half-precision elements of the destination vector. The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.
0.001110010.....111111..........
 QU     ze Rm    code Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 4H
 1 | 8H
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 8B
 1 | 16B
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fdot (8-bit floating-point to single-precision, by element) - 8-bit floating-point dot product to single-precision (vector, by element) - computes the fused sum-of-products of a group of four 8-bit floating-point values held in each 32-bit element of the first source vector and a group of four 8-bit floating-point values in an indexed 32-bit element of the second source vector. The single-precision sum-of-products are scaled by 2-UInt(FPMR.LSCALE), before being destructively added without intermediate rounding to the corresponding single-precision elements of the destination vector. The 8-bit floating-point groups within the second source vector are specified using an immediate index. The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.
0.00111100......0000.0..........
 QU     zeLMRm  codeH Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 2S
 1 | 4S
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 8B
 1 | 16B
 <Vm>:name of the second SIMD&FP source register, encoded in the "M:Rm" fields.
 <index>:immediate index of a 32-bit group of four 8-bit values, in the range 0 to 3, encoded in the "H:L" fields.

fdot (8-bit floating-point to single-precision, vector) - 8-bit floating-point dot product to single-precision (vector) - computes the fused sum-of-products of a group of four 8-bit floating-point values held in each 32-bit element of the first and second source vectors. The single-precision sum-of-products are scaled by 2-UInt(FPMR.LSCALE), before being destructively added without intermediate rounding to the corresponding single-precision elements of the destination vector. The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.
0.001110000.....111111..........
 QU     ze Rm    code Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 2S
 1 | 4S
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 8B
 1 | 16B
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fjcvtzs - floating-point javascript convert to signed fixed-point, rounding toward zero - converts the double-precision floating-point value in the SIMD&FP source register to a 32-bit signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register. If the result is too large to be represented as a signed 32-bit integer, then the result is the integer modulo 232, as held in a 32-bit signed integer. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0001111001111110000000..........
f S     pe deode      Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fmadd - floating-point fused multiply-add (scalar) - multiplies the values of the first two SIMD&FP source registers, adds the product to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011111..0.....0...............
M S     pe1Rm   0Ra   Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field.
 <Ha>:16-bit name of the third SIMD&FP source register holding the addend, encoded in the "Ra" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field.
 <Sa>:32-bit name of the third SIMD&FP source register holding the addend, encoded in the "Ra" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field.
 <Da>:64-bit name of the third SIMD&FP source register holding the addend, encoded in the "Ra" field.

fmax (scalar) - floating-point maximum (scalar) - compares the two source SIMD&FP registers, and writes the larger of the two floating-point values to the destination SIMD&FP register. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..1.....010010..........
M S     pe Rm     op  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

fmax (vector) - floating-point maximum (vector) - compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110010.....001101..........
 QU     1  Rm     ode Rn   Rd   
0.0011100.1.....111101..........
 QU     1z Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fmaxnm (scalar) - floating-point maximum number (scalar) - compares the first and second source SIMD&FP register values, and writes the larger of the two floating-point values to the destination SIMD&FP register. Regardless of the value of FPCR.AH, the behavior is as follows: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..1.....011010..........
M S     pe Rm     op  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

fmaxnm (vector) - floating-point maximum number (vector) - compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register. Regardless of the value of FPCR.AH, the behavior is as follows: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110010.....000001..........
 QU     a  Rm     ode Rn   Rd   
0.0011100.1.....110001..........
 QU     1z Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fmaxnmp (scalar) - floating-point maximum number of pair of elements (scalar) - compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register. Regardless of the value of FPCR.AH, the behavior is as follows for each pairwise operation: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111000110000110010..........
  U     1z     pcode  Rn   Rd   
011111100.110000110010..........
  U     1z     pcode  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <T>
 sz | <T>
 0 | 2S
 1 | 2D

fmaxnmp (vector) - floating-point maximum number pairwise (vector) - creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values. Regardless of the value of FPCR.AH, the behavior is as follows for each pairwise operation: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110010.....000001..........
 QU     a  Rm     ode Rn   Rd   
0.1011100.1.....110001..........
 QU     1z Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fmaxnmv - floating-point maximum number across vector - compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values. Regardless of the value of FPCR.AH, the behavior is as follows: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00111000110000110010..........
 QU     1      pcode  Rn   Rd   
0110111000110000110010..........
 QU     1z     pcode  Rn   Rd   
 <V>:destination width specifier, H.
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H

fmaxp (scalar) - floating-point maximum of pair of elements (scalar) - compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register. When FPCR.AH is 0, the behavior is as follows for each pairwise operation: When FPCR.AH is 1, the behavior is as follows for each pairwise operation: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111000110000111110..........
  U     1z     pcode  Rn   Rd   
011111100.110000111110..........
  U     1z     pcode  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <T>
 sz | <T>
 0 | 2S
 1 | 2D

fmaxp (vector) - floating-point maximum pairwise (vector) - creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values. When FPCR.AH is 0, the behavior is as follows for each pairwise operation: When FPCR.AH is 1, the behavior is as follows for each pairwise operation: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110010.....001101..........
 QU     1  Rm     ode Rn   Rd   
0.1011100.1.....111101..........
 QU     1z Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fmaxv - floating-point maximum across vector - compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00111000110000111110..........
 QU     1      pcode  Rn   Rd   
0110111000110000111110..........
 QU     1z     pcode  Rn   Rd   
 <V>:destination width specifier, H.
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H

fmin (scalar) - floating-point minimum (scalar) - compares the first and second source SIMD&FP register values, and writes the smaller of the two floating-point values to the destination SIMD&FP register. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..1.....010110..........
M S     pe Rm     op  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

fmin (vector) - floating-point minimum (vector) - compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110110.....001101..........
 QU     1  Rm     ode Rn   Rd   
0.0011101.1.....111101..........
 QU     1z Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fminnm (scalar) - floating-point minimum number (scalar) - compares the first and second source SIMD&FP register values, and writes the smaller of the two floating-point values to the destination SIMD&FP register. Regardless of the value of FPCR.AH, the behavior is as follows: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..1.....011110..........
M S     pe Rm     op  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

fminnm (vector) - floating-point minimum number (vector) - compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register. Regardless of the value of FPCR.AH, the behavior is as follows: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110110.....000001..........
 QU     a  Rm     ode Rn   Rd   
0.0011101.1.....110001..........
 QU     1z Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fminnmp (scalar) - floating-point minimum number of pair of elements (scalar) - compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register. Regardless of the value of FPCR.AH, the behavior is as follows for each pairwise operation: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111010110000110010..........
  U     1z     pcode  Rn   Rd   
011111101.110000110010..........
  U     1z     pcode  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <T>
 sz | <T>
 0 | 2S
 1 | 2D

fminnmp (vector) - floating-point minimum number pairwise (vector) - creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values. Regardless of the value of FPCR.AH, the behavior is as follows for each pairwise operation: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110110.....000001..........
 QU     a  Rm     ode Rn   Rd   
0.1011101.1.....110001..........
 QU     1z Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fminnmv - floating-point minimum number across vector - compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values. Regardless of the value of FPCR.AH, the behavior is as follows: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00111010110000110010..........
 QU     1      pcode  Rn   Rd   
0110111010110000110010..........
 QU     1z     pcode  Rn   Rd   
 <V>:destination width specifier, H.
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H

fminp (scalar) - floating-point minimum of pair of elements (scalar) - compares two vector elements in the source SIMD&FP register and writes the smallest of the floating-point values as a scalar to the destination SIMD&FP register. When FPCR.AH is 0, the behavior is as follows for each pairwise operation: When FPCR.AH is 1, the behavior is as follows for each pairwise operation: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111010110000111110..........
  U     1z     pcode  Rn   Rd   
011111101.110000111110..........
  U     1z     pcode  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <T>
 sz | <T>
 0 | 2S
 1 | 2D

fminp (vector) - floating-point minimum pairwise (vector) - creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values. When FPCR.AH is 0, the behavior is as follows for each pairwise operation: When FPCR.AH is 1, the behavior is as follows for each pairwise operation: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110110.....001101..........
 QU     1  Rm     ode Rn   Rd   
0.1011101.1.....111101..........
 QU     1z Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fminv - floating-point minimum across vector - compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows: can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00111010110000111110..........
 QU     1      pcode  Rn   Rd   
0110111010110000111110..........
 QU     1z     pcode  Rn   Rd   
 <V>:destination width specifier, H.
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H

fmla (by element) - floating-point fused multiply-add to accumulator (by element) - multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111100......0001.0..........
  U     zeLMRm   2  H Rn   Rd   
010111111.......0001.0..........
  U      zLMRm   2  H Rn   Rd   
0.00111100......0001.0..........
 QU     zeLMRm   2  H Rn   Rd   
0.0011111.......0001.0..........
 QU      zLMRm   2  H Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:For the "Scalar, half-precision" and "Vector, half-precision" variants: is the name of the second SIMD&FP source register, in the range V0 to V15, encoded in the "Rm" field.
 <Vm>:For the "Scalar, single-precision and double-precision" and "Vector, single-precision and double-precision" variants: is the name of the second SIMD&FP source register, encoded in the "M:Rm" fields.
 <index>:For the "Scalar, half-precision" and "Vector, half-precision" variants: is the element index, in the range 0 to 7, encoded in the "H:L:M" fields.
 <index>
 sz | L | <index>
 0 | x | UInt(H:L)
 1 | 0 | UInt(H)
 1 | 1 | RESERVED
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <Ts>
 sz | <Ts>
 0 | S
 1 | D
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 Q | sz | <T>
 0 | 0 | 2S
 0 | 1 | RESERVED
 1 | 0 | 4S
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.

fmla (vector) - floating-point fused multiply-add to accumulator (vector) - multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110010.....000011..........
 QU     a  Rm     ode Rn   Rd   
0.0011100.1.....110011..........
 QU     pz Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fmlal, fmlal2 (by element) - floating-point fused multiply-add long to accumulator (by element) - multiplies the half-precision vector elements in the first source SIMD&FP register by the specified half-precision value in the second source SIMD&FP register, and accumulates the intermediate product without rounding to the corresponding single-precision vector element of the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped. In Armv8.2 and Armv8.3, this is an OPTIONAL instruction. From Armv8.4, it is mandatory for all implementations to support it.
0.00111110......0000.0..........
 QU      zLMRm   S  H Rn   Rd   
0.10111110......1000.0..........
 QU      zLMRm   S  H Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 2S
 1 | 4S
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 2H
 1 | 4H
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.
 <index>:element index, encoded in the "H:L:M" fields.

fmlal, fmlal2 (vector) - floating-point fused multiply-add long to accumulator (vector) - multiplies corresponding half-precision floating-point values in the vectors in the two source SIMD&FP registers, and accumulates the intermediate product without rounding to the corresponding single-precision vector element of the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped. In Armv8.2 and Armv8.3, this is an OPTIONAL instruction. From Armv8.4, it is mandatory for all implementations to support it.
0.001110001.....111011..........
 QU     Sz Rm   pcode Rn   Rd   
0.101110001.....110011..........
 QU     Sz Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 2S
 1 | 4S
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 2H
 1 | 4H
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fmlalb, fmlalt (by element) - 8-bit floating-point multiply-add long to half-precision (vector, by element) - widens the even-numbered (bottom) or odd-numbered (top) 8-bit elements in the first source vector and the indexed element from the second source vector to half-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE[3:0]), before being destructively added without intermediate rounding to the half-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the first source vector. The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.
0.00111111......0000.0..........
 QU     zeLMRm  codeH Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, in the range V0 to V7, encoded in the "Rm<2:0>" field.
 <index>:element index, in the range 0 to 15, encoded in the "H:L:M:Rm<3>" fields.

fmlalb, fmlalt (vector) - 8-bit floating-point multiply-add long to half-precision (vector) - widens the even-numbered (bottom) or odd-numbered (top) 8-bit elements in the first and second source vectors to half-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE[3:0]), before being destructively added without intermediate rounding to the half-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the source vectors. The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.
0.001110110.....111111..........
 QU     ze Rm    code Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fmlallbb, fmlallbt, fmlalltb, fmlalltt (by element) - 8-bit floating-point multiply-add long-long to single-precision (vector, by element) - widens the first (bottom bottom), second (bottom top), third (top bottom), or fourth (top top) 8-bit element of each 32-bit container in the first source vector and the indexed element from the second source vector to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE), before being destructively added without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the first source vector. The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.
0.1011110x......1000.0..........
 QU     zeLMRm  codeH Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, in the range V0 to V7, encoded in the "Rm<2:0>" field.
 <index>:element index, in the range 0 to 15, encoded in the "H:L:M:Rm<3>" fields.

fmlallbb, fmlallbt, fmlalltb, fmlalltt (vector) - 8-bit floating-point multiply-add long-long to single-precision (vector) - widens the first (bottom bottom), second (bottom top), third (top bottom), or fourth (top top) 8-bit element of each 32-bit container in the first and second source vectors to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE), before being destructively added without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the source vectors. The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.
0.0011100x0.....110001..........
 QU     ze Rm    code Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fmls (by element) - floating-point fused multiply-subtract from accumulator (by element) - multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111100......0101.0..........
  U     zeLMRm   2  H Rn   Rd   
010111111.......0101.0..........
  U      zLMRm   2  H Rn   Rd   
0.00111100......0101.0..........
 QU     zeLMRm   2  H Rn   Rd   
0.0011111.......0101.0..........
 QU      zLMRm   2  H Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:For the "Scalar, half-precision" and "Vector, half-precision" variants: is the name of the second SIMD&FP source register, in the range V0 to V15, encoded in the "Rm" field.
 <Vm>:For the "Scalar, single-precision and double-precision" and "Vector, single-precision and double-precision" variants: is the name of the second SIMD&FP source register, encoded in the "M:Rm" fields.
 <index>:For the "Scalar, half-precision" and "Vector, half-precision" variants: is the element index, in the range 0 to 7, encoded in the "H:L:M" fields.
 <index>
 sz | L | <index>
 0 | x | UInt(H:L)
 1 | 0 | UInt(H)
 1 | 1 | RESERVED
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <Ts>
 sz | <Ts>
 0 | S
 1 | D
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 Q | sz | <T>
 0 | 0 | 2S
 0 | 1 | RESERVED
 1 | 0 | 4S
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.

fmls (vector) - floating-point fused multiply-subtract from accumulator (vector) - multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110110.....000011..........
 QU     a  Rm     ode Rn   Rd   
0.0011101.1.....110011..........
 QU     pz Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fmlsl, fmlsl2 (by element) - floating-point fused multiply-subtract long from accumulator (by element) - multiplies the negated half-precision vector elements in the first source SIMD&FP register by the specified half-precision value in the second source SIMD&FP register, and accumulates the intermediate product without rounding to the corresponding single-precision vector element of the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped. In Armv8.2 and Armv8.3, this is an OPTIONAL instruction. From Armv8.4, it is mandatory for all implementations to support it.
0.00111110......0100.0..........
 QU      zLMRm   S  H Rn   Rd   
0.10111110......1100.0..........
 QU      zLMRm   S  H Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 2S
 1 | 4S
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 2H
 1 | 4H
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.
 <index>:element index, encoded in the "H:L:M" fields.

fmlsl, fmlsl2 (vector) - floating-point fused multiply-subtract long from accumulator (vector) - negates the half-precision values in the vector of one SIMD&FP register, multiplies these with the corresponding half-precision values in another vector, and accumulates the intermediate product without rounding to the corresponding single-precision vector element of the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped. In Armv8.2 and Armv8.3, this is an OPTIONAL instruction. From Armv8.4, it is mandatory for all implementations to support it.
0.001110101.....111011..........
 QU     Sz Rm   pcode Rn   Rd   
0.101110101.....110011..........
 QU     Sz Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 2S
 1 | 4S
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 2H
 1 | 4H
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fmmla (8-bit floating-point to half-precision) - 8-bit floating-point matrix multiply-accumulate into 2x2 half-precision matrix - performs the fused sum-of-products within each four adjacent 8-bit elements while multiplying the 2×4 matrix of 8-bit floating-point values held in each 64-bit segment of the first source vector by the 4×2 matrix of 8-bit floating-point values in the corresponding segment of the second source vector. The half-precision sum-of-products are scaled by 2-UInt(FPMR.LSCALE[3:0]), before being destructively added without intermediate rounding to the 2x2 half-precision matrix in the destination vector. This is equivalent to accumulating 4-way dot product per destination element. The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.
01101110000.....111011..........
 QU     ze Rm    code Rn   Rd   
 <Vd>:name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fmmla (8-bit floating-point to single-precision) - 8-bit floating-point matrix multiply-accumulate into 2x2 single-precision matrix - performs the fused sum-of-products within each eight adjacent 8-bit elements while multiplying the 2×8 matrix of 8-bit floating-point values in the first source vector by the 8×2 matrix of 8-bit floating-point values in the second source vector. The single-precision sum-of-products are scaled by 2-UInt(FPMR.LSCALE), before being destructively added without intermediate rounding to the 2x2 single-precision matrix in the destination vector. This is equivalent to accumulating 8-way dot product per destination element. The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.
01101110100.....111011..........
 QU     ze Rm    code Rn   Rd   
 <Vd>:name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fmov (general) - floating-point move to or from general-purpose register without conversion - transfers the contents of a SIMD&FP register to a general-purpose register, or the contents of a general-purpose register to a SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..10x11x000000..........
f S     pe deode      Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fmov (register) - floating-point move register without conversion - copies the floating-point value in the SIMD&FP source register to the SIMD&FP destination register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..100000010000..........
M S     pe     pc     Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fmov (scalar, immediate) - floating-point move immediate (scalar) - copies a floating-point immediate constant into the SIMD&FP destination register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..1........10000000.....
M S     pe imm8       imm5 Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <imm>:Is a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision, encoded in the "imm8" field. For details of the range of constants available and the encoding of 
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

fmov (vector, immediate) - floating-point move immediate (vector) - copies an immediate floating-point constant into every element of the SIMD&FP destination register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00111100000...111111..........
 Qp          abcmode2 defghRd   
0..0111100000...111101..........
 Qp          abcmode2 defghRd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 Q | <T>
 0 | 2S
 1 | 4S
 <imm>:Is a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h". For details of the range of constants available and the encoding of 

fmsub - floating-point fused multiply-subtract (scalar) - multiplies the values of the first two SIMD&FP source registers, negates the product, adds that to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011111..0.....1...............
M S     pe1Rm   0Ra   Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field.
 <Ha>:16-bit name of the third SIMD&FP source register holding the minuend, encoded in the "Ra" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field.
 <Sa>:32-bit name of the third SIMD&FP source register holding the minuend, encoded in the "Ra" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field.
 <Da>:64-bit name of the third SIMD&FP source register holding the minuend, encoded in the "Ra" field.

fmul (by element) - floating-point multiply (by element) - multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111100......1001.0..........
  U     zeLMRm  codeH Rn   Rd   
010111111.......1001.0..........
  U      zLMRm  codeH Rn   Rd   
0.00111100......1001.0..........
 QU     zeLMRm  codeH Rn   Rd   
0.0011111.......1001.0..........
 QU      zLMRm  codeH Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:For the "Scalar, half-precision" and "Vector, half-precision" variants: is the name of the second SIMD&FP source register, in the range V0 to V15, encoded in the "Rm" field.
 <Vm>:For the "Scalar, single-precision and double-precision" and "Vector, single-precision and double-precision" variants: is the name of the second SIMD&FP source register, encoded in the "M:Rm" fields.
 <index>:For the "Scalar, half-precision" and "Vector, half-precision" variants: is the element index, in the range 0 to 7, encoded in the "H:L:M" fields.
 <index>
 sz | L | <index>
 0 | x | UInt(H:L)
 1 | 0 | UInt(H)
 1 | 1 | RESERVED
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <Ts>
 sz | <Ts>
 0 | S
 1 | D
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 Q | sz | <T>
 0 | 0 | 2S
 0 | 1 | RESERVED
 1 | 0 | 4S
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.

fmul (scalar) - floating-point multiply (scalar) - multiplies the floating-point values of the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..1.....000010..........
M S     pe Rm   p     Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

fmul (vector) - floating-point multiply (vector) - multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110010.....000111..........
 QU     a  Rm     ode Rn   Rd   
0.1011100.1.....110111..........
 QU      z Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fmulx - floating-point multiply extended - multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register. If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110010.....000111..........
  U     a  Rm     ode Rn   Rd   
010111100.1.....110111..........
  U      z Rm   pcode Rn   Rd   
0.001110010.....000111..........
 QU     a  Rm     ode Rn   Rd   
0.0011100.1.....110111..........
 QU      z Rm   pcode Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fmulx (by element) - floating-point multiply extended (by element) - multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111100......1001.0..........
  U     zeLMRm  codeH Rn   Rd   
011111111.......1001.0..........
  U      zLMRm  codeH Rn   Rd   
0.10111100......1001.0..........
 QU     zeLMRm  codeH Rn   Rd   
0.1011111.......1001.0..........
 QU      zLMRm  codeH Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:For the "Scalar, half-precision" and "Vector, half-precision" variants: is the name of the second SIMD&FP source register, in the range V0 to V15, encoded in the "Rm" field.
 <Vm>:For the "Scalar, single-precision and double-precision" and "Vector, single-precision and double-precision" variants: is the name of the second SIMD&FP source register, encoded in the "M:Rm" fields.
 <index>:For the "Scalar, half-precision" and "Vector, half-precision" variants: is the element index, in the range 0 to 7, encoded in the "H:L:M" fields.
 <index>
 sz | L | <index>
 0 | x | UInt(H:L)
 1 | 0 | UInt(H)
 1 | 1 | RESERVED
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <Ts>
 sz | <Ts>
 0 | S
 1 | D
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 Q | sz | <T>
 0 | 0 | 2S
 0 | 1 | RESERVED
 1 | 0 | 4S
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.

fneg (scalar) - floating-point negate (scalar) - negates the value in the SIMD&FP source register and writes the result to the SIMD&FP destination register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..100001010000..........
M S     pe     pc     Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fneg (vector) - floating-point negate (vector) - negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.10111011111000111110..........
 QU     a      pcode  Rn   Rd   
0.1011101.100000111110..........
 QU      z     pcode  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fnmadd - floating-point negated fused multiply-add (scalar) - multiplies the values of the first two SIMD&FP source registers, negates the product, subtracts the value of the third SIMD&FP source register, and writes the result to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011111..1.....0...............
M S     pe1Rm   0Ra   Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field.
 <Ha>:16-bit name of the third SIMD&FP source register holding the addend, encoded in the "Ra" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field.
 <Sa>:32-bit name of the third SIMD&FP source register holding the addend, encoded in the "Ra" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field.
 <Da>:64-bit name of the third SIMD&FP source register holding the addend, encoded in the "Ra" field.

fnmsub - floating-point negated fused multiply-subtract (scalar) - multiplies the values of the first two SIMD&FP source registers, subtracts the value of the third SIMD&FP source register, and writes the result to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011111..1.....1...............
M S     pe1Rm   0Ra   Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field.
 <Ha>:16-bit name of the third SIMD&FP source register holding the minuend, encoded in the "Ra" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field.
 <Sa>:32-bit name of the third SIMD&FP source register holding the minuend, encoded in the "Ra" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field.
 <Da>:64-bit name of the third SIMD&FP source register holding the minuend, encoded in the "Ra" field.

fnmul (scalar) - floating-point multiply-negate (scalar) - multiplies the floating-point values of the two source SIMD&FP registers, and writes the negation of the result to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..1.....100010..........
M S     pe Rm   p     Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

frecpe - floating-point reciprocal estimate - finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111011111001110110..........
  U     a      pcode  Rn   Rd   
010111101.100001110110..........
  U      z     pcode  Rn   Rd   
0.00111011111001110110..........
 QU     a      pcode  Rn   Rd   
0.0011101.100001110110..........
 QU      z     pcode  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

frecps - floating-point reciprocal step - multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110010.....001111..........
  U     a  Rm     ode Rn   Rd   
010111100.1.....111111..........
  U      z Rm   pcode Rn   Rd   
0.001110010.....001111..........
 QU     a  Rm     ode Rn   Rd   
0.0011100.1.....111111..........
 QU      z Rm   pcode Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

frecpx - floating-point reciprocal exponent (scalar) - finds an approximate reciprocal exponent for the source SIMD&FP register and writes the result to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111011111001111110..........
  U     a      pcode  Rn   Rd   
010111101.100001111110..........
  U      z     pcode  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.

frint32x (scalar) - floating-point round to 32-bit integer, using current rounding mode (scalar) - rounds a floating-point value in the SIMD&FP source register to an integral floating-point value that fits into a 32-bit integer size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register. A zero input returns a zero result with the same sign. When the result value is not numerically equal to the input value, an Inexact exception is raised. When the input is infinite, NaN or out-of-range, the instruction returns {for the corresponding result value} the most negative integer representable in the destination size, and an Invalid Operation floating-point exception is raised. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
000111100x101000110000..........
M S     pe     op     Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

frint32x (vector) - floating-point round to 32-bit integer, using current rounding mode (vector) - rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values that fit into a 32-bit integer size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register. A zero input returns a zero result with the same sign. When one of the result values is not numerically equal to the corresponding input value, an Inexact exception is raised. When an input is infinite, NaN or out-of-range, the instruction returns for the corresponding result value the most negative integer representable in the destination size, and an Invalid Operation floating-point exception is raised. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.1011100.100001111010..........
 QU      z         p  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

frint32z (scalar) - floating-point round to 32-bit integer toward zero (scalar) - rounds a floating-point value in the SIMD&FP source register to an integral floating-point value that fits into a 32-bit integer size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register. A zero input returns a zero result with the same sign. When the result value is not numerically equal to the {corresponding} input value, an Inexact exception is raised. When the input is infinite, NaN or out-of-range, the instruction returns {for the corresponding result value} the most negative integer representable in the destination size, and an Invalid Operation floating-point exception is raised. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
000111100x101000010000..........
M S     pe     op     Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

frint32z (vector) - floating-point round to 32-bit integer toward zero (vector) - rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values that fit into a 32-bit integer size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register. A zero input returns a zero result with the same sign. When one of the result values is not numerically equal to the corresponding input value, an Inexact exception is raised. When an input is infinite, NaN or out-of-range, the instruction returns for the corresponding result value the most negative integer representable in the destination size, and an Invalid Operation floating-point exception is raised. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.0011100.100001111010..........
 QU      z         p  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

frint64x (scalar) - floating-point round to 64-bit integer, using current rounding mode (scalar) - rounds a floating-point value in the SIMD&FP source register to an integral floating-point value that fits into a 64-bit integer size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register. A zero input returns a zero result with the same sign. When the result value is not numerically equal to the input value, an Inexact exception is raised. When the input is infinite, NaN or out-of-range, the instruction returns {for the corresponding result value} the most negative integer representable in the destination size, and an Invalid Operation floating-point exception is raised. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
000111100x101001110000..........
M S     pe     op     Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

frint64x (vector) - floating-point round to 64-bit integer, using current rounding mode (vector) - rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values that fit into a 64-bit integer size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register. A zero input returns a zero result with the same sign. When one of the result values is not numerically equal to the corresponding input value, an Inexact exception is raised. When an input is infinite, NaN or out-of-range, the instruction returns for the corresponding result value the most negative integer representable in the destination size, and an Invalid Operation floating-point exception is raised. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.1011100.100001111110..........
 QU      z         p  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

frint64z (scalar) - floating-point round to 64-bit integer toward zero (scalar) - rounds a floating-point value in the SIMD&FP source register to an integral floating-point value that fits into a 64-bit integer size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register. A zero input returns a zero result with the same sign. When the result value is not numerically equal to the {corresponding} input value, an Inexact exception is raised. When the input is infinite, NaN or out-of-range, the instruction returns {for the corresponding result value} the most negative integer representable in the destination size, and an Invalid Operation floating-point exception is raised. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
000111100x101001010000..........
M S     pe     op     Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

frint64z (vector) - floating-point round to 64-bit integer toward zero (vector) - rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values that fit into a 64-bit integer size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register. A zero input returns a zero result with the same sign. When one of the result values is not numerically equal to the corresponding input value, an Inexact exception is raised. When an input is infinite, NaN or out-of-range, the instruction returns for the corresponding result value the most negative integer representable in the destination size, and an Invalid Operation floating-point exception is raised. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.0011100.100001111110..........
 QU      z         p  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

frinta (scalar) - floating-point round to integral, to nearest with ties to away (scalar) - rounds a floating-point value in the SIMD&FP source register to an integral floating-point value of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..100110010000..........
M S     pe    ode     Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

frinta (vector) - floating-point round to integral, to nearest with ties to away (vector) - rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.10111001111001100010..........
 QU     2          1  Rn   Rd   
0.1011100.100001100010..........
 QU     2z         1  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

frinti (scalar) - floating-point round to integral, using current rounding mode (scalar) - rounds a floating-point value in the SIMD&FP source register to an integral floating-point value of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..100111110000..........
M S     pe    ode     Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

frinti (vector) - floating-point round to integral, using current rounding mode (vector) - rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.10111011111001100110..........
 QU     2          1  Rn   Rd   
0.1011101.100001100110..........
 QU     2z         1  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

frintm (scalar) - floating-point round to integral, toward minus infinity (scalar) - rounds a floating-point value in the SIMD&FP source register to an integral floating-point value of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..100101010000..........
M S     pe    ode     Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

frintm (vector) - floating-point round to integral, toward minus infinity (vector) - rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00111001111001100110..........
 QU     2          1  Rn   Rd   
0.0011100.100001100110..........
 QU     2z         1  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

frintn (scalar) - floating-point round to integral, to nearest with ties to even (scalar) - rounds a floating-point value in the SIMD&FP source register to an integral floating-point value of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..100100010000..........
M S     pe    ode     Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

frintn (vector) - floating-point round to integral, to nearest with ties to even (vector) - rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00111001111001100010..........
 QU     2          1  Rn   Rd   
0.0011100.100001100010..........
 QU     2z         1  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

frintp (scalar) - floating-point round to integral, toward plus infinity (scalar) - rounds a floating-point value in the SIMD&FP source register to an integral floating-point value of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..100100110000..........
M S     pe    ode     Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

frintp (vector) - floating-point round to integral, toward plus infinity (vector) - rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00111011111001100010..........
 QU     2          1  Rn   Rd   
0.0011101.100001100010..........
 QU     2z         1  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

frintx (scalar) - floating-point round to integral exact, using current rounding mode (scalar) - rounds a floating-point value in the SIMD&FP source register to an integral floating-point value of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register. When the result value is not numerically equal to the input value, an Inexact exception is raised. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..100111010000..........
M S     pe    ode     Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

frintx (vector) - floating-point round to integral exact, using current rounding mode (vector) - rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register. When a result value is not numerically equal to the corresponding input value, an Inexact exception is raised. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.10111001111001100110..........
 QU     2          1  Rn   Rd   
0.1011100.100001100110..........
 QU     2z         1  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

frintz (scalar) - floating-point round to integral, toward zero (scalar) - rounds a floating-point value in the SIMD&FP source register to an integral floating-point value of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..100101110000..........
M S     pe    ode     Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

frintz (vector) - floating-point round to integral, toward zero (vector) - rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00111011111001100110..........
 QU     2          1  Rn   Rd   
0.0011101.100001100110..........
 QU     2z         1  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

frsqrte - floating-point reciprocal square root estimate - calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111011111001110110..........
  U     a      pcode  Rn   Rd   
011111101.100001110110..........
  U      z     pcode  Rn   Rd   
0.10111011111001110110..........
 QU     a      pcode  Rn   Rd   
0.1011101.100001110110..........
 QU      z     pcode  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

frsqrts - floating-point reciprocal square root step - multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110110.....001111..........
  U     a  Rm     ode Rn   Rd   
010111101.1.....111111..........
  U      z Rm   pcode Rn   Rd   
0.001110110.....001111..........
 QU     a  Rm     ode Rn   Rd   
0.0011101.1.....111111..........
 QU      z Rm   pcode Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fscale - floating-point adjust exponent by vector - multiplies the floating-point elements of the first source vector by 2.0 to the power of the signed integer values in the corresponding elements of the second source vector, and places the results in the corresponding elements of the destination vector.
0.101110110.....001111..........
 QU     a  Rm     ode Rn   Rd   
0.1011101x1.....111111..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 size<0> | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

fsqrt (scalar) - floating-point square root (scalar) - calculates the square root of the value in the SIMD&FP source register and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..100001110000..........
M S     pe     pc     Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

fsqrt (vector) - floating-point square root (vector) - calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.10111011111001111110..........
 QU     a      pcode  Rn   Rd   
0.1011101.100001111110..........
 QU      z     pcode  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

fsub (scalar) - floating-point subtract (scalar) - subtracts the floating-point value of the second source SIMD&FP register from the floating-point value of the first source SIMD&FP register, and writes the result to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
00011110..1.....001110..........
M S     pe Rm      p  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Hm>:16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Sm>:32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Dm>:64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

fsub (vector) - floating-point subtract (vector) - subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110110.....000101..........
 QU     a  Rm     ode Rn   Rd   
0.0011101.1.....110101..........
 QU      z Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

ins (element) - insert vector element from another vector element - copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register. can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01101110000.....0....1..........
 Qp        imm5  imm4 Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ts>
 imm5 | <Ts>
 x0000 | RESERVED
 xxxx1 | B
 xxx10 | H
 xx100 | S
 x1000 | D
 <index1>
 imm5 | <index1>
 x0000 | RESERVED
 xxxx1 | UInt(imm5<4:1>)
 xxx10 | UInt(imm5<4:2>)
 xx100 | UInt(imm5<4:3>)
 x1000 | UInt(imm5<4>)
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <index2>
 imm5 | <index2>
 x0000 | RESERVED
 xxxx1 | UInt(imm4)
 xxx10 | UInt(imm4<3:1>)
 xx100 | UInt(imm4<3:2>)
 x1000 | UInt(imm4<3>)
 Unspecified bits in "imm4" are ignored but should be set to zero by an assembler.

ins (general) - insert vector element from general-purpose register - copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register. can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01001110000.....000111..........
 Qp        imm5  imm4 Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ts>
 imm5 | <Ts>
 x0000 | RESERVED
 xxxx1 | B
 xxx10 | H
 xx100 | S
 x1000 | D
 <index>
 imm5 | <index>
 x0000 | RESERVED
 xxxx1 | UInt(imm5<4:1>)
 xxx10 | UInt(imm5<4:2>)
 xx100 | UInt(imm5<4:3>)
 x1000 | UInt(imm5<4>)
 <R>
 imm5 | <R>
 x0000 | RESERVED
 xxxx1 | W
 xxx10 | W
 xx100 | W
 x1000 | X
 <n>:number [0-30] of the general-purpose source register or ZR (31), encoded in the "Rn" field.

ld1 (multiple structures) - load multiple single-element structures to one, two, three, or four registers - loads multiple single-element structures from memory and writes the result to one, two, three, or four SIMD&FP registers. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00110001000000xx1x............
 Q       L      codezeRn   Rt   
0.001100110.....xx1x............
 Q       L Rm   codezeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | 1D
 11 | 1 | 2D
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <Vt3>:name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32.
 <Vt4>:name of the fourth SIMD&FP register to be transferred, encoded as "Rt" plus 3 modulo 32.
 <imm>
 Q | <imm>
 0 | #8
 1 | #16
 <imm>
 Q | <imm>
 0 | #16
 1 | #32
 <imm>
 Q | <imm>
 0 | #24
 1 | #48
 <imm>
 Q | <imm>
 0 | #32
 1 | #64
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

ld1 (single structure) - load one single-element structure to one lane of one register - loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00110101000000xx0.............
 Q       LR    2odeSzeRn   Rt   
0.001101110.....xx0.............
 Q       LRRm   odeSzeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <index>:For the "8-bit", "8-bit, immediate offset", and "8-bit, register offset" variants: is the element index, encoded in "Q:S:size".
 <index>:For the "16-bit", "16-bit, immediate offset", and "16-bit, register offset" variants: is the element index, encoded in "Q:S:size<1>".
 <index>:For the "32-bit", "32-bit, immediate offset", and "32-bit, register offset" variants: is the element index, encoded in "Q:S".
 <index>:For the "64-bit", "64-bit, immediate offset", and "64-bit, register offset" variants: is the element index, encoded in "Q".
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

ld1r - load one single-element structure and replicate to all lanes (of one register) - loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001101010000001100............
 Q       LR    2odeSzeRn   Rt   
0.001101110.....1100............
 Q       LRRm   odeSzeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | 1D
 11 | 1 | 2D
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>
 size | <imm>
 00 | #1
 01 | #2
 10 | #4
 11 | #8
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

ld2 (multiple structures) - load multiple 2-element structures to two registers - loads multiple 2-element structures from memory and writes the result to the two SIMD&FP registers, with de-interleaving. For an example of de-interleaving, see LD3 (multiple structures). Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001100010000001000............
 Q       L      codezeRn   Rt   
0.001100110.....1000............
 Q       L Rm   codezeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>
 Q | <imm>
 0 | #16
 1 | #32
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

ld2 (single structure) - load single 2-element structure to one lane of two registers - loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00110101100000xx0.............
 Q       LR    2odeSzeRn   Rt   
0.001101111.....xx0.............
 Q       LRRm   odeSzeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <index>:For the "8-bit", "8-bit, immediate offset", and "8-bit, register offset" variants: is the element index, encoded in "Q:S:size".
 <index>:For the "16-bit", "16-bit, immediate offset", and "16-bit, register offset" variants: is the element index, encoded in "Q:S:size<1>".
 <index>:For the "32-bit", "32-bit, immediate offset", and "32-bit, register offset" variants: is the element index, encoded in "Q:S".
 <index>:For the "64-bit", "64-bit, immediate offset", and "64-bit, register offset" variants: is the element index, encoded in "Q".
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

ld2r - load single 2-element structure and replicate to all lanes of two registers - loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001101011000001100............
 Q       LR    2odeSzeRn   Rt   
0.001101111.....1100............
 Q       LRRm   odeSzeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | 1D
 11 | 1 | 2D
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>
 size | <imm>
 00 | #2
 01 | #4
 10 | #8
 11 | #16
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

ld3 (multiple structures) - load multiple 3-element structures to three registers - loads multiple 3-element structures from memory and writes the result to the three SIMD&FP registers, with de-interleaving.  Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001100010000000100............
 Q       L      codezeRn   Rt   
0.001100110.....0100............
 Q       L Rm   codezeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <Vt3>:name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>
 Q | <imm>
 0 | #24
 1 | #48
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

ld3 (single structure) - load single 3-element structure to one lane of three registers - loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00110101000000xx1.............
 Q       LR    2odeSzeRn   Rt   
0.001101110.....xx1.............
 Q       LRRm   odeSzeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <Vt3>:name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32.
 <index>:For the "8-bit", "8-bit, immediate offset", and "8-bit, register offset" variants: is the element index, encoded in "Q:S:size".
 <index>:For the "16-bit", "16-bit, immediate offset", and "16-bit, register offset" variants: is the element index, encoded in "Q:S:size<1>".
 <index>:For the "32-bit", "32-bit, immediate offset", and "32-bit, register offset" variants: is the element index, encoded in "Q:S".
 <index>:For the "64-bit", "64-bit, immediate offset", and "64-bit, register offset" variants: is the element index, encoded in "Q".
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

ld3r - load single 3-element structure and replicate to all lanes of three registers - loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001101010000001110............
 Q       LR    2odeSzeRn   Rt   
0.001101110.....1110............
 Q       LRRm   odeSzeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | 1D
 11 | 1 | 2D
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <Vt3>:name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>
 size | <imm>
 00 | #3
 01 | #6
 10 | #12
 11 | #24
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

ld4 (multiple structures) - load multiple 4-element structures to four registers - loads multiple 4-element structures from memory and writes the result to the four SIMD&FP registers, with de-interleaving. For an example of de-interleaving, see LD3 (multiple structures). Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001100010000000000............
 Q       L      codezeRn   Rt   
0.001100110.....0000............
 Q       L Rm   codezeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <Vt3>:name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32.
 <Vt4>:name of the fourth SIMD&FP register to be transferred, encoded as "Rt" plus 3 modulo 32.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>
 Q | <imm>
 0 | #32
 1 | #64
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

ld4 (single structure) - load single 4-element structure to one lane of four registers - loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00110101100000xx1.............
 Q       LR    2odeSzeRn   Rt   
0.001101111.....xx1.............
 Q       LRRm   odeSzeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <Vt3>:name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32.
 <Vt4>:name of the fourth SIMD&FP register to be transferred, encoded as "Rt" plus 3 modulo 32.
 <index>:For the "8-bit", "8-bit, immediate offset", and "8-bit, register offset" variants: is the element index, encoded in "Q:S:size".
 <index>:For the "16-bit", "16-bit, immediate offset", and "16-bit, register offset" variants: is the element index, encoded in "Q:S:size<1>".
 <index>:For the "32-bit", "32-bit, immediate offset", and "32-bit, register offset" variants: is the element index, encoded in "Q:S".
 <index>:For the "64-bit", "64-bit, immediate offset", and "64-bit, register offset" variants: is the element index, encoded in "Q".
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

ld4r - load single 4-element structure and replicate to all lanes of four registers - loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001101011000001110............
 Q       LR    2odeSzeRn   Rt   
0.001101111.....1110............
 Q       LRRm   odeSzeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | 1D
 11 | 1 | 2D
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <Vt3>:name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32.
 <Vt4>:name of the fourth SIMD&FP register to be transferred, encoded as "Rt" plus 3 modulo 32.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>
 size | <imm>
 00 | #4
 01 | #8
 10 | #16
 11 | #32
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

ldap1 (simd&fp) - load-acquire rcpc one single-element structure to one lane of one register - loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register. The instruction has memory ordering semantics, as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: This difference in memory ordering is not described in the pseudocode. For information about addressing modes, see Load/Store addressing modes. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00110101000001100001..........
 Q       LR    2odeSzeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <index>:element index, encoded in "Q".
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldapur (simd&fp) - load-acquire rcpc simd&fp register (unscaled offset) - loads a SIMD&FP register from memory. The address that is used for the load is calculated from a base register value and an optional immediate offset. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: This difference in memory ordering is not described in the pseudocode. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
..011101x10.........10..........
ze      pc imm9       Rn   Rt   
 <Bt>:8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Ht>:16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <St>:32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Dt>:64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt>:128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

ldbfadd, ldbfadda, ldbfaddal, ldbfaddl - bfloat16 floating-point add in memory - atomically loads a 16-bit value from memory, adds it to the BFloat16 value held in a register, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
00111100..1.....000000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Ht>:16-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldbfmax, ldbfmaxa, ldbfmaxal, ldbfmaxl - bfloat16 floating-point atomic maximum in memory - atomically loads a 16-bit value from memory, computes the BFloat16 maximum with the value held in a register, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
00111100..1.....010000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Ht>:16-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldbfmaxnm, ldbfmaxnma, ldbfmaxnmal, ldbfmaxnml - bfloat16 floating-point atomic maximum number in memory - atomically loads a 16-bit value from memory, computes the BFloat16 maximum number with the value held in a register, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
00111100..1.....011000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Ht>:16-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldbfmin, ldbfmina, ldbfminal, ldbfminl - bfloat16 floating-point atomic minimum in memory - atomically loads a 16-bit value from memory, computes the BFloat16 minimum with the value held in a register, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
00111100..1.....010100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Ht>:16-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldbfminnm, ldbfminnma, ldbfminnmal, ldbfminnml - bfloat16 floating-point atomic minimum number in memory - atomically loads a 16-bit value from memory, computes the BFloat16 minimum number with the value held in a register, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
00111100..1.....011100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Ht>:16-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

ldfadd, ldfadda, ldfaddal, ldfaddl - floating-point atomic add in memory - atomically loads a 16-bit, 32-bit, or 64-bit value from memory, performs a floating-point add with the value held in a register, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
..111100..1.....000000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Ht>:16-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Ss>:32-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <St>:32-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Ds>:64-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Dt>:64-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.

ldfmax, ldfmaxa, ldfmaxal, ldfmaxl - floating-point atomic maximum in memory - atomically loads a 16-bit, 32-bit, or 64-bit value from memory, computes the floating-point maximum with the value held in a register, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
..111100..1.....010000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Ht>:16-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Ss>:32-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <St>:32-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Ds>:64-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Dt>:64-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.

ldfmaxnm, ldfmaxnma, ldfmaxnmal, ldfmaxnml - floating-point atomic maximum number in memory - atomically loads a 16-bit, 32-bit, or 64-bit value from memory, computes the floating-point maximum number with the value held in a register, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
..111100..1.....011000..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Ht>:16-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Ss>:32-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <St>:32-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Ds>:64-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Dt>:64-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.

ldfmin, ldfmina, ldfminal, ldfminl - floating-point atomic minimum in memory - atomically loads a 16-bit, 32-bit, or 64-bit value from memory, computes the floating-point minimum with the value held in a register, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
..111100..1.....010100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Ht>:16-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Ss>:32-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <St>:32-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Ds>:64-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Dt>:64-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.

ldfminnm, ldfminnma, ldfminnmal, ldfminnml - floating-point atomic minimum number in memory - atomically loads a 16-bit, 32-bit, or 64-bit value from memory, computes the floating-point minimum number with the value held in a register, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
..111100..1.....011100..........
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Ht>:16-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Ss>:32-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <St>:32-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Ds>:64-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Dt>:64-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.

ldnp (simd&fp) - load pair of simd&fp registers, with non-temporal hint - loads a pair of SIMD&FP registers from memory, issuing a hint to the memory system that the access is non-temporal. The address that is used for the load is calculated from a base register value and an optional immediate offset. For information about non-temporal pair instructions, see Load/Store SIMD and Floating-point non-temporal pair. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
..10110001......................
pc   R   Limm7   Rt2  Rn   Rt   
 <St1>:32-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <St2>:32-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "32-bit" variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.
 <imm>:For the "64-bit" variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.
 <imm>:For the "128-bit" variant: is the optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as <imm>/16.
 <Dt1>:64-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Dt2>:64-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.
 <Qt1>:128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt2>:128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.

ldp (simd&fp) - load pair of simd&fp registers - loads a pair of SIMD&FP registers from memory. The address that is used for the load is calculated from a base register value and an optional immediate offset. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
..10110011......................
pc   R   Limm7   Rt2  Rn   Rt   
..10110111......................
pc   R   Limm7   Rt2  Rn   Rt   
..10110101......................
pc   R   Limm7   Rt2  Rn   Rt   
 <St1>:32-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <St2>:32-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "32-bit Post-index" and "32-bit Pre-index" variants: is the signed immediate byte offset, a multiple of 4 in the range -256 to 252, encoded in the "imm7" field as <imm>/4.
 <imm>:For the "64-bit Post-index" and "64-bit Pre-index" variants: is the signed immediate byte offset, a multiple of 8 in the range -512 to 504, encoded in the "imm7" field as <imm>/8.
 <imm>:For the "128-bit Post-index" and "128-bit Pre-index" variants: is the signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, encoded in the "imm7" field as <imm>/16.
 <imm>:For the "32-bit Signed offset" variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.
 <imm>:For the "64-bit Signed offset" variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.
 <imm>:For the "128-bit Signed offset" variant: is the optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as <imm>/16.
 <Dt1>:64-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Dt2>:64-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.
 <Qt1>:128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt2>:128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.

ldr (immediate, simd&fp) - load simd&fp register (immediate offset) - loads an element from memory, and writes the result as a scalar to the SIMD&FP register. The address that is used for the load is calculated from a base register value, a signed immediate offset, and an optional offset that is a multiple of the element size. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
..111100x10.........01..........
ze   R  pc imm9       Rn   Rt   
..111100x10.........11..........
ze   R  pc imm9       Rn   Rt   
..111101x1......................
ze   R  pcimm12       Rn   Rt   
 <Bt>:8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.
 <Ht>:16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <St>:32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Dt>:64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt>:128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <pimm>:For the "8-bit" variant: is the optional positive immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
 <pimm>:For the "16-bit" variant: is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0 and encoded in the "imm12" field as <pimm>/2.
 <pimm>:For the "32-bit" variant: is the optional positive immediate byte offset, a multiple of 4 in the range 0 to 16380, defaulting to 0 and encoded in the "imm12" field as <pimm>/4.
 <pimm>:For the "64-bit" variant: is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as <pimm>/8.
 <pimm>:For the "128-bit" variant: is the optional positive immediate byte offset, a multiple of 16 in the range 0 to 65520, defaulting to 0 and encoded in the "imm12" field as <pimm>/16.

ldr (literal, simd&fp) - load simd&fp register (pc-relative literal) - loads a SIMD&FP register from memory. The address that is used for the load is calculated from the PC value and an immediate offset. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
..011100........................
pc   R  imm19              Rt   
 <St>:32-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <label>:program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.
 <Dt>:64-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
 <Qt>:128-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.

ldr (register, simd&fp) - load simd&fp register (register offset) - loads a SIMD&FP register from memory. The address that is used for the load is calculated from a base register value and an offset register value. The offset can be optionally shifted and extended. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
..111100x11.........10..........
ze   R  pc Rm   ionS  Rn   Rt   
 <Bt>:8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Wm>:When 
 <Xm>:When 
 <extend>
 option | <extend>
 010 | UXTW
 110 | SXTW
 111 | SXTX
 <extend>
 option | <extend>
 010 | UXTW
 011 | LSL
 110 | SXTW
 111 | SXTX
 <amount>:For the "8-bit" variant: is the index shift amount, it must be 
 <amount>
 S | <amount>
 0 | #0
 1 | #1
 <amount>
 S | <amount>
 0 | #0
 1 | #2
 <amount>
 S | <amount>
 0 | #0
 1 | #3
 <amount>
 S | <amount>
 0 | #0
 1 | #4
 <Ht>:16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <St>:32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Dt>:64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt>:128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

ldtnp (simd&fp) - load unprivileged pair of simd&fp registers, with non-temporal hint - loads a pair of SIMD&FP registers from memory, issuing a hint to the memory system that the access is non-temporal. The address that is used for the load is calculated from a base register value and an optional immediate offset. For information about non-temporal pair instructions, see Load/Store SIMD and Floating-point non-temporal pair. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
1110110001......................
pc   R   Limm7   Rt2  Rn   Rt   
 <Qt1>:128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt2>:128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as <imm>/16.

ldtp (simd&fp) - load unprivileged pair of simd&fp registers - loads a pair of SIMD&FP registers from memory. The address that is used for the load is calculated from a base register value and an optional immediate offset. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
1110110011......................
pc   R   Limm7   Rt2  Rn   Rt   
1110110111......................
pc   R   Limm7   Rt2  Rn   Rt   
1110110101......................
pc   R   Limm7   Rt2  Rn   Rt   
 <Qt1>:128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt2>:128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Post-index" and "Pre-index" variants: is the signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, encoded in the "imm7" field as <imm>/16.
 <imm>:For the "Signed offset" variant: is the optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as <imm>/16.

ldur (simd&fp) - load simd&fp register (unscaled offset) - loads a SIMD&FP register from memory. The address that is used for the load is calculated from a base register value and an optional immediate offset. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
..111100x10.........00..........
ze   R  pc imm9       Rn   Rt   
 <Bt>:8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Ht>:16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <St>:32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Dt>:64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt>:128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

luti2 - lookup table read with 2-bit indices - copies indexed 8-bit or 16-bit elements from the table vector to the destination vector using packed 2-bit indices from a segment of the source vector. A segment corresponds to a portion of the source vector that is consumed in order to fill the destination vector. The segment is selected by the vector segment index.
010011101x0.....0...00..........
 Q      p2 Rm    enp  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP table register, encoded in the "Rn" field.
 <Vm>:name of the SIMD&FP source register, encoded in the "Rm" field.
 <index>:For the "Byte" variant: is the vector segment index, in the range 0 to 3, encoded in the "len" field.
 <index>:For the "Halfword" variant: is the vector segment index, in the range 0 to 7, encoded in the "len:op" fields.

luti4 - lookup table read with 4-bit indices - copies indexed 8-bit or 16-bit elements from the one or two table vectors to the destination vector using packed 4-bit indices from a segment of the source vector. A segment corresponds to a portion of the source vector that is consumed in order to fill the destination vector. The segment is selected by the vector segment index.
01001110010.....0...00..........
 Q      p2 Rm    enp  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP table register, encoded in the "Rn" field.
 <Vm>:name of the SIMD&FP source register, encoded in the "Rm" field.
 <index>:For the "Byte" variant: is the vector segment index, in the range 0 to 1, encoded in the "len<1>" field.
 <index>:For the "Halfword" variant: is the vector segment index, in the range 0 to 3, encoded in the "len" field.
 <Vn1>:name of the first SIMD&FP table register, encoded in the "Rn" field.
 <Vn2>:name of the second SIMD&FP table register, encoded as "Rn" plus 1 modulo 32.

mla (by element) - multiply-add to accumulator (vector, by element) - multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101111........0000.0..........
 QU     zeLMRm   2  H Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED

mla (vector) - multiply-add to accumulator (vector) - multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....100101..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

mls (by element) - multiply-subtract from accumulator (vector, by element) - multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101111........0100.0..........
 QU     zeLMRm   2  H Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED

mls (vector) - multiply-subtract from accumulator (vector) - multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....100101..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

mov (element) - move vector element to another vector element - copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register. can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01101110000.....0....1..........
 Qp        imm5  imm4 Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ts>
 imm5 | <Ts>
 x0000 | RESERVED
 xxxx1 | B
 xxx10 | H
 xx100 | S
 x1000 | D
 <index1>
 imm5 | <index1>
 x0000 | RESERVED
 xxxx1 | UInt(imm5<4:1>)
 xxx10 | UInt(imm5<4:2>)
 xx100 | UInt(imm5<4:3>)
 x1000 | UInt(imm5<4>)
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <index2>
 imm5 | <index2>
 x0000 | RESERVED
 xxxx1 | UInt(imm4)
 xxx10 | UInt(imm4<3:1>)
 xx100 | UInt(imm4<3:2>)
 x1000 | UInt(imm4<3>)
 Unspecified bits in "imm4" are ignored but should be set to zero by an assembler.

mov (from general) - move general-purpose register to a vector element - copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register. can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01001110000.....000111..........
 Qp        imm5  imm4 Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ts>
 imm5 | <Ts>
 x0000 | RESERVED
 xxxx1 | B
 xxx10 | H
 xx100 | S
 x1000 | D
 <index>
 imm5 | <index>
 x0000 | RESERVED
 xxxx1 | UInt(imm5<4:1>)
 xxx10 | UInt(imm5<4:2>)
 xx100 | UInt(imm5<4:3>)
 x1000 | UInt(imm5<4>)
 <R>
 imm5 | <R>
 x0000 | RESERVED
 xxxx1 | W
 xxx10 | W
 xx100 | W
 x1000 | X
 <n>:number [0-30] of the general-purpose source register or ZR (31), encoded in the "Rn" field.

mov (scalar) - move vector element to scalar - duplicates the specified vector element in the SIMD&FP source register into a scalar, and writes the result to the SIMD&FP destination register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110000.....000001..........
  p        imm5  imm4 Rn   Rd   
 <V>
 imm5 | <V>
 x0000 | RESERVED
 xxxx1 | B
 xxx10 | H
 xx100 | S
 x1000 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <T>
 imm5 | <T>
 x0000 | RESERVED
 xxxx1 | B
 xxx10 | H
 xx100 | S
 x1000 | D
 <index>
 imm5 | <index>
 x0000 | RESERVED
 xxxx1 | UInt(imm5<4:1>)
 xxx10 | UInt(imm5<4:2>)
 xx100 | UInt(imm5<4:3>)
 x1000 | UInt(imm5<4>)

mov (to general) - move vector element to general-purpose register - reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110000xxx00001111..........
 Qp        imm5  imm4 Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <index>:For the "32-bit" variant: is the element index encoded in "imm5<4:3>".
 <index>:For the "64-bit" variant: is the element index encoded in "imm5<4>".
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.

mov (vector) - move vector - copies the vector in the source SIMD&FP register into the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110101.....000111..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 8B
 1 | 16B
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

movi - move immediate (vector) - places an immediate constant into every vector element of the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0..0111100000.......01..........
 Qp          abcmode2 defghRd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 8B
 1 | 16B
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 Q | <T>
 0 | 2S
 1 | 4S
 <imm8>:Is an 8-bit immediate encoded in "a:b:c:d:e:f:g:h".
 <amount>
 cmode<1> | <amount>
 0 | 0
 1 | 8
 defaulting to 0 if LSL is omitted.
 <amount>
 cmode<2:1> | <amount>
 00 | 0
 01 | 8
 10 | 16
 11 | 24
 defaulting to 0 if LSL is omitted.
 <amount>
 cmode<0> | <amount>
 0 | 8
 1 | 16
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <imm>:Is a 64-bit immediate 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh', encoded in "a:b:c:d:e:f:g:h".

mul (by element) - multiply (vector, by element) - multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001111........1000.0..........
 QU     zeLMRm  codeH Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED

mul (vector) - multiply (vector) - multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....100111..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

mvn - bitwise not (vector) - reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.10111000100000010110..........
 QU     ze     pcode  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 8B
 1 | 16B
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

mvni - move inverted immediate (vector) - places the inverse of an immediate constant into every vector element of the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.10111100000.......01..........
 Qp          abcmode2 defghRd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 Q | <T>
 0 | 2S
 1 | 4S
 <imm8>:Is an 8-bit immediate encoded in "a:b:c:d:e:f:g:h".
 <amount>
 cmode<1> | <amount>
 0 | 0
 1 | 8
 defaulting to 0 if LSL is omitted.
 <amount>
 cmode<2:1> | <amount>
 00 | 0
 01 | 8
 10 | 16
 11 | 24
 defaulting to 0 if LSL is omitted.
 <amount>
 cmode<0> | <amount>
 0 | 8
 1 | 16

neg (vector) - negate (vector) - reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111011100000101110..........
  U     ze     pcode  Rn   Rd   
0.101110..100000101110..........
 QU     ze     pcode  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

not - bitwise not (vector) - reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.10111000100000010110..........
 QU     ze     pcode  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 8B
 1 | 16B
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

orn (vector) - bitwise inclusive or not (vector) - performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110111.....000111..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 8B
 1 | 16B
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

orr (vector, immediate) - bitwise inclusive or (vector, immediate) - reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00111100000...xxx101..........
 Qp          abcmode2 defghRd   
 <Vd>:name of the SIMD&FP register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 Q | <T>
 0 | 2S
 1 | 4S
 <imm8>:Is an 8-bit immediate encoded in "a:b:c:d:e:f:g:h".
 <amount>
 cmode<1> | <amount>
 0 | 0
 1 | 8
 defaulting to 0 if LSL is omitted.
 <amount>
 cmode<2:1> | <amount>
 00 | 0
 01 | 8
 10 | 16
 11 | 24
 defaulting to 0 if LSL is omitted.

orr (vector, register) - bitwise inclusive or (vector, register) - performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110101.....000111..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 8B
 1 | 16B
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

pmul - polynomial multiply - multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register. For information about multiplying polynomials see Polynomial arithmetic over {0, 1}. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....100111..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | x | RESERVED
 1x | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

pmull, pmull2 - polynomial multiply long - multiplies corresponding elements in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. For information about multiplying polynomials, see Polynomial arithmetic over {0, 1}. The PMULL instruction extracts each source vector from the lower half of each source register. The PMULL2 instruction extracts each source vector from the upper half of each source register. The PMULL and PMULL2 variants that operate on 64-bit source elements are defined only when FEAT_PMULL is implemented. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....111000..........
 QU     ze Rm   code  Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | RESERVED
 10 | RESERVED
 11 | 1Q
 The '1Q' arrangement is only allocated in an implementation that includes the Cryptographic Extension, and is otherwise RESERVED.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | x | RESERVED
 10 | x | RESERVED
 11 | 0 | 1D
 11 | 1 | 2D
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

raddhn, raddhn2 - rounding add returning high narrow - adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The results are rounded. For truncated results, see ADDHN. The RADDHN instruction writes the vector to the lower half of the destination register and clears the upper half. The RADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....010000..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

rax1 - rotate and exclusive-or - rotates each 64-bit element of the 128-bit vector in a source SIMD&FP register left by 1, performs a bitwise exclusive-OR of the resulting 128-bit vector and the vector in another source SIMD&FP register, and writes the result to the destination SIMD&FP register.
11001110011.....100011..........
           Rm    O  deRn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

rbit (vector) - reverse bit order (vector) - reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.10111001100000010110..........
 QU     ze     pcode  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 8B
 1 | 16B
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

rev16 (vector) - reverse elements in 16-bit halfwords (vector) - reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..100000000110..........
 QU     ze         0  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | x | RESERVED
 1x | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

rev32 (vector) - reverse elements in 32-bit words (vector) - reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..100000000010..........
 QU     ze         0  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 1x | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

rev64 - reverse elements in 64-bit doublewords (vector) - reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..100000000010..........
 QU     ze         0  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

rshrn, rshrn2 - rounding shift right narrow (immediate) - reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN. The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half. The RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.0011110!= 0000!= 0000!= 0000!= 0000...100011..........
 QU      immhmmb    p Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 immh | Q | <Tb>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 immh | <Ta>
 0001 | 8H
 001x | 4S
 01xx | 2D
 1xxx | RESERVED
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | RESERVED

rsubhn, rsubhn2 - rounding subtract returning high narrow - subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The results are rounded. For truncated results, see SUBHN. The RSUBHN instruction writes the vector to the lower half of the destination register and clears the upper half. The RSUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....011000..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

saba - signed absolute difference and accumulate - subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....011111..........
 QU     ze Rm       c Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sabal, sabal2 - signed absolute difference and accumulate long - subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. The SABAL instruction extracts each source vector from the lower half of each source register. The SABAL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....010100..........
 QU     ze Rm     p   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sabd - signed absolute difference - subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....011101..........
 QU     ze Rm       c Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sabdl, sabdl2 - signed absolute difference long - subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. The SABDL instruction extracts each source vector from the lower half of each source register. The SABDL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....011100..........
 QU     ze Rm     p   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sadalp - signed add and accumulate long pairwise - adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..100000011010..........
 QU     ze       p    Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | Q | <Ta>
 00 | 0 | 4H
 00 | 1 | 8H
 01 | 0 | 2S
 01 | 1 | 4S
 10 | 0 | 1D
 10 | 1 | 2D
 11 | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED

saddl, saddl2 - signed add long (vector) - adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.  The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values. The SADDL instruction extracts each source vector from the lower half of each source register. The SADDL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....000000..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

saddlp - signed add long pairwise - adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..100000001010..........
 QU     ze       p    Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | Q | <Ta>
 00 | 0 | 4H
 00 | 1 | 8H
 01 | 0 | 2S
 01 | 1 | 4S
 10 | 0 | 1D
 10 | 1 | 2D
 11 | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED

saddlv - signed add long across vector - adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..110000001110..........
 QU     ze     pcode  Rn   Rd   
 <V>
 size | <V>
 00 | H
 01 | S
 10 | D
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | RESERVED
 10 | 1 | 4S
 11 | x | RESERVED

saddw, saddw2 - signed add wide - adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register. The SADDW instruction extracts the second source vector from the lower half of the second source register. The SADDW2 instruction extracts the second source vector from the upper half of the second source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....000100..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED

scvtf (scalar simd&fp) - signed integer convert to floating-point (scalar simd&fp) - converts the signed integer value in the SIMD&FP source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..111100000000..........
f S     pe deode      Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

scvtf (scalar, fixed-point) - signed fixed-point convert to floating-point (scalar) - converts the signed value in the 32-bit or 64-bit general-purpose source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..000010................
f S     pe deodescale Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <fbits>:For the "32-bit to double-precision", "32-bit to half-precision", and "32-bit to single-precision" variants: is the number of bits after the binary point in the fixed-point source, in the range 1 to 32, encoded as 64 minus "scale".
 <fbits>:For the "64-bit to double-precision", "64-bit to half-precision", and "64-bit to single-precision" variants: is the number of bits after the binary point in the fixed-point source, in the range 1 to 64, encoded as 64 minus "scale".
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

scvtf (scalar, integer) - signed integer convert to floating-point (scalar) - converts the signed integer value in the general-purpose source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..100010000000..........
f S     pe deode      Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

scvtf (vector, fixed-point) - signed fixed-point convert to floating-point (vector) - converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
010111110!= 0000!= 0000!= 0000!= 0000...111001..........
  U      immhmmbpcode Rn   Rd   
0.0011110!= 0000!= 0000!= 0000!= 0000...111001..........
 QU      immhmmbpcode Rn   Rd   
 <V>
 immh | <V>
 0001 | RESERVED
 001x | H
 01xx | S
 1xxx | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <fbits>
 immh | <fbits>
 0001 | RESERVED
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <fbits>
 immh | <fbits>
 0001 | RESERVED
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | x | RESERVED
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

scvtf (vector, integer) - signed integer convert to floating-point (vector) - converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111001111001110110..........
  U     a      pcode  Rn   Rd   
010111100.100001110110..........
  U      z     pcode  Rn   Rd   
0.00111001111001110110..........
 QU     a      pcode  Rn   Rd   
0.0011100.100001110110..........
 QU      z     pcode  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

sdot (by element) - dot product signed arithmetic (vector, by element) - performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped. In Armv8.2 and Armv8.3, this is an OPTIONAL instruction. From Armv8.4 it is mandatory for all implementations to support it.
0.001111........1110.0..........
 QU     zeLMRm  codeH Rn   Rd   
 <Vd>:name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 2S
 1 | 4S
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 8B
 1 | 16B
 <Vm>:name of the second SIMD&FP source register, encoded in the "M:Rm" fields.
 <index>:element index, encoded in the "H:L" fields.

sdot (vector) - dot product signed arithmetic (vector) - performs the dot product of the four signed 8-bit elements in each 32-bit element of the first source register with the four signed 8-bit elements of the corresponding 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped. In Armv8.2 and Armv8.3, this is an OPTIONAL instruction. From Armv8.4 it is mandatory for all implementations to support it.
0.001110..0.....100101..........
 QU     ze Rm    code Rn   Rd   
 <Vd>:name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 2S
 1 | 4S
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 8B
 1 | 16B
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sha1c - sha1 hash update (choose) - SHA1 hash update (choose).
01011110000.....000000..........
        ze Rm    ode  Rn   Rd   
 <Qd>:128-bit name of the SIMD&FP source and destination, encoded in the "Rd" field.
 <Sn>:32-bit name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.

sha1h - sha1 fixed rotate - SHA1 fixed rotate.
0101111000101000000010..........
        ze     pcode  Rn   Rd   
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.

sha1m - sha1 hash update (majority) - SHA1 hash update (majority).
01011110000.....001000..........
        ze Rm    ode  Rn   Rd   
 <Qd>:128-bit name of the SIMD&FP source and destination, encoded in the "Rd" field.
 <Sn>:32-bit name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.

sha1p - sha1 hash update (parity) - SHA1 hash update (parity).
01011110000.....000100..........
        ze Rm    ode  Rn   Rd   
 <Qd>:128-bit name of the SIMD&FP source and destination, encoded in the "Rd" field.
 <Sn>:32-bit name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.

sha1su0 - sha1 schedule update 0 - SHA1 schedule update 0.
01011110000.....001100..........
        ze Rm    ode  Rn   Rd   
 <Vd>:name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Vn>:name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.

sha1su1 - sha1 schedule update 1 - SHA1 schedule update 1.
0101111000101000000110..........
        ze     pcode  Rn   Rd   
 <Vd>:name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Vn>:name of the second SIMD&FP source register, encoded in the "Rn" field.

sha256h - sha256 hash update (part 1) - SHA256 hash update (part 1).
01011110000.....010000..........
        ze Rm      P  Rn   Rd   
 <Qd>:128-bit name of the SIMD&FP source and destination, encoded in the "Rd" field.
 <Qn>:128-bit name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.

sha256h2 - sha256 hash update (part 2) - SHA256 hash update (part 2).
01011110000.....010100..........
        ze Rm      P  Rn   Rd   
 <Qd>:128-bit name of the SIMD&FP source and destination, encoded in the "Rd" field.
 <Qn>:128-bit name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.

sha256su0 - sha256 schedule update 0 - SHA256 schedule update 0.
0101111000101000001010..........
        ze     pcode  Rn   Rd   
 <Vd>:name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Vn>:name of the second SIMD&FP source register, encoded in the "Rn" field.

sha256su1 - sha256 schedule update 1 - SHA256 schedule update 1.
01011110000.....011000..........
        ze Rm    ode  Rn   Rd   
 <Vd>:name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Vn>:name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.

sha512h - sha512 hash update part 1 - takes the values from the three 128-bit source SIMD&FP registers and produces a 128-bit output value that combines the sigma1 and chi functions of two iterations of the SHA512 computation. It returns this value to the destination SIMD&FP register.
11001110011.....100000..........
           Rm    O  deRn   Rd   
 <Qd>:128-bit name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Qn>:128-bit name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.

sha512h2 - sha512 hash update part 2 - takes the values from the three 128-bit source SIMD&FP registers and produces a 128-bit output value that combines the sigma0 and majority functions of two iterations of the SHA512 computation. It returns this value to the destination SIMD&FP register.
11001110011.....100001..........
           Rm    O  deRn   Rd   
 <Qd>:128-bit name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Qn>:128-bit name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.

sha512su0 - sha512 schedule update 0 - takes the values from the two 128-bit source SIMD&FP registers and produces a 128-bit output value that combines the gamma0 functions of two iterations of the SHA512 schedule update that are performed after the first 16 iterations within a block. It returns this value to the destination SIMD&FP register.
1100111011000000100000..........
                    deRn   Rd   
 <Vd>:name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Vn>:name of the second SIMD&FP source register, encoded in the "Rn" field.

sha512su1 - sha512 schedule update 1 - takes the values from the three source SIMD&FP registers and produces a 128-bit output value that combines the gamma1 functions of two iterations of the SHA512 schedule update that are performed after the first 16 iterations within a block. It returns this value to the destination SIMD&FP register.
11001110011.....100010..........
           Rm    O  deRn   Rd   
 <Vd>:name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Vn>:name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.

shadd - signed halving add - adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SRHADD. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....000001..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

shl - shift left (immediate) - reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111101xxx...010101..........
  U      immhmmbpcode Rn   Rd   
0.0011110!= 0000!= 0000!= 0000!= 0000...010101..........
 QU      immhmmbpcode Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <shift>:For the "Scalar" variant: is the left shift amount, in the range 0 to 63, encoded as 
 <shift>
 immh | <shift>
 0001 | UInt(immh:immb) - 8
 001x | UInt(immh:immb) - 16
 01xx | UInt(immh:immb) - 32
 1xxx | UInt(immh:immb) - 64
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

shll, shll2 - shift left long (by element size) - reads each vector element in the lower or upper half of the  source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. The SHLL instruction extracts vector elements from the lower half of the source register. The SHLL2 instruction extracts vector elements from the upper half of the source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..100001001110..........
 QU     ze     pcode  Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <shift>
 size | <shift>
 00 | 8
 01 | 16
 10 | 32
 11 | RESERVED

shrn, shrn2 - shift right narrow (immediate) - reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN. The SHRN instruction writes the vector to the lower half of the destination register and clears the upper half. The SHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.0011110!= 0000!= 0000!= 0000!= 0000...100001..........
 QU      immhmmb    p Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 immh | Q | <Tb>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 immh | <Ta>
 0001 | 8H
 001x | 4S
 01xx | 2D
 1xxx | RESERVED
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | RESERVED

shsub - signed halving subtract - subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....001001..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sli - shift left and insert (immediate) - reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.  Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111101xxx...010101..........
  U      immhmmbpcode Rn   Rd   
0.1011110!= 0000!= 0000!= 0000!= 0000...010101..........
 QU      immhmmbpcode Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <shift>:For the "Scalar" variant: is the left shift amount, in the range 0 to 63, encoded as 
 <shift>
 immh | <shift>
 0001 | UInt(immh:immb) - 8
 001x | UInt(immh:immb) - 16
 01xx | UInt(immh:immb) - 32
 1xxx | UInt(immh:immb) - 64
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

sm3partw1 - sm3partw1 - takes three 128-bit vectors from the three source SIMD&FP registers and returns a 128-bit result in the destination SIMD&FP register. The result is obtained by a three-way exclusive-OR of the elements within the input vectors with some fixed rotations, see the Operation pseudocode for more information.
11001110011.....110000..........
           Rm    O  deRn   Rd   
 <Vd>:name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Vn>:name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.

sm3partw2 - sm3partw2 - takes three 128-bit vectors from three source SIMD&FP registers and returns a 128-bit result in the destination SIMD&FP register. The result is obtained by a three-way exclusive-OR of the elements within the input vectors with some fixed rotations, see the Operation pseudocode for more information.
11001110011.....110001..........
           Rm    O  deRn   Rd   
 <Vd>:name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Vn>:name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.

sm3ss1 - sm3ss1 - rotates the top 32 bits of the 128-bit vector in the first source SIMD&FP register by 12, and adds that 32-bit value to the two other 32-bit values held in the top 32 bits of each of the 128-bit vectors in the second and third source SIMD&FP registers, rotating this result left by 7 and writing the final result into the top 32 bits of the vector in the destination SIMD&FP register, with the bottom 96 bits of the vector being written to 0.
11001110010.....0...............
         p0Rm    Ra   Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Va>:name of the third SIMD&FP source register, encoded in the "Ra" field.

sm3tt1a - sm3tt1a - takes three 128-bit vectors from three source SIMD&FP registers and a 2-bit immediate index value, and returns a 128-bit result in the destination SIMD&FP register.  It performs a three-way exclusive-OR of the three 32-bit fields held in the upper three elements of the first source vector, and adds the resulting 32-bit value and the following three other 32-bit values: The result of this addition is returned as the top element of the result. The other elements of the result are taken from elements of the first source vector, with the element returned in bits<63:32> being rotated left by 9.
11001110010.....10..00..........
           Rm     m2deRn   Rd   
 <Vd>:name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Vn>:name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.
 <imm2>:Is a 32-bit element indexed out of <Vm>, encoded in "imm2".

sm3tt1b - sm3tt1b - takes three 128-bit vectors from three source SIMD&FP registers and a 2-bit immediate index value, and returns a 128-bit result in the destination SIMD&FP register. It performs a 32-bit majority function between the three 32-bit fields held in the upper three elements of the first source vector, and adds the resulting 32-bit value and the following three other 32-bit values: The result of this addition is returned as the top element of the result. The other elements of the result are taken from elements of the first source vector, with the element returned in bits<63:32> being rotated left by 9.
11001110010.....10..01..........
           Rm     m2deRn   Rd   
 <Vd>:name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Vn>:name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.
 <imm2>:Is a 32-bit element indexed out of <Vm>, encoded in "imm2".

sm3tt2a - sm3tt2a - takes three 128-bit vectors from three source SIMD&FP register and a 2-bit immediate index value, and returns a 128-bit result in the destination SIMD&FP register. It performs a three-way exclusive-OR of the three 32-bit fields held in the upper three elements of the first source vector, and adds the resulting 32-bit value and the following three other 32-bit values: A three-way exclusive-OR is performed of the result of this addition, the result of the addition rotated left by 9, and the result of the addition rotated left by 17. The result of this exclusive-OR is returned as the top element of the returned result. The other elements of this result are taken from elements of the first source vector, with the element returned in bits<63:32> being rotated left by 19.
11001110010.....10..10..........
           Rm     m2deRn   Rd   
 <Vd>:name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Vn>:name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.
 <imm2>:Is a 32-bit element indexed out of <Vm>, encoded in "imm2".

sm3tt2b - sm3tt2b - takes three 128-bit vectors from three source SIMD&FP registers, and a 2-bit immediate index value, and returns a 128-bit result in the destination SIMD&FP register. It performs a 32-bit majority function between the three 32-bit fields held in the upper three elements of the first source vector, and adds the resulting 32-bit value and the following three other 32-bit values: A three-way exclusive-OR is performed of the result of this addition, the result of the addition rotated left by 9, and the result of the addition rotated left by 17. The result of this exclusive-OR is returned as the top element of the returned result. The other elements of this result are taken from elements of the first source vector, with the element returned in bits<63:32> being rotated left by 19.
11001110010.....10..11..........
           Rm     m2deRn   Rd   
 <Vd>:name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Vn>:name of the second SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the third SIMD&FP source register, encoded in the "Rm" field.
 <imm2>:Is a 32-bit element indexed out of <Vm>, encoded in "imm2".

sm4e - sm4 encode - takes input data as a 128-bit vector from the first source SIMD&FP register, and four iterations of the round key held as the elements of the 128-bit vector in the second source SIMD&FP register. It encrypts the data by four rounds, in accordance with the SM4 standard, returning the 128-bit result to the destination SIMD&FP register.
1100111011000000100001..........
                    deRn   Rd   
 <Vd>:name of the SIMD&FP source and destination register, encoded in the "Rd" field.
 <Vn>:name of the second SIMD&FP source register, encoded in the "Rn" field.

sm4ekey - sm4 key - takes an input as a 128-bit vector from the first source SIMD&FP register and a 128-bit constant from the second SIMD&FP register. It derives four iterations of the output key, in accordance with the SM4 standard, returning the 128-bit result to the destination SIMD&FP register.
11001110011.....110010..........
           Rm    O  deRn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

smax - signed maximum (vector) - compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....011001..........
 QU     ze Rm       1 Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

smaxp - signed maximum pairwise - creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....101001..........
 QU     ze Rm       1 Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

smaxv - signed maximum across vector - compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..110000101010..........
 QU     ze     p      Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | RESERVED
 10 | 1 | 4S
 11 | x | RESERVED

smin - signed minimum (vector) - compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....011011..........
 QU     ze Rm       1 Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sminp - signed minimum pairwise - creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....101011..........
 QU     ze Rm       1 Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sminv - signed minimum across vector - compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..110001101010..........
 QU     ze     p      Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | RESERVED
 10 | 1 | 4S
 11 | x | RESERVED

smlal, smlal2 (by element) - signed multiply-add long (vector, by element) - multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values. The SMLAL instruction extracts vector elements from the lower half of the first source register. The SMLAL2 instruction extracts vector elements from the upper half of the first source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001111........0010.0..........
 QU     zeLMRm   2  H Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | RESERVED
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED

smlal, smlal2 (vector) - signed multiply-add long (vector) - multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. The SMLAL instruction extracts each source vector from the lower half of each source register. The SMLAL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....100000..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

smlsl, smlsl2 (by element) - signed multiply-subtract long (vector, by element) - multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. The SMLSL instruction extracts vector elements from the lower half of the first source register. The SMLSL2 instruction extracts vector elements from the upper half of the first source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001111........0110.0..........
 QU     zeLMRm   2  H Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | RESERVED
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED

smlsl, smlsl2 (vector) - signed multiply-subtract long (vector) - multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. The SMLSL instruction extracts each source vector from the lower half of each source register. The SMLSL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....101000..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

smmla (vector) - signed 8-bit integer matrix multiply-accumulate (vector) - multiplies the 2x8 matrix of signed 8-bit integer values in the first source vector by the 8x2 matrix of signed 8-bit integer values in the second source vector. The resulting 2x2 32-bit integer matrix product is destructively added to the 32-bit integer matrix accumulator in the destination vector. This is equivalent to performing an 8-way dot product per destination element. From Armv8.2 to Armv8.5, this is an OPTIONAL instruction. From Armv8.6 it is mandatory for implementations that include Advanced SIMD to support it. ID_AA64ISAR1_EL1.I8MM indicates whether this instruction is supported.
01001110100.....101001..........
 QU     ze Rm       B Rn   Rd   
 <Vd>:name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

smov - signed move vector element to general-purpose register - reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110000.....001011..........
 Qp        imm5  imm4 Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ts>
 imm5 | <Ts>
 xxx00 | RESERVED
 xxxx1 | B
 xxx10 | H
 <Ts>
 imm5 | <Ts>
 xx000 | RESERVED
 xxxx1 | B
 xxx10 | H
 xx100 | S
 <index>
 imm5 | <index>
 xxx00 | RESERVED
 xxxx1 | UInt(imm5<4:1>)
 xxx10 | UInt(imm5<4:2>)
 <index>
 imm5 | <index>
 xx000 | RESERVED
 xxxx1 | UInt(imm5<4:1>)
 xxx10 | UInt(imm5<4:2>)
 xx100 | UInt(imm5<4:3>)
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.

smull, smull2 (by element) - signed multiply long (vector, by element) - multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. The SMULL instruction extracts vector elements from the lower half of the first source register. The SMULL2 instruction extracts vector elements from the upper half of the first source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001111........1010.0..........
 QU     zeLMRm  codeH Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | RESERVED
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED

smull, smull2 (vector) - signed multiply long (vector) - multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. The SMULL instruction extracts each source vector from the lower half of each source register. The SMULL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....110000..........
 QU     ze Rm   code  Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sqabs - signed saturating absolute value - reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110..100000011110..........
  U     ze     pcode  Rn   Rd   
0.001110..100000011110..........
 QU     ze     pcode  Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

sqadd - signed saturating add - adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110..1.....000011..........
  U     ze Rm   pcode Rn   Rd   
0.001110..1.....000011..........
 QU     ze Rm   pcode Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sqdmlal, sqdmlal2 (by element) - signed saturating doubling multiply-add long (by element) - multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. The SQDMLAL instruction extracts vector elements from the lower half of the first source register. The SQDMLAL2 instruction extracts vector elements from the upper half of the first source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011111........0011.0..........
  U     zeLMRm   2  H Rn   Rd   
0.001111........0011.0..........
 QU     zeLMRm   2  H Rn   Rd   
 <Va>
 size | <Va>
 00 | RESERVED
 01 | S
 10 | D
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vb>
 size | <Vb>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | RESERVED
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED

sqdmlal, sqdmlal2 (vector) - signed saturating doubling multiply-add long - multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. The SQDMLAL instruction extracts each source vector from the lower half of each source register. The SQDMLAL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110..1.....100100..........
  U     ze Rm     1   Rn   Rd   
0.001110..1.....100100..........
 QU     ze Rm     1   Rn   Rd   
 <Va>
 size | <Va>
 00 | RESERVED
 01 | S
 10 | D
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vb>
 size | <Vb>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | RESERVED
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sqdmlsl, sqdmlsl2 (by element) - signed saturating doubling multiply-subtract long (by element) - multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. The SQDMLSL instruction extracts vector elements from the lower half of the first source register. The SQDMLSL2 instruction extracts vector elements from the upper half of the first source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011111........0111.0..........
  U     zeLMRm   2  H Rn   Rd   
0.001111........0111.0..........
 QU     zeLMRm   2  H Rn   Rd   
 <Va>
 size | <Va>
 00 | RESERVED
 01 | S
 10 | D
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vb>
 size | <Vb>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | RESERVED
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED

sqdmlsl, sqdmlsl2 (vector) - signed saturating doubling multiply-subtract long - multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. The SQDMLSL instruction extracts each source vector from the lower half of each source register. The SQDMLSL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110..1.....101100..........
  U     ze Rm     1   Rn   Rd   
0.001110..1.....101100..........
 QU     ze Rm     1   Rn   Rd   
 <Va>
 size | <Va>
 00 | RESERVED
 01 | S
 10 | D
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vb>
 size | <Vb>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | RESERVED
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sqdmulh (by element) - signed saturating doubling multiply returning high half (by element) - multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRDMULH. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011111........1100.0..........
  U     zeLMRm     pH Rn   Rd   
0.001111........1100.0..........
 QU     zeLMRm     pH Rn   Rd   
 <V>
 size | <V>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.

sqdmulh (vector) - signed saturating doubling multiply returning high half - multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRDMULH. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110..1.....101101..........
  U     ze Rm   pcode Rn   Rd   
0.001110..1.....101101..........
 QU     ze Rm   pcode Rn   Rd   
 <V>
 size | <V>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sqdmull, sqdmull2 (by element) - signed saturating doubling multiply long (by element) - multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. The SQDMULL instruction extracts the first source vector from the lower half of the first source register. The SQDMULL2 instruction extracts the first source vector from the upper half of the first source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001111........1011.0..........
 QU     zeLMRm  codeH Rn   Rd   
01011111........1011.0..........
  U     zeLMRm  codeH Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | RESERVED
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED
 <Va>
 size | <Va>
 00 | RESERVED
 01 | S
 10 | D
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vb>
 size | <Vb>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.

sqdmull, sqdmull2 (vector) - signed saturating doubling multiply long - multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. The SQDMULL instruction extracts each source vector from the lower half of each source register. The SQDMULL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110..1.....110100..........
  U     ze Rm   code  Rn   Rd   
0.001110..1.....110100..........
 QU     ze Rm   code  Rn   Rd   
 <Va>
 size | <Va>
 00 | RESERVED
 01 | S
 10 | D
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vb>
 size | <Vb>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | RESERVED
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sqneg - signed saturating negate - reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110..100000011110..........
  U     ze     pcode  Rn   Rd   
0.101110..100000011110..........
 QU     ze     pcode  Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

sqrdmlah (by element) - signed saturating rounding doubling multiply accumulate returning high half (by element) - multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111111........1101.0..........
  U     zeLMRm    S H Rn   Rd   
0.101111........1101.0..........
 QU     zeLMRm    S H Rn   Rd   
 <V>
 size | <V>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.

sqrdmlah (vector) - signed saturating rounding doubling multiply accumulate returning high half (vector) - multiplies the vector elements of the first source SIMD&FP register with the corresponding vector elements of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110..0.....100001..........
  U     ze Rm       S Rn   Rd   
0.101110..0.....100001..........
 QU     ze Rm       S Rn   Rd   
 <V>
 size | <V>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sqrdmlsh (by element) - signed saturating rounding doubling multiply subtract returning high half (by element) - multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111111........1111.0..........
  U     zeLMRm    S H Rn   Rd   
0.101111........1111.0..........
 QU     zeLMRm    S H Rn   Rd   
 <V>
 size | <V>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.

sqrdmlsh (vector) - signed saturating rounding doubling multiply subtract returning high half (vector) - multiplies the vector elements of the first source SIMD&FP register with the corresponding vector elements of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110..0.....100011..........
  U     ze Rm       S Rn   Rd   
0.101110..0.....100011..........
 QU     ze Rm       S Rn   Rd   
 <V>
 size | <V>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sqrdmulh (by element) - signed saturating rounding doubling multiply returning high half (by element) - multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQDMULH. If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011111........1101.0..........
  U     zeLMRm     pH Rn   Rd   
0.001111........1101.0..........
 QU     zeLMRm     pH Rn   Rd   
 <V>
 size | <V>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.

sqrdmulh (vector) - signed saturating rounding doubling multiply returning high half - multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQDMULH. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110..1.....101101..........
  U     ze Rm   pcode Rn   Rd   
0.101110..1.....101101..........
 QU     ze Rm   pcode Rn   Rd   
 <V>
 size | <V>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sqrshl - signed saturating rounding shift left (register) - takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see SQSHL. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110..1.....010111..........
  U     ze Rm      RS Rn   Rd   
0.001110..1.....010111..........
 QU     ze Rm      RS Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sqrshrn, sqrshrn2 - signed saturating rounded shift right narrow (immediate) - reads each vector element in the  source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN. The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half. The SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
010111110!= 0000!= 0000!= 0000!= 0000...100111..........
  U      immhmmb    p Rn   Rd   
0.0011110!= 0000!= 0000!= 0000!= 0000...100111..........
 QU      immhmmb    p Rn   Rd   
 <Vb>
 immh | <Vb>
 0001 | B
 001x | H
 01xx | S
 1xxx | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Va>
 immh | <Va>
 0001 | H
 001x | S
 01xx | D
 1xxx | RESERVED
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | RESERVED
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | RESERVED
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 immh | Q | <Tb>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 immh | <Ta>
 0001 | 8H
 001x | 4S
 01xx | 2D
 1xxx | RESERVED

sqrshrun, sqrshrun2 - signed saturating rounded shift right unsigned narrow (immediate) - reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN. The SQRSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half. The SQRSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
011111110!= 0000!= 0000!= 0000!= 0000...100011..........
  U      immhmmb    p Rn   Rd   
0.1011110!= 0000!= 0000!= 0000!= 0000...100011..........
 QU      immhmmb    p Rn   Rd   
 <Vb>
 immh | <Vb>
 0001 | B
 001x | H
 01xx | S
 1xxx | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Va>
 immh | <Va>
 0001 | H
 001x | S
 01xx | D
 1xxx | RESERVED
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | RESERVED
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | RESERVED
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 immh | Q | <Tb>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 immh | <Ta>
 0001 | 8H
 001x | 4S
 01xx | 2D
 1xxx | RESERVED

sqshl (immediate) - signed saturating shift left (immediate) - reads each vector element in the source SIMD&FP register, shifts each result by an immediate value, places the final result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
010111110!= 0000!= 0000!= 0000!= 0000...011101..........
  U      immhmmb   p  Rn   Rd   
0.0011110!= 0000!= 0000!= 0000!= 0000...011101..........
 QU      immhmmb   p  Rn   Rd   
 <V>
 immh | <V>
 0001 | B
 001x | H
 01xx | S
 1xxx | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <shift>
 immh | <shift>
 0001 | UInt(immh:immb) - 8
 001x | UInt(immh:immb) - 16
 01xx | UInt(immh:immb) - 32
 1xxx | UInt(immh:immb) - 64
 <shift>
 immh | <shift>
 0001 | UInt(immh:immb) - 8
 001x | UInt(immh:immb) - 16
 01xx | UInt(immh:immb) - 32
 1xxx | UInt(immh:immb) - 64
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

sqshl (register) - signed saturating shift left (register) - takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are truncated. For rounded results, see SQRSHL. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110..1.....010011..........
  U     ze Rm      RS Rn   Rd   
0.001110..1.....010011..........
 QU     ze Rm      RS Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sqshlu - signed saturating shift left unsigned (immediate) - reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
011111110!= 0000!= 0000!= 0000!= 0000...011001..........
  U      immhmmb   p  Rn   Rd   
0.1011110!= 0000!= 0000!= 0000!= 0000...011001..........
 QU      immhmmb   p  Rn   Rd   
 <V>
 immh | <V>
 0001 | B
 001x | H
 01xx | S
 1xxx | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <shift>
 immh | <shift>
 0001 | UInt(immh:immb) - 8
 001x | UInt(immh:immb) - 16
 01xx | UInt(immh:immb) - 32
 1xxx | UInt(immh:immb) - 64
 <shift>
 immh | <shift>
 0001 | UInt(immh:immb) - 8
 001x | UInt(immh:immb) - 16
 01xx | UInt(immh:immb) - 32
 1xxx | UInt(immh:immb) - 64
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

sqshrn, sqshrn2 - signed saturating shift right narrow (immediate) - reads each vector element in the  source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN. The SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half. The SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
010111110!= 0000!= 0000!= 0000!= 0000...100101..........
  U      immhmmb    p Rn   Rd   
0.0011110!= 0000!= 0000!= 0000!= 0000...100101..........
 QU      immhmmb    p Rn   Rd   
 <Vb>
 immh | <Vb>
 0001 | B
 001x | H
 01xx | S
 1xxx | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Va>
 immh | <Va>
 0001 | H
 001x | S
 01xx | D
 1xxx | RESERVED
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | RESERVED
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | RESERVED
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 immh | Q | <Tb>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 immh | <Ta>
 0001 | 8H
 001x | 4S
 01xx | 2D
 1xxx | RESERVED

sqshrun, sqshrun2 - signed saturating shift right unsigned narrow (immediate) - reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN. The SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half. The SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
011111110!= 0000!= 0000!= 0000!= 0000...100001..........
  U      immhmmb    p Rn   Rd   
0.1011110!= 0000!= 0000!= 0000!= 0000...100001..........
 QU      immhmmb    p Rn   Rd   
 <Vb>
 immh | <Vb>
 0001 | B
 001x | H
 01xx | S
 1xxx | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Va>
 immh | <Va>
 0001 | H
 001x | S
 01xx | D
 1xxx | RESERVED
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | RESERVED
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | RESERVED
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 immh | Q | <Tb>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 immh | <Ta>
 0001 | 8H
 001x | 4S
 01xx | 2D
 1xxx | RESERVED

sqsub - signed saturating subtract - subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110..1.....001011..........
  U     ze Rm   pcode Rn   Rd   
0.001110..1.....001011..........
 QU     ze Rm   pcode Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sqxtn, sqxtn2 - signed saturating extract narrow - reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half. The SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110..100001010010..........
  U     ze     pcode  Rn   Rd   
0.001110..100001010010..........
 QU     ze     pcode  Rn   Rd   
 <Vb>
 size | <Vb>
 00 | B
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Va>
 size | <Va>
 00 | H
 01 | S
 10 | D
 11 | RESERVED
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED

sqxtun, sqxtun2 - signed saturating extract unsigned narrow - reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. If saturation occurs, the cumulative saturation bit FPSR.QC is set. The SQXTUN instruction writes the vector to the lower half of the destination register and clears the upper half. The SQXTUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110..100001001010..........
  U     ze     pcode  Rn   Rd   
0.101110..100001001010..........
 QU     ze     pcode  Rn   Rd   
 <Vb>
 size | <Vb>
 00 | B
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Va>
 size | <Va>
 00 | H
 01 | S
 10 | D
 11 | RESERVED
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED

srhadd - signed rounding halving add - adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SHADD. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....000101..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sri - shift right and insert (immediate) - reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.  Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111101xxx...010001..........
  U      immhmmbpcode Rn   Rd   
0.1011110!= 0000!= 0000!= 0000!= 0000...010001..........
 QU      immhmmbpcode Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <shift>:For the "Scalar" variant: is the right shift amount, in the range 1 to 64, encoded as 
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

srshl - signed rounding shift left (register) - takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110111.....010101..........
  U     ze Rm      RS Rn   Rd   
0.001110..1.....010101..........
 QU     ze Rm      RS Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

srshr - signed rounding shift right (immediate) - reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111101xxx...001001..........
  U      immhmmb  10  Rn   Rd   
0.0011110!= 0000!= 0000!= 0000!= 0000...001001..........
 QU      immhmmb  10  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <shift>:For the "Scalar" variant: is the right shift amount, in the range 1 to 64, encoded as 
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

srsra - signed rounding shift right and accumulate (immediate) - reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111101xxx...001101..........
  U      immhmmb  10  Rn   Rd   
0.0011110!= 0000!= 0000!= 0000!= 0000...001101..........
 QU      immhmmb  10  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <shift>:For the "Scalar" variant: is the right shift amount, in the range 1 to 64, encoded as 
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

sshl - signed shift left (register) - takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see SRSHL. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110111.....010001..........
  U     ze Rm      RS Rn   Rd   
0.001110..1.....010001..........
 QU     ze Rm      RS Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sshll, sshll2 - signed shift left long (immediate) - reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values. The SSHLL instruction extracts vector elements from the lower half of the source register. The SSHLL2 instruction extracts vector elements from the upper half of the source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.0011110!= 0000!= 0000!= 0000!= 0000...101001..........
 QU      immhmmbpcode Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 immh | <Ta>
 0001 | 8H
 001x | 4S
 01xx | 2D
 1xxx | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 immh | Q | <Tb>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | x | RESERVED
 <shift>
 immh | <shift>
 0001 | UInt(immh:immb) - 8
 001x | UInt(immh:immb) - 16
 01xx | UInt(immh:immb) - 32
 1xxx | RESERVED

sshr - signed shift right (immediate) - reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111101xxx...000001..........
  U      immhmmb  10  Rn   Rd   
0.0011110!= 0000!= 0000!= 0000!= 0000...000001..........
 QU      immhmmb  10  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <shift>:For the "Scalar" variant: is the right shift amount, in the range 1 to 64, encoded as 
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

ssra - signed shift right and accumulate (immediate) - reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0101111101xxx...000101..........
  U      immhmmb  10  Rn   Rd   
0.0011110!= 0000!= 0000!= 0000!= 0000...000101..........
 QU      immhmmb  10  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <shift>:For the "Scalar" variant: is the right shift amount, in the range 1 to 64, encoded as 
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

ssubl, ssubl2 - signed subtract long - subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements. The SSUBL instruction extracts each source vector from the lower half of each source register. The SSUBL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....001000..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

ssubw, ssubw2 - signed subtract wide - subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values. The SSUBW instruction extracts the second source vector from the lower half of the second source register. The SSUBW2 instruction extracts the second source vector from the upper half of the second source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....001100..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED

st1 (multiple structures) - store multiple single-element structures from one, two, three, or four registers - stores elements to memory from one, two, three, or four SIMD&FP registers, without interleaving. Every element of each register is stored. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00110000000000xx1x............
 Q       L      codezeRn   Rt   
0.001100100.....xx1x............
 Q       L Rm   codezeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | 1D
 11 | 1 | 2D
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <Vt3>:name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32.
 <Vt4>:name of the fourth SIMD&FP register to be transferred, encoded as "Rt" plus 3 modulo 32.
 <imm>
 Q | <imm>
 0 | #8
 1 | #16
 <imm>
 Q | <imm>
 0 | #16
 1 | #32
 <imm>
 Q | <imm>
 0 | #24
 1 | #48
 <imm>
 Q | <imm>
 0 | #32
 1 | #64
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

st1 (single structure) - store a single-element structure from one lane of one register - stores the specified element of a SIMD&FP register to memory. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00110100000000xx0.............
 Q       LR    2odeSzeRn   Rt   
0.001101100.....xx0.............
 Q       LRRm   odeSzeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <index>:For the "8-bit", "8-bit, immediate offset", and "8-bit, register offset" variants: is the element index, encoded in "Q:S:size".
 <index>:For the "16-bit", "16-bit, immediate offset", and "16-bit, register offset" variants: is the element index, encoded in "Q:S:size<1>".
 <index>:For the "32-bit", "32-bit, immediate offset", and "32-bit, register offset" variants: is the element index, encoded in "Q:S".
 <index>:For the "64-bit", "64-bit, immediate offset", and "64-bit, register offset" variants: is the element index, encoded in "Q".
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

st2 (multiple structures) - store multiple 2-element structures from two registers - stores multiple 2-element structures from two SIMD&FP registers to memory, with interleaving. Every element of each register is stored. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001100000000001000............
 Q       L      codezeRn   Rt   
0.001100100.....1000............
 Q       L Rm   codezeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>
 Q | <imm>
 0 | #16
 1 | #32
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

st2 (single structure) - store single 2-element structure from one lane of two registers - stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00110100100000xx0.............
 Q       LR    2odeSzeRn   Rt   
0.001101101.....xx0.............
 Q       LRRm   odeSzeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <index>:For the "8-bit", "8-bit, immediate offset", and "8-bit, register offset" variants: is the element index, encoded in "Q:S:size".
 <index>:For the "16-bit", "16-bit, immediate offset", and "16-bit, register offset" variants: is the element index, encoded in "Q:S:size<1>".
 <index>:For the "32-bit", "32-bit, immediate offset", and "32-bit, register offset" variants: is the element index, encoded in "Q:S".
 <index>:For the "64-bit", "64-bit, immediate offset", and "64-bit, register offset" variants: is the element index, encoded in "Q".
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

st3 (multiple structures) - store multiple 3-element structures from three registers - stores multiple 3-element structures to memory from three SIMD&FP registers, with interleaving. Every element of each register is stored. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001100000000000100............
 Q       L      codezeRn   Rt   
0.001100100.....0100............
 Q       L Rm   codezeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <Vt3>:name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>
 Q | <imm>
 0 | #24
 1 | #48
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

st3 (single structure) - store single 3-element structure from one lane of three registers - stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00110100000000xx1.............
 Q       LR    2odeSzeRn   Rt   
0.001101100.....xx1.............
 Q       LRRm   odeSzeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <Vt3>:name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32.
 <index>:For the "8-bit", "8-bit, immediate offset", and "8-bit, register offset" variants: is the element index, encoded in "Q:S:size".
 <index>:For the "16-bit", "16-bit, immediate offset", and "16-bit, register offset" variants: is the element index, encoded in "Q:S:size<1>".
 <index>:For the "32-bit", "32-bit, immediate offset", and "32-bit, register offset" variants: is the element index, encoded in "Q:S".
 <index>:For the "64-bit", "64-bit, immediate offset", and "64-bit, register offset" variants: is the element index, encoded in "Q".
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

st4 (multiple structures) - store multiple 4-element structures from four registers - stores multiple 4-element structures to memory from four SIMD&FP registers, with interleaving. Every element of each register is stored. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001100000000000000............
 Q       L      codezeRn   Rt   
0.001100100.....0000............
 Q       L Rm   codezeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <Vt3>:name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32.
 <Vt4>:name of the fourth SIMD&FP register to be transferred, encoded as "Rt" plus 3 modulo 32.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>
 Q | <imm>
 0 | #32
 1 | #64
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

st4 (single structure) - store single 4-element structure from one lane of four registers - stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00110100100000xx1.............
 Q       LR    2odeSzeRn   Rt   
0.001101101.....xx1.............
 Q       LRRm   odeSzeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Vt2>:name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
 <Vt3>:name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32.
 <Vt4>:name of the fourth SIMD&FP register to be transferred, encoded as "Rt" plus 3 modulo 32.
 <index>:For the "8-bit", "8-bit, immediate offset", and "8-bit, register offset" variants: is the element index, encoded in "Q:S:size".
 <index>:For the "16-bit", "16-bit, immediate offset", and "16-bit, register offset" variants: is the element index, encoded in "Q:S:size<1>".
 <index>:For the "32-bit", "32-bit, immediate offset", and "32-bit, register offset" variants: is the element index, encoded in "Q:S".
 <index>:For the "64-bit", "64-bit, immediate offset", and "64-bit, register offset" variants: is the element index, encoded in "Q".
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

stbfadd, stbfaddl - bfloat16 floating-point atomic add in memory, without return - atomically loads a 16-bit value from memory, adds it to the BFloat16 value held in a register, and stores the result back to memory. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
001111000.1.....100000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stbfmax, stbfmaxl - bfloat16 floating-point atomic maximum in memory, without return - atomically loads a 16-bit value from memory, computes the BFloat16 maximum with the value held in a register, and stores the result back to memory. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
001111000.1.....110000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stbfmaxnm, stbfmaxnml - bfloat16 floating-point atomic maximum number in memory, without return - atomically loads a 16-bit value from memory, computes the BFloat16 maximum number with the value held in a register, and stores the result back to memory. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
001111000.1.....111000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stbfmin, stbfminl - bfloat16 floating-point atomic minimum in memory, without return - atomically loads a 16-bit value from memory, computes the BFloat16 minimum with the value held in a register, and stores the result back to memory. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
001111000.1.....110100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stbfminnm, stbfminnml - bfloat16 floating-point atomic minimum number in memory, without return - atomically loads a 16-bit value from memory, computes the BFloat16 minimum number with the value held in a register, and stores the result back to memory. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
001111000.1.....111100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stfadd, stfaddl - floating-point atomic add in memory, without return - atomically loads a 16-bit, 32-bit, or 64-bit value from memory, performs a floating-point add with the value held in a register, and stores the result back to memory. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
..1111000.1.....100000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Ss>:32-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Ds>:64-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

stfmax, stfmaxl - floating-point atomic maximum in memory, without return - atomically loads a 16-bit, 32-bit, or 64-bit value from memory, computes the floating-point maximum with the value held in a register, and stores the result back to memory. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
..1111000.1.....110000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Ss>:32-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Ds>:64-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

stfmaxnm, stfmaxnml - floating-point atomic maximum number in memory, without return - atomically loads a 16-bit, 32-bit, or 64-bit value from memory, computes the floating-point maximum number with the value held in a register, and stores the result back to memory. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
..1111000.1.....111000.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Ss>:32-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Ds>:64-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

stfmin, stfminl - floating-point atomic minimum in memory, without return - atomically loads a 16-bit, 32-bit, or 64-bit value from memory, computes the floating-point minimum with the value held in a register, and stores the result back to memory. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
..1111000.1.....110100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Ss>:32-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Ds>:64-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

stfminnm, stfminnml - floating-point atomic minimum number in memory, without return - atomically loads a 16-bit, 32-bit, or 64-bit value from memory, computes the floating-point minimum number with the value held in a register, and stores the result back to memory. This instruction: For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
..1111000.1.....111100.....11111
ze   R  AR Rs   3opc  Rn   Rt   
 <Hs>:16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Ss>:32-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
 <Ds>:64-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

stl1 (simd&fp) - store-release a single-element structure from one lane of one register - stores the specified element of a SIMD&FP register to memory. The instruction also has memory ordering semantics, as described in Load-Acquire, Load-AcquirePC, and Store-Release. For information about addressing modes, see Load/Store addressing modes. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.00110100000001100001..........
 Q       LR    2odeSzeRn   Rt   
 <Vt>:name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
 <index>:element index, encoded in "Q".
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

stlur (simd&fp) - store-release simd&fp register (unscaled offset) - stores a single SIMD&FP register to memory. The address that is used for the store is calculated from a base register value and an optional immediate offset. The instruction has memory ordering semantics, as described in Load-Acquire, Load-AcquirePC, and Store-Release. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
..011101x00.........10..........
ze      pc imm9       Rn   Rt   
 <Bt>:8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Ht>:16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <St>:32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Dt>:64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt>:128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

stnp (simd&fp) - store pair of simd&fp registers, with non-temporal hint - stores a pair of SIMD&FP registers to memory, issuing a hint to the memory system that the access is non-temporal. The address used for the store is calculated from an address from a base register value and an immediate offset. For information about non-temporal pair instructions, see Load/Store SIMD and Floating-point non-temporal pair. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
..10110000......................
pc   R   Limm7   Rt2  Rn   Rt   
 <St1>:32-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <St2>:32-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "32-bit" variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.
 <imm>:For the "64-bit" variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.
 <imm>:For the "128-bit" variant: is the optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as <imm>/16.
 <Dt1>:64-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Dt2>:64-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.
 <Qt1>:128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt2>:128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.

stp (simd&fp) - store pair of simd&fp registers - stores a pair of SIMD&FP registers to memory. The address used for the store is calculated from a base register value and an immediate offset. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
..10110010......................
pc   R   Limm7   Rt2  Rn   Rt   
..10110110......................
pc   R   Limm7   Rt2  Rn   Rt   
..10110100......................
pc   R   Limm7   Rt2  Rn   Rt   
 <St1>:32-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <St2>:32-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "32-bit Post-index" and "32-bit Pre-index" variants: is the signed immediate byte offset, a multiple of 4 in the range -256 to 252, encoded in the "imm7" field as <imm>/4.
 <imm>:For the "64-bit Post-index" and "64-bit Pre-index" variants: is the signed immediate byte offset, a multiple of 8 in the range -512 to 504, encoded in the "imm7" field as <imm>/8.
 <imm>:For the "128-bit Post-index" and "128-bit Pre-index" variants: is the signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, encoded in the "imm7" field as <imm>/16.
 <imm>:For the "32-bit Signed offset" variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.
 <imm>:For the "64-bit Signed offset" variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.
 <imm>:For the "128-bit Signed offset" variant: is the optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as <imm>/16.
 <Dt1>:64-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Dt2>:64-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.
 <Qt1>:128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt2>:128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.

str (immediate, simd&fp) - store simd&fp register (immediate offset) - stores a single SIMD&FP register to memory. The address that is used for the store is calculated from a base register value and an immediate offset. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
..111100x00.........01..........
ze   R  pc imm9       Rn   Rt   
..111100x00.........11..........
ze   R  pc imm9       Rn   Rt   
..111101x0......................
ze   R  pcimm12       Rn   Rt   
 <Bt>:8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.
 <Ht>:16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <St>:32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Dt>:64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt>:128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <pimm>:For the "8-bit" variant: is the optional positive immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
 <pimm>:For the "16-bit" variant: is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0 and encoded in the "imm12" field as <pimm>/2.
 <pimm>:For the "32-bit" variant: is the optional positive immediate byte offset, a multiple of 4 in the range 0 to 16380, defaulting to 0 and encoded in the "imm12" field as <pimm>/4.
 <pimm>:For the "64-bit" variant: is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as <pimm>/8.
 <pimm>:For the "128-bit" variant: is the optional positive immediate byte offset, a multiple of 16 in the range 0 to 65520, defaulting to 0 and encoded in the "imm12" field as <pimm>/16.

str (register, simd&fp) - store simd&fp register (register offset) - stores a single SIMD&FP register to memory. The address that is used for the store is calculated from a base register value and an offset register value. The offset can be optionally shifted and extended. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
..111100x01.........10..........
ze   R  pc Rm   ionS  Rn   Rt   
 <Bt>:8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Wm>:When 
 <Xm>:When 
 <extend>
 option | <extend>
 010 | UXTW
 110 | SXTW
 111 | SXTX
 <extend>
 option | <extend>
 010 | UXTW
 011 | LSL
 110 | SXTW
 111 | SXTX
 <amount>:For the "8-bit" variant: is the index shift amount, it must be 
 <amount>
 S | <amount>
 0 | #0
 1 | #1
 <amount>
 S | <amount>
 0 | #0
 1 | #2
 <amount>
 S | <amount>
 0 | #0
 1 | #3
 <amount>
 S | <amount>
 0 | #0
 1 | #4
 <Ht>:16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <St>:32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Dt>:64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt>:128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

sttnp (simd&fp) - store unprivileged pair of simd&fp registers, with non-temporal hint - stores a pair of SIMD&FP registers to memory, issuing a hint to the memory system that the access is non-temporal. The address used for the store is calculated from an address from a base register value and an immediate offset. For information about non-temporal pair instructions, see Load/Store SIMD and Floating-point non-temporal pair. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
1110110000......................
pc   R   Limm7   Rt2  Rn   Rt   
 <Qt1>:128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt2>:128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as <imm>/16.

sttp (simd&fp) - store unprivileged pair of simd&fp registers - stores a pair of SIMD&FP registers to memory. The address used for the store is calculated from a base register value and an immediate offset. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped. Explicit Memory  effects produced by the instruction behave as if the instruction was   executed at EL0 if the Effective value of   PSTATE.UAO is 0 and either: Otherwise, the Explicit Memory  effects operate with the restrictions determined by   the Exception level at which the instruction is executed.
1110110010......................
pc   R   Limm7   Rt2  Rn   Rt   
1110110110......................
pc   R   Limm7   Rt2  Rn   Rt   
1110110100......................
pc   R   Limm7   Rt2  Rn   Rt   
 <Qt1>:128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt2>:128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Post-index" and "Pre-index" variants: is the signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, encoded in the "imm7" field as <imm>/16.
 <imm>:For the "Signed offset" variant: is the optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as <imm>/16.

stur (simd&fp) - store simd&fp register (unscaled offset) - stores a single SIMD&FP register to memory. The address that is used for the store is calculated from a base register value and an optional immediate offset. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
..111100x00.........00..........
ze   R  pc imm9       Rn   Rt   
 <Bt>:8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <simm>:optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
 <Ht>:16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <St>:32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Dt>:64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
 <Qt>:128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

sub (vector) - subtract (vector) - subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110111.....100001..........
  U     ze Rm   pcode Rn   Rd   
0.101110..1.....100001..........
 QU     ze Rm   pcode Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

subhn, subhn2 - subtract returning high narrow - subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see RSUBHN. The SUBHN instruction writes the vector to the lower half of the destination register and clears the upper half. The SUBHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..1.....011000..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

sudot (by element) - dot product with signed and unsigned integers (vector, by element) - performs the dot product of the four signed 8-bit integer values in each 32-bit element of the first source register with the four unsigned 8-bit integer values in an indexed 32-bit element of the second source register, accumulating the result into the corresponding 32-bit element of the destination vector. From Armv8.2 to Armv8.5, this is an OPTIONAL instruction. From Armv8.6 it is mandatory for implementations that include Advanced SIMD to support it. ID_AA64ISAR1_EL1.I8MM indicates whether this instruction is supported.
0.00111100......1111.0..........
 QU     S LMRm  codeH Rn   Rd   
 <Vd>:name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 2S
 1 | 4S
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 8B
 1 | 16B
 <Vm>:name of the second SIMD&FP source register, encoded in the "M:Rm" fields.
 <index>:immediate index of a 32-bit group of four 8-bit values, in the range 0 to 3, encoded in the "H:L" fields.

suqadd - signed saturating accumulate of unsigned value - adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01011110..100000001110..........
  U     ze     pcode  Rn   Rd   
0.001110..100000001110..........
 QU     ze     pcode  Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

sxtl, sxtl2 - signed extend long - duplicates each vector element in the lower or upper half of the source SIMD&FP register into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values. The SXTL instruction extracts the source vector from the lower half of the source register. The SXTL2 instruction extracts the source vector from the upper half of the source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.0011110!= 0000!= 0000!= 0000!= 0000000101001..........
 QU      immhmmbpcode Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 immh | <Ta>
 0001 | 8H
 001x | 4S
 01xx | 2D
 1xxx | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 immh | Q | <Tb>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | x | RESERVED

tbl - table vector lookup - reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110000.....0..000..........
 Q      p2 Rm    enp  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 8B
 1 | 16B
 <Vn>:For the "Single register table" variant: is the name of the SIMD&FP table register, encoded in the "Rn" field.
 <Vn>:For the "Four register table", "Three register table", and "Two register table" variants: is the name of the first SIMD&FP table register, encoded in the "Rn" field.
 <Vm>:name of the SIMD&FP index register, encoded in the "Rm" field.
 <Vn+1>:name of the second SIMD&FP table register, encoded as "Rn" plus 1 modulo 32.
 <Vn+2>:name of the third SIMD&FP table register, encoded as "Rn" plus 2 modulo 32.
 <Vn+3>:name of the fourth SIMD&FP table register, encoded as "Rn" plus 3 modulo 32.

tbx - table vector lookup extension - reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110000.....0..100..........
 Q      p2 Rm    enp  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 8B
 1 | 16B
 <Vn>:For the "Single register table" variant: is the name of the SIMD&FP table register, encoded in the "Rn" field.
 <Vn>:For the "Four register table", "Three register table", and "Two register table" variants: is the name of the first SIMD&FP table register, encoded in the "Rn" field.
 <Vm>:name of the SIMD&FP index register, encoded in the "Rm" field.
 <Vn+1>:name of the second SIMD&FP table register, encoded as "Rn" plus 1 modulo 32.
 <Vn+2>:name of the third SIMD&FP table register, encoded as "Rn" plus 2 modulo 32.
 <Vn+3>:name of the fourth SIMD&FP table register, encoded as "Rn" plus 3 modulo 32.

trn1 - transpose vectors (primary) - reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.  Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..0.....001010..........
 Q      ze Rm    p    Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

trn2 - transpose vectors (secondary) - reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.  Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..0.....011010..........
 Q      ze Rm    p    Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uaba - unsigned absolute difference and accumulate - subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....011111..........
 QU     ze Rm       c Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uabal, uabal2 - unsigned absolute difference and accumulate long - subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values. The UABAL instruction extracts each source vector from the lower half of each source register. The UABAL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....010100..........
 QU     ze Rm     p   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uabd - unsigned absolute difference (vector) - subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....011101..........
 QU     ze Rm       c Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uabdl, uabdl2 - unsigned absolute difference long - subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values. The UABDL instruction extracts each source vector from the lower half of each source register. The UABDL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....011100..........
 QU     ze Rm     p   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uadalp - unsigned add and accumulate long pairwise - adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..100000011010..........
 QU     ze       p    Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | Q | <Ta>
 00 | 0 | 4H
 00 | 1 | 8H
 01 | 0 | 2S
 01 | 1 | 4S
 10 | 0 | 1D
 10 | 1 | 2D
 11 | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED

uaddl, uaddl2 - unsigned add long (vector) - adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values. The UADDL instruction extracts each source vector from the lower half of each source register. The UADDL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....000000..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uaddlp - unsigned add long pairwise - adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..100000001010..........
 QU     ze       p    Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | Q | <Ta>
 00 | 0 | 4H
 00 | 1 | 8H
 01 | 0 | 2S
 01 | 1 | 4S
 10 | 0 | 1D
 10 | 1 | 2D
 11 | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED

uaddlv - unsigned sum long across vector - adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..110000001110..........
 QU     ze     pcode  Rn   Rd   
 <V>
 size | <V>
 00 | H
 01 | S
 10 | D
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | RESERVED
 10 | 1 | 4S
 11 | x | RESERVED

uaddw, uaddw2 - unsigned add wide - adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values. The UADDW instruction extracts vector elements from the lower half of the second source register. The UADDW2 instruction extracts vector elements from the upper half of the second source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....000100..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED

ucvtf (scalar simd&fp) - unsigned integer convert to floating-point (scalar simd&fp) - converts the unsigned integer value in the SIMD&FP source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..111101000000..........
f S     pe deode      Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Sn>:32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dn>:64-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

ucvtf (scalar, fixed-point) - unsigned fixed-point convert to floating-point (scalar) - converts the unsigned value in the 32-bit or 64-bit general-purpose source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..000011................
f S     pe deodescale Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <fbits>:For the "32-bit to double-precision", "32-bit to half-precision", and "32-bit to single-precision" variants: is the number of bits after the binary point in the fixed-point source, in the range 1 to 32, encoded as 64 minus "scale".
 <fbits>:For the "64-bit to double-precision", "64-bit to half-precision", and "64-bit to single-precision" variants: is the number of bits after the binary point in the fixed-point source, in the range 1 to 64, encoded as 64 minus "scale".
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

ucvtf (scalar, integer) - unsigned integer convert to floating-point (scalar) - converts the unsigned integer value in the general-purpose source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
.0011110..100011000000..........
f S     pe deode      Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Wn>:32-bit name of the general-purpose source register, encoded in the "Rn" field.
 <Sd>:32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Dd>:64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Xn>:64-bit name of the general-purpose source register, encoded in the "Rn" field.

ucvtf (vector, fixed-point) - unsigned fixed-point convert to floating-point (vector) - converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
011111110!= 0000!= 0000!= 0000!= 0000...111001..........
  U      immhmmbpcode Rn   Rd   
0.1011110!= 0000!= 0000!= 0000!= 0000...111001..........
 QU      immhmmbpcode Rn   Rd   
 <V>
 immh | <V>
 0001 | RESERVED
 001x | H
 01xx | S
 1xxx | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <fbits>
 immh | <fbits>
 0001 | RESERVED
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <fbits>
 immh | <fbits>
 0001 | RESERVED
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | x | RESERVED
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

ucvtf (vector, integer) - unsigned integer convert to floating-point (vector) - converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register. can generate a floating-point exception.   Depending on the settings in FPCR,   the exception results in either a flag being set in FPSR   or a synchronous exception being generated.   For more information, see   Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111001111001110110..........
  U     a      pcode  Rn   Rd   
011111100.100001110110..........
  U      z     pcode  Rn   Rd   
0.10111001111001110110..........
 QU     a      pcode  Rn   Rd   
0.1011100.100001110110..........
 QU      z     pcode  Rn   Rd   
 <Hd>:16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Hn>:16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
 <V>
 sz | <V>
 0 | S
 1 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 Q | <T>
 0 | 4H
 1 | 8H
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | 0 | RESERVED
 1 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

udot (by element) - dot product unsigned arithmetic (vector, by element) - performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped. In Armv8.2 and Armv8.3, this is an OPTIONAL instruction. From Armv8.4 it is mandatory for all implementations to support it.
0.101111........1110.0..........
 QU     zeLMRm  codeH Rn   Rd   
 <Vd>:name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 2S
 1 | 4S
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 8B
 1 | 16B
 <Vm>:name of the second SIMD&FP source register, encoded in the "M:Rm" fields.
 <index>:element index, encoded in the "H:L" fields.

udot (vector) - dot product unsigned arithmetic (vector) - performs the dot product of the four unsigned 8-bit elements in each 32-bit element of the first source register with the four unsigned 8-bit elements of the corresponding 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped. In Armv8.2 and Armv8.3, this is an OPTIONAL instruction. From Armv8.4 it is mandatory for all implementations to support it.
0.101110..0.....100101..........
 QU     ze Rm    code Rn   Rd   
 <Vd>:name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 2S
 1 | 4S
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 8B
 1 | 16B
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uhadd - unsigned halving add - adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see URHADD. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....000001..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uhsub - unsigned halving subtract - subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....001001..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

umax - unsigned maximum (vector) - compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....011001..........
 QU     ze Rm       1 Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

umaxp - unsigned maximum pairwise - creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....101001..........
 QU     ze Rm       1 Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

umaxv - unsigned maximum across vector - compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..110000101010..........
 QU     ze     p      Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | RESERVED
 10 | 1 | 4S
 11 | x | RESERVED

umin - unsigned minimum (vector) - compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....011011..........
 QU     ze Rm       1 Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uminp - unsigned minimum pairwise - creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....101011..........
 QU     ze Rm       1 Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uminv - unsigned minimum across vector - compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..110001101010..........
 QU     ze     p      Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | RESERVED
 10 | 1 | 4S
 11 | x | RESERVED

umlal, umlal2 (by element) - unsigned multiply-add long (vector, by element) - multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. The UMLAL instruction extracts vector elements from the lower half of the first source register. The UMLAL2 instruction extracts vector elements from the upper half of the first source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101111........0010.0..........
 QU     zeLMRm   2  H Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | RESERVED
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED

umlal, umlal2 (vector) - unsigned multiply-add long (vector) - multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. The UMLAL instruction extracts vector elements from the lower half of the first source register. The UMLAL2 instruction extracts vector elements from the upper half of the first source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....100000..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

umlsl, umlsl2 (by element) - unsigned multiply-subtract long (vector, by element) - multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. The UMLSL instruction extracts vector elements from the lower half of the first source register. The UMLSL2 instruction extracts vector elements from the upper half of the first source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101111........0110.0..........
 QU     zeLMRm   2  H Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | RESERVED
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED

umlsl, umlsl2 (vector) - unsigned multiply-subtract long (vector) - multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values. The UMLSL instruction extracts each source vector from the lower half of each source register. The UMLSL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....101000..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

ummla (vector) - unsigned 8-bit integer matrix multiply-accumulate (vector) - multiplies the 2x8 matrix of unsigned 8-bit integer values in the first source vector by the 8x2 matrix of unsigned 8-bit integer values in the second source vector. The resulting 2x2 32-bit integer matrix product is destructively added to the 32-bit integer matrix accumulator in the destination vector. This is equivalent to performing an 8-way dot product per destination element. From Armv8.2 to Armv8.5, this is an OPTIONAL instruction. From Armv8.6 it is mandatory for implementations that include Advanced SIMD to support it. ID_AA64ISAR1_EL1.I8MM indicates whether this instruction is supported.
01101110100.....101001..........
 QU     ze Rm       B Rn   Rd   
 <Vd>:name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

umov - unsigned move vector element to general-purpose register - reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110000.....001111..........
 Qp        imm5  imm4 Rn   Rd   
 <Wd>:32-bit name of the general-purpose destination register, encoded in the "Rd" field.
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ts>
 imm5 | <Ts>
 xx000 | RESERVED
 xxxx1 | B
 xxx10 | H
 xx100 | S
 <index>
 imm5 | <index>
 xx000 | RESERVED
 xxxx1 | UInt(imm5<4:1>)
 xxx10 | UInt(imm5<4:2>)
 xx100 | UInt(imm5<4:3>)
 <index>:For the "64-bit" variant: is the element index encoded in "imm5<4>".
 <Xd>:64-bit name of the general-purpose destination register, encoded in the "Rd" field.

umull, umull2 (by element) - unsigned multiply long (vector, by element) - multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. The UMULL instruction extracts vector elements from the lower half of the first source register. The UMULL2 instruction extracts vector elements from the upper half of the first source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101111........1010.0..........
 QU     zeLMRm  codeH Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | RESERVED
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | x | RESERVED
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>
 size | <Vm>
 00 | RESERVED
 01 | UInt('0':Rm)
 10 | UInt(M:Rm)
 11 | RESERVED
 Restricted to V0-V15 when element size <Ts> is H.
 <Ts>
 size | <Ts>
 00 | RESERVED
 01 | H
 10 | S
 11 | RESERVED
 <index>
 size | <index>
 00 | RESERVED
 01 | UInt(H:L:M)
 10 | UInt(H:L)
 11 | RESERVED

umull, umull2 (vector) - unsigned multiply long (vector) - multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values. The UMULL instruction extracts each source vector from the lower half of each source register. The UMULL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....110000..........
 QU     ze Rm   code  Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uqadd - unsigned saturating add - adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110..1.....000011..........
  U     ze Rm   pcode Rn   Rd   
0.101110..1.....000011..........
 QU     ze Rm   pcode Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uqrshl - unsigned saturating rounding shift left (register) - takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110..1.....010111..........
  U     ze Rm      RS Rn   Rd   
0.101110..1.....010111..........
 QU     ze Rm      RS Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uqrshrn, uqrshrn2 - unsigned saturating rounded shift right narrow (immediate) - reads each vector element in the  source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN. The UQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half. The UQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
011111110!= 0000!= 0000!= 0000!= 0000...100111..........
  U      immhmmb    p Rn   Rd   
0.1011110!= 0000!= 0000!= 0000!= 0000...100111..........
 QU      immhmmb    p Rn   Rd   
 <Vb>
 immh | <Vb>
 0001 | B
 001x | H
 01xx | S
 1xxx | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Va>
 immh | <Va>
 0001 | H
 001x | S
 01xx | D
 1xxx | RESERVED
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | RESERVED
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | RESERVED
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 immh | Q | <Tb>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 immh | <Ta>
 0001 | 8H
 001x | 4S
 01xx | 2D
 1xxx | RESERVED

uqshl (immediate) - unsigned saturating shift left (immediate) - takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
011111110!= 0000!= 0000!= 0000!= 0000...011101..........
  U      immhmmb   p  Rn   Rd   
0.1011110!= 0000!= 0000!= 0000!= 0000...011101..........
 QU      immhmmb   p  Rn   Rd   
 <V>
 immh | <V>
 0001 | B
 001x | H
 01xx | S
 1xxx | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <shift>
 immh | <shift>
 0001 | UInt(immh:immb) - 8
 001x | UInt(immh:immb) - 16
 01xx | UInt(immh:immb) - 32
 1xxx | UInt(immh:immb) - 64
 <shift>
 immh | <shift>
 0001 | UInt(immh:immb) - 8
 001x | UInt(immh:immb) - 16
 01xx | UInt(immh:immb) - 32
 1xxx | UInt(immh:immb) - 64
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

uqshl (register) - unsigned saturating shift left (register) - takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are truncated. For rounded results, see UQRSHL. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110..1.....010011..........
  U     ze Rm      RS Rn   Rd   
0.101110..1.....010011..........
 QU     ze Rm      RS Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uqshrn, uqshrn2 - unsigned saturating shift right narrow (immediate) - reads each vector element in the  source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN. The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half. The UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
011111110!= 0000!= 0000!= 0000!= 0000...100101..........
  U      immhmmb    p Rn   Rd   
0.1011110!= 0000!= 0000!= 0000!= 0000...100101..........
 QU      immhmmb    p Rn   Rd   
 <Vb>
 immh | <Vb>
 0001 | B
 001x | H
 01xx | S
 1xxx | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Va>
 immh | <Va>
 0001 | H
 001x | S
 01xx | D
 1xxx | RESERVED
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | RESERVED
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | RESERVED
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 immh | Q | <Tb>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 immh | <Ta>
 0001 | 8H
 001x | 4S
 01xx | 2D
 1xxx | RESERVED

uqsub - unsigned saturating subtract - subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110..1.....001011..........
  U     ze Rm   pcode Rn   Rd   
0.101110..1.....001011..........
 QU     ze Rm   pcode Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uqxtn, uqxtn2 - unsigned saturating extract narrow - reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. If saturation occurs, the cumulative saturation bit FPSR.QC is set. The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half. The UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110..100001010010..........
  U     ze     pcode  Rn   Rd   
0.101110..100001010010..........
 QU     ze     pcode  Rn   Rd   
 <Vb>
 size | <Vb>
 00 | B
 01 | H
 10 | S
 11 | RESERVED
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <Va>
 size | <Va>
 00 | H
 01 | S
 10 | D
 11 | RESERVED
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED

urecpe - unsigned reciprocal estimate - reads each vector element from the source SIMD&FP register, calculates an approximate inverse for the unsigned integer value, places the result into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.0011101.100001110010..........
 QU      z     pcode  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

urhadd - unsigned rounding halving add - adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see UHADD. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....000101..........
 QU     ze Rm   pcode Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

urshl - unsigned rounding shift left (register) - takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110111.....010101..........
  U     ze Rm      RS Rn   Rd   
0.101110..1.....010101..........
 QU     ze Rm      RS Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

urshr - unsigned rounding shift right (immediate) - reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111101xxx...001001..........
  U      immhmmb  10  Rn   Rd   
0.1011110!= 0000!= 0000!= 0000!= 0000...001001..........
 QU      immhmmb  10  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <shift>:For the "Scalar" variant: is the right shift amount, in the range 1 to 64, encoded as 
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

ursqrte - unsigned reciprocal square root estimate - reads each vector element from the source SIMD&FP register, calculates an approximate inverse square root for each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.1011101.100001110010..........
 QU      z     pcode  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 sz | Q | <T>
 0 | 0 | 2S
 0 | 1 | 4S
 1 | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

ursra - unsigned rounding shift right and accumulate (immediate) - reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111101xxx...001101..........
  U      immhmmb  10  Rn   Rd   
0.1011110!= 0000!= 0000!= 0000!= 0000...001101..........
 QU      immhmmb  10  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <shift>:For the "Scalar" variant: is the right shift amount, in the range 1 to 64, encoded as 
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

usdot (by element) - dot product with unsigned and signed integers (vector, by element) - performs the dot product of the four unsigned 8-bit integer values in each 32-bit element of the first source register with the four signed 8-bit integer values in an indexed 32-bit element of the second source register, accumulating the result into the corresponding 32-bit element of the destination register. From Armv8.2 to Armv8.5, this is an OPTIONAL instruction. From Armv8.6 it is mandatory for implementations that include Advanced SIMD to support it. ID_AA64ISAR1_EL1.I8MM indicates whether this instruction is supported.
0.00111110......1111.0..........
 QU     S LMRm  codeH Rn   Rd   
 <Vd>:name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 2S
 1 | 4S
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 8B
 1 | 16B
 <Vm>:name of the second SIMD&FP source register, encoded in the "M:Rm" fields.
 <index>:immediate index of a 32-bit group of four 8-bit values, in the range 0 to 3, encoded in the "H:L" fields.

usdot (vector) - dot product with unsigned and signed integers (vector) - performs the dot product of the four unsigned 8-bit integer values in each 32-bit element of the first source register with the four signed 8-bit integer values in the corresponding 32-bit element of the second source register, accumulating the result into the corresponding 32-bit element of the destination register. From Armv8.2 to Armv8.5, this is an OPTIONAL instruction. From Armv8.6 it is mandatory for implementations that include Advanced SIMD to support it. ID_AA64ISAR1_EL1.I8MM indicates whether this instruction is supported.
0.001110100.....100111..........
 QU     ze Rm    code Rn   Rd   
 <Vd>:name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
 <Ta>
 Q | <Ta>
 0 | 2S
 1 | 4S
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 Q | <Tb>
 0 | 8B
 1 | 16B
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

ushl - unsigned shift left (register) - takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift. For a rounding shift, see URSHL. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110111.....010001..........
  U     ze Rm      RS Rn   Rd   
0.101110..1.....010001..........
 QU     ze Rm      RS Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <m>:number of the second SIMD&FP source register, encoded in the "Rm" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

ushll, ushll2 - unsigned shift left long (immediate) - reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. The USHLL instruction extracts vector elements from the lower half of the source register. The USHLL2 instruction extracts vector elements from the upper half of the source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.1011110!= 0000!= 0000!= 0000!= 0000...101001..........
 QU      immhmmbpcode Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 immh | <Ta>
 0001 | 8H
 001x | 4S
 01xx | 2D
 1xxx | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 immh | Q | <Tb>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | x | RESERVED
 <shift>
 immh | <shift>
 0001 | UInt(immh:immb) - 8
 001x | UInt(immh:immb) - 16
 01xx | UInt(immh:immb) - 32
 1xxx | RESERVED

ushr - unsigned shift right (immediate) - reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111101xxx...000001..........
  U      immhmmb  10  Rn   Rd   
0.1011110!= 0000!= 0000!= 0000!= 0000...000001..........
 QU      immhmmb  10  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <shift>:For the "Scalar" variant: is the right shift amount, in the range 1 to 64, encoded as 
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

usmmla (vector) - unsigned and signed 8-bit integer matrix multiply-accumulate (vector) - multiplies the 2x8 matrix of unsigned 8-bit integer values in the first source vector by the 8x2 matrix of signed 8-bit integer values in the second source vector. The resulting 2x2 32-bit integer matrix product is destructively added to the 32-bit integer matrix accumulator in the destination vector. This is equivalent to performing an 8-way dot product per destination element. From Armv8.2 to Armv8.5, this is an OPTIONAL instruction. From Armv8.6 it is mandatory for implementations that include Advanced SIMD to support it. ID_AA64ISAR1_EL1.I8MM indicates whether this instruction is supported.
01001110100.....101011..........
 QU     ze Rm       B Rn   Rd   
 <Vd>:name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

usqadd - unsigned saturating accumulate of signed value - adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
01111110..100000001110..........
  U     ze     pcode  Rn   Rd   
0.101110..100000001110..........
 QU     ze     pcode  Rn   Rd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the SIMD&FP source register, encoded in the "Rn" field.
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

usra - unsigned shift right and accumulate (immediate) - reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0111111101xxx...000101..........
  U      immhmmb  10  Rn   Rd   
0.1011110!= 0000!= 0000!= 0000!= 0000...000101..........
 QU      immhmmb  10  Rn   Rd   
 <d>:number of the SIMD&FP destination register, encoded in the "Rd" field.
 <n>:number of the first SIMD&FP source register, encoded in the "Rn" field.
 <shift>:For the "Scalar" variant: is the right shift amount, in the range 1 to 64, encoded as 
 <shift>
 immh | <shift>
 0001 | 16 - UInt(immh:immb)
 001x | 32 - UInt(immh:immb)
 01xx | 64 - UInt(immh:immb)
 1xxx | 128 - UInt(immh:immb)
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 immh | Q | <T>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | 0 | RESERVED
 1xxx | 1 | 2D
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.

usubl, usubl2 - unsigned subtract long - subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements. The USUBL instruction extracts each source vector from the lower half of each source register. The USUBL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....001000..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

usubw, usubw2 - unsigned subtract wide - subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are unsigned integer values. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. The USUBW instruction extracts vector elements from the lower half of the first source register. The USUBW2 instruction extracts vector elements from the upper half of the first source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.101110..1.....001100..........
 QU     ze Rm     1   Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED

uxtl, uxtl2 - unsigned extend long - copies each vector element from the lower or upper half of the source SIMD&FP register into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. The UXTL instruction extracts vector elements from the lower half of the source register. The UXTL2 instruction extracts vector elements from the upper half of the source register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.1011110!= 0000!= 0000!= 0000!= 0000000101001..........
 QU      immhmmbpcode Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Ta>
 immh | <Ta>
 0001 | 8H
 001x | 4S
 01xx | 2D
 1xxx | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Tb>
 immh | Q | <Tb>
 0001 | 0 | 8B
 0001 | 1 | 16B
 001x | 0 | 4H
 001x | 1 | 8H
 01xx | 0 | 2S
 01xx | 1 | 4S
 1xxx | x | RESERVED

uzp1 - unzip vectors (primary) - reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.  Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..0.....000110..........
 Q      ze Rm    p    Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

uzp2 - unzip vectors (secondary) - reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.  Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..0.....010110..........
 Q      ze Rm    p    Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

xar - exclusive-or and rotate - performs a bitwise exclusive-OR of the 128-bit vectors in the two source SIMD&FP registers, rotates each 64-bit element of the resulting 128-bit vector right by the value specified by a 6-bit immediate value, and writes the result to the destination SIMD&FP register.
11001110100.....................
           Rm   imm6  Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.
 <imm6>:Is a rotation right, encoded in "imm6".

xtn, xtn2 - extract narrow - reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The XTN instruction writes the vector to the lower half of the destination register and clears the upper half. The XTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..100001001010..........
 QU     ze     pcode  Rn   Rd   
 2
 Q | 2
 0 | [absent]
 1 | [present]
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <Tb>
 size | Q | <Tb>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | x | RESERVED
 <Vn>:name of the SIMD&FP source register, encoded in the "Rn" field.
 <Ta>
 size | <Ta>
 00 | 8H
 01 | 4S
 10 | 2D
 11 | RESERVED

zip1 - zip vectors (primary) - reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.  Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..0.....001110..........
 Q      ze Rm    p    Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

zip2 - zip vectors (secondary) - reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.  Depending on the settings in the CPACR_EL1,   CPTR_EL2, and CPTR_EL3 registers,   and the current Security state and Exception level,   an attempt to execute the instruction might be trapped.
0.001110..0.....011110..........
 Q      ze Rm    p    Rn   Rd   
 <Vd>:name of the SIMD&FP destination register, encoded in the "Rd" field.
 <T>
 size | Q | <T>
 00 | 0 | 8B
 00 | 1 | 16B
 01 | 0 | 4H
 01 | 1 | 8H
 10 | 0 | 2S
 10 | 1 | 4S
 11 | 0 | RESERVED
 11 | 1 | 2D
 <Vn>:name of the first SIMD&FP source register, encoded in the "Rn" field.
 <Vm>:name of the second SIMD&FP source register, encoded in the "Rm" field.

abs - absolute value (predicated) - Compute the absolute value of the signed integer in each active element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
00000100..010110101.............
        ze M opc   Pg Zn   Zd   
00000100..000110101.............
        ze M opc   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

adclb - add with carry long (bottom) - Add the even-numbered elements of the first source vector and the  1-bit carry from the least-significant bit of the odd-numbered elements of the second source vector to the even-numbered elements of the destination and accumulator vector. The 1-bit carry output is placed in the corresponding odd-numbered element of the destination vector.
010001010.0.....110100..........
         z Zm        TZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 sz | <T>
 0 | S
 1 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

adclt - add with carry long (top) - Add the odd-numbered elements of the first source vector and the  1-bit carry from the least-significant bit of the odd-numbered elements of the second source vector to the even-numbered elements of the destination and accumulator vector. The 1-bit carry output is placed in the corresponding odd-numbered element of the destination vector.
010001010.0.....110101..........
         z Zm        TZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 sz | <T>
 0 | S
 1 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

add (immediate) - add immediate (unpredicated) - Add an unsigned immediate to each element of the source vector, and destructively place the results in the corresponding elements of the  source vector. is unpredicated. The immediate is an unsigned value in the range 0 to 255, and for element widths of 16 bits or higher it may also be a positive multiple of 256 in the range 256 to 65280. The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<uimm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".
00100101..10000011..............
        ze   opc  himm8    Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm>:Is an unsigned immediate in the range 0 to 255, encoded in the "imm8" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #8

add (vectors, predicated) - add vectors (predicated) - Add active elements of the second source vector to corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..000000000.............
        ze   opc   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

add (vectors, unpredicated) - add vectors (unpredicated) - Add all elements of the second source vector to corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. is unpredicated.
00000100..1.....000000..........
        ze Zm      opcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

addhnb - add narrow high part (bottom) - Add each vector element of the first source vector to the corresponding vector element of the second source vector, and place the most significant half of the result in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. is unpredicated.
01000101..1.....011000..........
        ze Zm      SRTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

addhnt - add narrow high part (top) - Add each vector element of the first source vector to the corresponding vector element of the second source vector, and place the most significant half of the result in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. is unpredicated.
01000101..1.....011001..........
        ze Zm      SRTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

addp - add pairwise - Add pairs of adjacent elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector.
01000100..010001101.............
        ze   pcU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

addpl - add multiple of predicate register size to scalar register - Add the current predicate register size in bytes multiplied by an immediate in the range -32 to 31 to the 64-bit source general-purpose register or current stack pointer and place the result in the 64-bit destination general-purpose register or current stack pointer.
00000100011.....01010...........
         p Rn        imm6  Rd   
 <Xd|SP>:64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.
 <imm>:signed immediate operand, in the range -32 to 31, encoded in the "imm6" field.

addpt (predicated) - add checked pointer vectors (predicated) - Add with pointer check active elements of the second source vector to corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
0000010011000100000.............
        ze   opc   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

addpt (unpredicated) - add checked pointer vectors (unpredicated) - Add with pointer check all elements of the second source vector to corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. is unpredicated. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
00000100111.....000010..........
        ze Zm      opcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

addqv - unsigned add reduction of quadword vector segments - Unsigned addition of the same element numbers from each 128-bit source vector segment, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as zero.
00000100..000101001.............
        ze    pU   Pg Zn   Vd   
 <Vd>:name of the destination SIMD&FP register, encoded in the "Vd" field.
 <T>
 size | <T>
 00 | 16B
 01 | 8H
 10 | 4S
 11 | 2D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | B
 01 | H
 10 | S
 11 | D

addvl - add multiple of vector register size to scalar register - Add the current vector register size in bytes multiplied by an immediate in the range -32 to 31 to the 64-bit source general-purpose register or current stack pointer, and place the result in the 64-bit destination general-purpose register or current stack pointer.
00000100001.....01010...........
         p Rn        imm6  Rd   
 <Xd|SP>:64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
 <Xn|SP>:64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.
 <imm>:signed immediate operand, in the range -32 to 31, encoded in the "imm6" field.

adr - compute vector address - Optionally sign or zero-extend the least significant 32-bits of each element from a vector of offsets or indices in the second source vector, scale each index by 2, 4 or 8, add to a vector of base addresses from the first source vector, and place the resulting addresses in the destination vector. is unpredicated. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
000001001.1.....1010............
         z Zm       szZn   Zd   
00000100001.....1010............
        pc Zm       szZn   Zd   
00000100011.....1010............
        pc Zm       szZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 sz | <T>
 0 | S
 1 | D
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 msz | <mod>
 00 | [absent]
 x1 | LSL
 10 | LSL
 <amount>
 msz | <amount>
 00 | [absent]
 01 | #1
 10 | #2
 11 | #3

aesd (indexed) - multi-vector aes single round decryption - The AESD instruction reads a 16-byte state array from each 128-bit segment of the two or four first source vectors, together with a round key from the indexed 128-bit segment of the corresponding 512-bit portion of the second source vector. Each state array undergoes a single round of the AddRoundKey(), InvShiftRows(), and InvSubBytes() transformations in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the two or four first source vectors. When the vector length is less than 512 bits, the most significant bits of the index are ignored to select the indexed 128-bit segment of the second source vector. is unpredicated. is legal in Streaming SVE mode if both FEAT_SSVE_AES and FEAT_SVE_AES2 are implemented.
01000101001..010111011.........0
        ze i2  p     2Zm   Zdn 3
01000101001..110111011........00
        ze i2  p     2Zm   Zdnc3
 <Zdn1>:For the "Two registers" variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2.
 <Zdn1>:For the "Four registers" variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4.
 <Zdn2>:name of the second scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2 plus 1.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <index>:round key index, in the range 0 to 3, encoded in the "i2" field.
 <Zdn4>:name of the fourth scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4 plus 3.

aesd (vectors) - aes single round decryption - The AESD instruction reads a 16-byte state array from each 128-bit segment of the first source vector, together with a round key from the corresponding 128-bit segment of the second source vector. Each state array undergoes a single round of the AddRoundKey(), InvShiftRows() and InvSubBytes() transformations in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. is unpredicated. ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented. is legal in Streaming SVE mode if one of the following is true:
0100010100100010111001..........
        ze     p     2Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

aesdimc - multi-vector aes single round decryption and inverse mix columns - The AESDIMC instruction reads a 16-byte state array from each 128-bit segment of the two or four first source vectors, together with a round key from the indexed 128-bit segment of the corresponding 512-bit portion of the second source vector. Each state array undergoes a single round of the AddRoundKey(), InvShiftRows(), InvSubBytes(), and InvMixColumns() transformations in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the two or four first source vectors. When the vector length is less than 512 bits, the most significant bits of the index are ignored to select the indexed 128-bit segment of the second source vector. is unpredicated. is legal in Streaming SVE mode if both FEAT_SSVE_AES and FEAT_SVE_AES2 are implemented.
01000101001..011111011.........0
        ze i2  p     2Zm   Zdn 3
01000101001..111111011........00
        ze i2  p     2Zm   Zdnc3
 <Zdn1>:For the "Two registers" variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2.
 <Zdn1>:For the "Four registers" variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4.
 <Zdn2>:name of the second scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2 plus 1.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <index>:round key index, in the range 0 to 3, encoded in the "i2" field.
 <Zdn4>:name of the fourth scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4 plus 3.

aese (indexed) - multi-vector aes single round encryption - The AESE instruction reads a 16-byte state array from each 128-bit segment of the two or four first source vectors, together with a round key from the indexed 128-bit segment of the corresponding 512-bit portion of the second source vector. Each state array undergoes a single round of the AddRoundKey(), ShiftRows(), and SubBytes() transformations in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the two or four first source vectors. When the vector length is less than 512 bits, the most significant bits of the index are ignored to select the indexed 128-bit segment of the second source vector. is unpredicated. is legal in Streaming SVE mode if both FEAT_SSVE_AES and FEAT_SVE_AES2 are implemented.
01000101001..010111010.........0
        ze i2  p     2Zm   Zdn 3
01000101001..110111010........00
        ze i2  p     2Zm   Zdnc3
 <Zdn1>:For the "Two registers" variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2.
 <Zdn1>:For the "Four registers" variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4.
 <Zdn2>:name of the second scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2 plus 1.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <index>:round key index, in the range 0 to 3, encoded in the "i2" field.
 <Zdn4>:name of the fourth scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4 plus 3.

aese (vectors) - aes single round encryption - The AESE instruction reads a 16-byte state array from each 128-bit segment of the first source vector together with a round key from the corresponding 128-bit segment of the second source vector. Each state array undergoes a single round of the AddRoundKey(), ShiftRows() and SubBytes() transformations in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. is unpredicated. ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented. is legal in Streaming SVE mode if one of the following is true:
0100010100100010111000..........
        ze     p     2Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

aesemc - multi-vector aes single round encryption and mix columns - The AESEMC instruction reads a 16-byte state array from each 128-bit segment of the two or four first source vectors, together with a round key from the indexed 128-bit segment of the corresponding 512-bit portion of the second source vector. Each state array undergoes a single round of the AddRoundKey(), ShiftRows(), SubBytes(), and MixColumns() transformations in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the two or four first source vectors. When the vector length is less than 512 bits, the most significant bits of the index are ignored to select the indexed 128-bit segment of the second source vector. is unpredicated. is legal in Streaming SVE mode if both FEAT_SSVE_AES and FEAT_SVE_AES2 are implemented.
01000101001..011111010.........0
        ze i2  p     2Zm   Zdn 3
01000101001..111111010........00
        ze i2  p     2Zm   Zdnc3
 <Zdn1>:For the "Two registers" variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2.
 <Zdn1>:For the "Four registers" variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4.
 <Zdn2>:name of the second scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2 plus 1.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <index>:round key index, in the range 0 to 3, encoded in the "i2" field.
 <Zdn4>:name of the fourth scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4 plus 3.

aesimc - aes inverse mix columns - The AESIMC instruction reads a 16-byte state array from each 128-bit segment of the source register, and performs a single round of the InvMixColumns() transformation on each state array in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. is unpredicated. ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented. is legal in Streaming SVE mode if one of the following is true:
010001010010000011100100000.....
        ze           p     Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.

aesmc - aes mix columns - The AESMC instruction reads a 16-byte state array from each 128-bit segment of the source register, and performs a single round of the MixColumns() transformation on each state array in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. is unpredicated. ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented. is legal in Streaming SVE mode if one of the following is true:
010001010010000011100000000.....
        ze           p     Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.

and (immediate) - bitwise and with immediate (unpredicated) - Bitwise AND an immediate with each 64-bit element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits. is unpredicated.
00000101100000..................
        pc    imm13        Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 imm13 | <T>
 0xxxxxx0xxxxx | S
 0xxxxxx10xxxx | H
 0xxxxxx110xxx | B
 0xxxxxx1110xx | B
 0xxxxxx11110x | B
 0xxxxxx11111x | RESERVED
 1xxxxxxxxxxxx | D
 <const>:Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.

and (predicates) - bitwise and predicates - Bitwise AND active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
001001010000....01....0....0....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

and (vectors, predicated) - bitwise and vectors (predicated) - Bitwise AND active elements of the second source vector with corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..011010000.............
        ze   opc   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

and (vectors, unpredicated) - bitwise and vectors (unpredicated) - Bitwise AND all elements of the second source vector with corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. is unpredicated.
00000100001.....001100..........
        pc Zm         Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

andqv - bitwise and reduction of quadword vector segments - Bitwise AND of the same element numbers from each 128-bit source vector segment, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as all ones.
00000100..011110001.............
        ze    pc   Pg Zn   Vd   
 <Vd>:name of the destination SIMD&FP register, encoded in the "Vd" field.
 <T>
 size | <T>
 00 | 16B
 01 | 8H
 10 | 4S
 11 | 2D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | B
 01 | H
 10 | S
 11 | D

ands - bitwise and predicates, setting the condition flags - Bitwise AND active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
001001010100....01....0....0....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

andv - bitwise and reduction to scalar - Bitwise AND horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register.  Inactive elements in the source vector are treated as all ones.
00000100..011010001.............
        ze    pc   Pg Zn   Vd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

asr (immediate, predicated) - arithmetic shift right by immediate (predicated) - Shift right by immediate, preserving the sign bit, each active element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. Inactive elements in the destination vector register remain unmodified.
00000100..000000100.............
        zh  pcLU   Pg zlmm3Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

asr (immediate, unpredicated) - arithmetic shift right by immediate (unpredicated) - Shift right by immediate, preserving the sign bit, each element of the source vector, and place the results in the corresponding elements of the destination vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
00000100..1.....100100..........
        zh zlmm3     UZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

asr (vectors) - arithmetic shift right by vector (predicated) - Shift right, preserving the sign bit, active elements of the first source vector by corresponding elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount operand is a vector of unsigned elements in which all bits are significant, and not used modulo the element size. Inactive elements in the destination vector register remain unmodified.
00000100..010000100.............
        ze   RLU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

asr (wide elements, predicated) - arithmetic shift right by 64-bit wide elements (predicated) - Shift right, preserving the sign bit, active elements of the first source vector by corresponding overlapping 64-bit elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount is a vector of unsigned 64-bit doubleword elements in which all bits are significant, and not used modulo the destination element size. Inactive elements in the destination vector register remain unmodified.
00000100..011000100.............
        ze   RLU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | RESERVED
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

asr (wide elements, unpredicated) - arithmetic shift right by 64-bit wide elements (unpredicated) - Shift right, preserving the sign bit, all elements of the first source vector by corresponding overlapping 64-bit elements of the second source vector and place the first in the corresponding elements of the destination vector. The shift amount is a vector of unsigned 64-bit doubleword elements in which all bits are significant, and not used modulo the destination element size. is unpredicated.
00000100..1.....100000..........
        ze Zm        UZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | RESERVED
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

asrd - arithmetic shift right for divide by immediate (predicated) - Shift right by immediate, preserving the sign bit, each active element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The result rounds toward zero as in a signed division. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. Inactive elements in the destination vector register remain unmodified.
00000100..000100100.............
        zh  pcLU   Pg zlmm3Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

asrr - reversed arithmetic shift right by vector (predicated) - Reversed shift right, preserving the sign bit, active elements of the second source vector by corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount operand is a vector of unsigned elements in which all bits are significant, and not used modulo the element size.  Inactive elements in the destination vector register remain unmodified.
00000100..010100100.............
        ze   RLU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bcax - bitwise clear and exclusive-or - Bitwise AND elements of the second source vector with the corresponding inverted elements of the third source vector, then exclusive-OR the results with corresponding elements of the first source vector. The final results are destructively placed in the corresponding elements of the destination and first source vector. is unpredicated.
00000100011.....001110..........
        pc Zm        2Zk   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Zk>:name of the third source scalable vector register, encoded in the "Zk" field.

bdep - scatter lower bits into positions selected by bitmask - scatters the lowest-numbered contiguous bits within each element of the first source vector to the bit positions indicated by non-zero bits in the corresponding mask element of the second source vector, preserving their order, and set the bits corresponding to a zero mask bit to zero. is unpredicated. ID_AA64ZFR0_EL1.BitPerm indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled, or FEAT_SSVE_BitPerm is implemented.
01000101..0.....101101..........
        ze Zm       pcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bext - gather lower bits from positions selected by bitmask - gathers bits in each element of the first source vector from the bit positions indicated by non-zero bits in the corresponding mask element of the second source vector to the lowest-numbered contiguous bits of the corresponding destination element, preserving their order, and sets the remaining higher-numbered bits to zero. is unpredicated. ID_AA64ZFR0_EL1.BitPerm indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled, or FEAT_SSVE_BitPerm is implemented.
01000101..0.....101100..........
        ze Zm       pcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bf1cvt, bf2cvt - 8-bit floating-point convert to bfloat16 - Convert each even-numbered 8-bit floating-point element of the source vector to BFloat16 while downscaling the value, and place the results in the overlapping 16-bit elements of the destination vector. BF1CVT scales the values by 2-UInt(FPMR.LSCALE[5:0]). BF2CVT scales the values by 2-UInt(FPMR.LSCALE2[5:0]). The 8-bit floating-point encoding format for BF1CVT is selected by FPMR.F8S1. The 8-bit floating-point encoding format for BF2CVT is selected by FPMR.F8S2. is unpredicated.
0110010100001000001110..........
               L    pcZn   Zd   
0110010100001000001111..........
               L    pcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

bf1cvtlt, bf2cvtlt - 8-bit floating-point convert to bfloat16 (top) - Convert each odd-numbered 8-bit floating-point element of the source vector to BFloat16 while downscaling the value, and place the results in the overlapping 16-bit elements of the destination vector. BF1CVTLT scales the values by 2-UInt(FPMR.LSCALE[5:0]). BF2CVTLT scales the values by 2-UInt(FPMR.LSCALE2[5:0]). The 8-bit floating-point encoding format for BF1CVTLT is selected by FPMR.F8S1. The 8-bit floating-point encoding format for BF2CVTLT is selected by FPMR.F8S2. is unpredicated.
0110010100001001001110..........
               L    pcZn   Zd   
0110010100001001001111..........
               L    pcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

bfadd (predicated) - bfloat16 floating-point add vectors (predicated) - Add active BFloat16 elements of the second source vector to corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified. follows SVE2 non-widening BFloat16 numerical behaviors. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
0110010100000000100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfadd (unpredicated) - bfloat16 floating-point add vectors (unpredicated) - Add all BFloat16 elements of the second source vector to corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. follows SVE2 non-widening BFloat16 numerical behaviors. is unpredicated. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
01100101000.....000000..........
        ze Zm      opcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfclamp - bfloat16 floating-point clamp to minimum/maximum number - Clamp each BFloat16 element in the destination vector to between the BFloat16 minimum value in the corresponding element of the first source vector and the BFloat16 maximum value in the corresponding element of the second source vector and destructively place the clamped results in the corresponding elements of the destination vector. Regardless of the value of FPCR.AH, the behavior is as follows for each minimum number and maximum number operation: follows SVE2 non-widening BFloat16 numerical behaviors. is unpredicated. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
01100100001.....001001..........
        ze Zm         Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfcvt - floating-point down convert to bfloat16 format (predicated) - Convert to BFloat16 from single-precision in each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. Since the result type is smaller than the input type, the results are zero-extended to fill each destination element. ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.
0110010110001010101.............
        pc    c2   Pg Zn   Zd   
0110010010011010110.............
        pc       c2Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

bfcvtn - bfloat16 convert, narrow and interleave to 8-bit floating-point - Convert each BFloat16 element of the group of two source vectors to 8-bit floating-point while scaling the value by 2SInt(FPMR.NSCALE), and place the two-way interleaved results in the corresponding 8-bit elements of the destination vector. The 8-bit floating-point encoding format is selected by FPMR.F8D. is unpredicated.
0110010100001010001110....0.....
                    pcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn1>:name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.
 <Zn2>:name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.

bfcvtnt - floating-point down convert and narrow to bfloat16 (top, predicated) - Convert to BFloat16 from single-precision in each active floating-point element of the source vector, and place the results in the odd-numbered 16-bit elements of the destination vector, leaving the even-numbered elements unchanged.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.
0110010010001010101.............
        pc    c2   Pg Zn   Zd   
0110010010000010101.............
        pc    c2   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

bfdot (indexed) - bfloat16 floating-point indexed dot product - delimits the source vectors into pairs of BFloat16 elements. The BFloat16 pairs within the second source vector are specified using an immediate index which selects the same BFloat16 pair position within each 128-bit vector segment.  The index range is from 0 to 3. If FEAT_EBF16 is not implemented or FPCR.EBF is 0, this instruction: If FEAT_EBF16 is implemented and FPCR.EBF is 1, then this instruction: Irrespective of FEAT_EBF16 and FPCR.EBF, this instruction: is unpredicated. ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.
01100100011.....010000..........
         p i2Zm     c2Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index of a group of two 16-bit elements within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.

bfdot (vectors) - bfloat16 floating-point dot product - delimits the source vectors into pairs of BFloat16 elements.  If FEAT_EBF16 is not implemented or FPCR.EBF is 0, this instruction: If FEAT_EBF16 is implemented and FPCR.EBF is 1, then this instruction: Irrespective of FEAT_EBF16 and FPCR.EBF, this instruction: is unpredicated. ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.
01100100011.....100000..........
         p Zm        2Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfmax - bfloat16 floating-point maximum (predicated) - Determine the maximum of active BFloat16 elements of the second source vector and corresponding BFloat16 elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows: Inactive elements in the destination vector register remain unmodified. follows SVE2 non-widening BFloat16 numerical behaviors. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
0110010100000110100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfmaxnm - bfloat16 floating-point maximum number (predicated) - Determine the maximum number value of active BFloat16 elements of the second source vector and corresponding BFloat16 elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Regardless of the value of FPCR.AH, the behavior is as follows: Inactive elements in the destination vector register remain unmodified. follows SVE2 non-widening BFloat16 numerical behaviors. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
0110010100000100100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfmin - bfloat16 floating-point minimum (predicated) - Determine the minimum of active BFloat16 elements of the second source vector and corresponding BFloat16 elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows: Inactive elements in the destination vector register remain unmodified. follows SVE2 non-widening BFloat16 numerical behaviors. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
0110010100000111100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfminnm - bfloat16 floating-point minimum number (predicated) - Determine the minimum number value of active BFloat16 elements of the second source vector and corresponding BFloat16 elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Regardless of the value of FPCR.AH, the behavior is as follows: Inactive elements in the destination vector register remain unmodified. follows SVE2 non-widening BFloat16 numerical behaviors. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
0110010100000101100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfmla (indexed) - bfloat16 floating-point fused multiply-add vectors by indexed elements - Multiply all BFloat16 elements within each 128-bit segment of the first source vector by the specified element in the corresponding second source vector segment. The products are then destructively added without intermediate rounding to the corresponding elements of the addend and destination vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment. The index range is from 0 to 7. follows SVE2 non-widening BFloat16 numerical behaviors. is unpredicated. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
011001000.1.....000010..........
         h 3lZm     2pZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

bfmla (vectors) - bfloat16 floating-point fused multiply-add vectors - Multiply the corresponding active BFloat16 elements of the first and second source vectors and add to elements of the third source (addend) vector without intermediate rounding. Destructively place the results in the destination and third source (addend) vector. Inactive elements in the destination vector register remain unmodified. follows SVE2 non-widening BFloat16 numerical behaviors. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
01100101001.....000.............
        ze Zm     pPg Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfmlalb (indexed) - bfloat16 floating-point multiply-add long to single-precision (bottom, indexed) - This BFloat16 floating-point multiply-add long instruction widens the even-numbered BFloat16 elements in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to single-precision format and then destructively multiplies and adds these values without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding BFloat16 elements in the first source vector. is unpredicated. ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.
01100100111.....0100.0..........
         2 3hZm   p lTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

bfmlalb (vectors) - bfloat16 floating-point multiply-add long to single-precision (bottom) - This BFloat16 floating-point multiply-add long instruction widens the even-numbered BFloat16 elements in the first source vector and the corresponding elements in the second source vector to single-precision format and then destructively multiplies and adds these values without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding BFloat16 elements in the source vectors. is unpredicated. ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.
01100100111.....100000..........
         2 Zm     p  TZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfmlalt (indexed) - bfloat16 floating-point multiply-add long to single-precision (top, indexed) - This BFloat16 floating-point multiply-add long instruction widens the odd-numbered BFloat16 elements in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to single-precision format and then destructively multiplies and adds these values without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding BFloat16 elements in the first source vector. is unpredicated. ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.
01100100111.....0100.1..........
         2 3hZm   p lTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

bfmlalt (vectors) - bfloat16 floating-point multiply-add long to single-precision (top) - This BFloat16 floating-point multiply-add long instruction widens the odd-numbered BFloat16 elements in the first source vector and the corresponding elements in the second source vector to single-precision format and then destructively multiplies and adds these values without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding BFloat16 elements in the source vectors. is unpredicated. ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.
01100100111.....100001..........
         2 Zm     p  TZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfmls (indexed) - bfloat16 floating-point fused multiply-subtract vectors by indexed elements - Multiply all BFloat16 elements within each 128-bit segment of the first source vector by the specified element in the corresponding second source vector segment. The products are then destructively subtracted without intermediate rounding from the corresponding elements of the addend and destination vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment. The index range is from 0 to 7. follows SVE2 non-widening BFloat16 numerical behaviors. is unpredicated. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
011001000.1.....000011..........
         h 3lZm     2pZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

bfmls (vectors) - bfloat16 floating-point fused multiply-subtract vectors - Multiply the corresponding active BFloat16 elements of the first and second source vectors and subtract from elements of the third source (addend) vector without intermediate rounding. Destructively place the results in the destination and third source (addend) vector. Inactive elements in the destination vector register remain unmodified. follows SVE2 non-widening BFloat16 numerical behaviors. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
01100101001.....001.............
        ze Zm     pPg Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfmlslb (indexed) - bfloat16 floating-point multiply-subtract long from single-precision (bottom, indexed) - This BFloat16 floating-point multiply-subtract long instruction widens the even-numbered BFloat16 elements in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to single-precision format and then destructively multiplies and subtracts these values without intermediate rounding from the single-precision elements of the destination vector that overlap with the corresponding BFloat16 elements in the first source vector. is unpredicated.
01100100111.....0110.0..........
         2 3hZm   p lTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

bfmlslb (vectors) - bfloat16 floating-point multiply-subtract long from single-precision (bottom) - This BFloat16 floating-point multiply-subtract long instruction widens the even-numbered BFloat16 elements in the first source vector and the corresponding elements in the second source vector to single-precision format and then destructively multiplies and subtracts these values without intermediate rounding from the single-precision elements of the destination vector that overlap with the corresponding BFloat16 elements in the source vectors. is unpredicated.
01100100111.....101000..........
         2 Zm     p  TZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfmlslt (indexed) - bfloat16 floating-point multiply-subtract long from single-precision (top, indexed) - This BFloat16 floating-point multiply-subtract long instruction widens the odd-numbered BFloat16 elements in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to single-precision format and then destructively multiplies and subtracts these values without intermediate rounding from the single-precision elements of the destination vector that overlap with the corresponding BFloat16 elements in the first source vector. is unpredicated.
01100100111.....0110.1..........
         2 3hZm   p lTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

bfmlslt (vectors) - bfloat16 floating-point multiply-subtract long from single-precision (top) - This BFloat16 floating-point multiply-subtract long instruction widens the odd-numbered BFloat16 elements in the first source vector and the corresponding elements in the second source vector to single-precision format and then destructively multiplies and subtracts these values without intermediate rounding from the single-precision elements of the destination vector that overlap with the corresponding BFloat16 elements in the source vectors. is unpredicated.
01100100111.....101001..........
         2 Zm     p  TZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfmmla - bfloat16 floating-point matrix multiply-accumulate into 2×2 matrices - If FEAT_EBF16 is not implemented or FPCR.EBF is 0, this instruction: If FEAT_EBF16 is implemented and FPCR.EBF is 1, then this instruction: Irrespective of FEAT_EBF16 and FPCR.EBF, this instruction: is unpredicated and vector length agnostic. ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01100100011.....111001..........
        pc Zm         Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfmul (indexed) - bfloat16 floating-point multiply vectors by indexed elements - Multiply all BFloat16 elements within each 128-bit segment of the first source vector by the specified element in the corresponding second source vector segment and place the results in the corresponding elements of the destination vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment. The index range is from 0 to 7. follows SVE2 non-widening BFloat16 numerical behaviors. is unpredicated. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
011001000.1.....001010..........
         h 3lZm     2 Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

bfmul (vectors, predicated) - bfloat16 floating-point multiply vectors (predicated) - Multiply active BFloat16 elements of the second source vector to corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified. follows SVE2 non-widening BFloat16 numerical behaviors. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
0110010100000010100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfmul (vectors, unpredicated) - bfloat16 floating-point multiply vectors (unpredicated) - Multiply all BFloat16 elements of the second source vector to corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. follows SVE2 non-widening BFloat16 numerical behaviors. is unpredicated. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
01100101000.....000010..........
        ze Zm      opcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfscale - bfloat16 adjust exponent by vector (predicated) - Multiply the active BFloat16 elements of the first source vector by 2.0 to the power of the signed integer values in the corresponding elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified. follows SVE2 non-widening BFloat16 numerical behaviors.
0110010100001001100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfsub (predicated) - bfloat16 floating-point subtract vectors (predicated) - Subtract active BFloat16 elements of the second source vector from corresponding BFloat16 elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified. follows SVE2 non-widening BFloat16 numerical behaviors. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
0110010100000001100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bfsub (unpredicated) - bfloat16 floating-point subtract vectors (unpredicated) - Subtract all BFloat16 elements of the second source vector from corresponding BFloat16 elements of the first source vector and place the results in the corresponding elements of the destination vector. follows SVE2 non-widening BFloat16 numerical behaviors. is unpredicated. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
01100101000.....000001..........
        ze Zm      opcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bgrp - group bits to right or left as selected by bitmask - separates bits in each element of the first source vector by gathering from the bit positions indicated by non-zero bits in the corresponding mask element of the second source vector to the lowest-numbered contiguous bits of the corresponding destination element, and from positions indicated by zero bits to the highest-numbered bits of the destination element, preserving the bit order within each group. is unpredicated. ID_AA64ZFR0_EL1.BitPerm indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled, or FEAT_SSVE_BitPerm is implemented.
01000101..0.....101110..........
        ze Zm       pcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bic (immediate) - bitwise clear bits using immediate (unpredicated) - Bitwise clear bits using immediate with each 64-bit element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits. is unpredicated.
00000101100000..................
        pc    imm13        Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 imm13 | <T>
 0xxxxxx0xxxxx | S
 0xxxxxx10xxxx | H
 0xxxxxx110xxx | B
 0xxxxxx1110xx | B
 0xxxxxx11110x | B
 0xxxxxx11111x | RESERVED
 1xxxxxxxxxxxx | D
 <const>:Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.

bic (predicates) - bitwise clear predicates - Bitwise AND inverted active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
001001010000....01....0....1....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

bic (vectors, predicated) - bitwise clear vectors (predicated) - Bitwise AND inverted active elements of the second source vector with corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..011011000.............
        ze   opc   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bic (vectors, unpredicated) - bitwise clear vectors (unpredicated) - Bitwise AND inverted all elements of the second source vector with corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. is unpredicated.
00000100111.....001100..........
        pc Zm         Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

bics - bitwise clear predicates, setting the condition flags - Bitwise AND inverted active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
001001010100....01....0....1....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

brka - break after first true condition - Sets destination predicate elements up to and including the first active and true source element to true, then sets subsequent elements to false. Inactive elements in the destination predicate register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. Does not set the condition flags.
001001010001000001....0.........
        BS        Pg   Pn  MPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <ZM>
 M | <ZM>
 0 | Z
 1 | M
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.

brkas - break after first true condition, setting the condition flags - Sets destination predicate elements up to and including the first active and true source element to true, then sets subsequent elements to false. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
001001010101000001....0....0....
        BS        Pg   Pn  MPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.

brkb - break before first true condition - Sets destination predicate elements up to but not including the first active and true source element to true, then sets subsequent elements to false. Inactive elements in the destination predicate register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. Does not set the condition flags.
001001011001000001....0.........
        BS        Pg   Pn  MPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <ZM>
 M | <ZM>
 0 | Z
 1 | M
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.

brkbs - break before first true condition, setting the condition flags - Sets destination predicate elements up to but not including the first active and true source element to true, then sets subsequent elements to false. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
001001011101000001....0....0....
        BS        Pg   Pn  MPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.

brkn - propagate break to next partition - If the last active element of the first source predicate is false then set the destination predicate to all-false. Otherwise leaves the destination and second source predicate unchanged. Does not set the condition flags.
001001010001100001....0....0....
         S        Pg   Pn   Pdm 
 <Pdm>:name of the second source and destination scalable predicate register, encoded in the "Pdm" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.

brkns - propagate break to next partition, setting the condition flags - If the last active element of the first source predicate is false then set the destination predicate to all-false. Otherwise leaves the destination and second source predicate unchanged. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
001001010101100001....0....0....
         S        Pg   Pn   Pdm 
 <Pdm>:name of the second source and destination scalable predicate register, encoded in the "Pdm" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.

brkpa - break after first true condition, propagating from previous partition - If the last active element of the first source predicate is false then set the destination predicate to all-false. Otherwise sets destination predicate elements up to and including the first active and true source element to true, then sets subsequent elements to false. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
001001010000....11....0....0....
        pS  Pm    Pg   Pn  BPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

brkpas - break after first true condition, propagating from previous partition and setting the condition flags - If the last active element of the first source predicate is false then set the destination predicate to all-false. Otherwise sets destination predicate elements up to and including the first active and true source element to true, then sets subsequent elements to false. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
001001010100....11....0....0....
        pS  Pm    Pg   Pn  BPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

brkpb - break before first true condition, propagating from previous partition - If the last active element of the first source predicate is false then set the destination predicate to all-false. Otherwise sets destination predicate elements up to but not including the first active and true source element to true, then sets subsequent elements to false. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
001001010000....11....0....1....
        pS  Pm    Pg   Pn  BPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

brkpbs - break before first true condition, propagating from previous partition and setting the condition flags - If the last active element of the first source predicate is false then set the destination predicate to all-false. Otherwise sets destination predicate elements up to but not including the first active and true source element to true, then sets subsequent elements to false. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
001001010100....11....0....1....
        pS  Pm    Pg   Pn  BPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

bsl - bitwise select - Selects bits from the  first source vector where the corresponding bit in the third source vector is '1', and from the  second source vector where the corresponding bit in the third source vector is '0'. The  result is placed destructively in the destination and first source vector. is unpredicated.
00000100001.....001111..........
        pc Zm        2Zk   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Zk>:name of the third source scalable vector register, encoded in the "Zk" field.

bsl1n - bitwise select with first input inverted - Selects bits from the inverted first source vector where the corresponding bit in the third source vector is '1', and from the  second source vector where the corresponding bit in the third source vector is '0'. The  result is placed destructively in the destination and first source vector. is unpredicated.
00000100011.....001111..........
        pc Zm        2Zk   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Zk>:name of the third source scalable vector register, encoded in the "Zk" field.

bsl2n - bitwise select with second input inverted - Selects bits from the  first source vector where the corresponding bit in the third source vector is '1', and from the inverted second source vector where the corresponding bit in the third source vector is '0'. The  result is placed destructively in the destination and first source vector. is unpredicated.
00000100101.....001111..........
        pc Zm        2Zk   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Zk>:name of the third source scalable vector register, encoded in the "Zk" field.

cadd - complex integer add with rotate - Add the real and imaginary components of the integral complex numbers from the first source vector to the complex numbers from the second source vector which have first been rotated by 90 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation, equivalent to multiplying the complex numbers in the second source vector by ±j beforehand. Destructively place the results in the corresponding elements of the first source vector. is unpredicated. Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.
01000101..00000011011...........
        ze     p     tZm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <const>
 rot | <const>
 0 | #90
 1 | #270

cdot (indexed) - complex integer dot product (indexed) - The complex integer dot product instructions delimit the source vectors into pairs of 8-bit or 16-bit signed integer complex numbers. Within each pair, the complex numbers in the first source vector are multiplied by the corresponding complex numbers in the second source vector and the resulting wide real or wide imaginary part of the product is accumulated into a 32-bit or 64-bit destination vector element which overlaps all four of the elements that comprise a pair of complex number values in the first source vector. As a result each instruction implicitly deinterleaves the real and imaginary components of their complex number inputs, so that the destination vector accumulates 4×wide real sums or 4×wide imaginary sums. The complex numbers in the second source vector are rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation, by performing the following transformations prior to the dot product operations: The indexed form of these instructions select a single pair of complex numbers within each 128-bit segment of the second source vector as the multiplier for all pairs of complex numbers within the corresponding 128-bit segment of the first source vector. The complex number pairs within the second source vector are specified using an immediate index which selects the same complex number pair position within each 128-bit vector segment.  The index range is from 0 to one less than the number of complex number pairs per                         128-bit segment, encoded in 1 or 2 bits                         depending on the size of the complex number pair. Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.
01000100101.....0100............
        ze i2Zm     otZn   Zda  
01000100111.....0100............
        ze 1Zm      otZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the immediate index of a 32-bit group of four 8-bit values within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "64-bit" variant: is the immediate index of a 64-bit group of four 16-bit values within each 128-bit vector segment, in the range 0 to 1, encoded in the "i1" field.
 <const>
 rot | <const>
 00 | #0
 01 | #90
 10 | #180
 11 | #270

cdot (vectors) - complex integer dot product - The complex integer dot product instructions delimit the source vectors into pairs of 8-bit or 16-bit signed integer complex numbers. Within each pair, the complex numbers in the first source vector are multiplied by the corresponding complex numbers in the second source vector and the resulting wide real or wide imaginary part of the product is accumulated into a 32-bit or 64-bit destination vector element which overlaps all four of the elements that comprise a pair of complex number values in the first source vector. As a result each instruction implicitly deinterleaves the real and imaginary components of their complex number inputs, so that the destination vector accumulates 4×wide real sums or 4×wide imaginary sums. The complex numbers in the second source vector are rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation, by performing the following transformations prior to the dot product operations: Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.
01000100..0.....0001............
        ze Zm       otZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size<0> | <T>
 0 | S
 1 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size<0> | <Tb>
 0 | B
 1 | H
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <const>
 rot | <const>
 00 | #0
 01 | #90
 10 | #180
 11 | #270

clasta (scalar) - conditionally extract element after last to general-purpose register - From the source vector register extract the    element after the last active element, or if the    last active element is the final element extract    element zero,    and then zero-extend that element to destructively    place in the destination and first source general-purpose    register.    If there are no active elements then destructively    zero-extend the least significant element-size bits    of the destination and first source general-purpose register.
00000101..110000101.............
        ze     B   Pg Zm   Rdn  
 <R>
 size | <R>
 00 | W
 01 | W
 10 | W
 11 | X
 <dn>:number [0-30] of the source and destination general-purpose register or the name ZR (31), encoded in the "Rdn" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the source scalable vector register, encoded in the "Zm" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

clasta (simd&fp scalar) - conditionally extract element after last to simd&fp scalar register - From the source vector register extract the    element after the last active element, or if the    last active element is the final element extract    element zero,    and then zero-extend that element to destructively    place in the destination and first source SIMD & floating-point scalar    register.    If there are no active elements then destructively    zero-extend the least significant element-size bits    of the destination and first source SIMD & floating-point scalar register.
00000101..101010100.............
        ze     B   Pg Zm   Vdn  
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <dn>:number [0-31] of the source and destination SIMD&FP register, encoded in the "Vdn" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the source scalable vector register, encoded in the "Zm" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

clasta (vectors) - conditionally extract element after last to vector register - From the second source vector register extract the    element after the last active element, or if the    last active element is the final element extract    element zero, and then replicate that element to    destructively fill the destination and first source    vector. If there are no active elements then leave the    destination and source vector unmodified.
00000101..101000100.............
        ze     B   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

clastb (scalar) - conditionally extract last element to general-purpose register - From the source vector register extract the    last active element,    and then zero-extend that element to destructively    place in the destination and first source general-purpose    register.    If there are no active elements then destructively    zero-extend the least significant element-size bits    of the destination and first source general-purpose register.
00000101..110001101.............
        ze     B   Pg Zm   Rdn  
 <R>
 size | <R>
 00 | W
 01 | W
 10 | W
 11 | X
 <dn>:number [0-30] of the source and destination general-purpose register or the name ZR (31), encoded in the "Rdn" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the source scalable vector register, encoded in the "Zm" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

clastb (simd&fp scalar) - conditionally extract last element to simd&fp scalar register - From the source vector register extract the    last active element,    and then zero-extend that element to destructively    place in the destination and first source SIMD & floating-point scalar    register.    If there are no active elements then destructively    zero-extend the least significant element-size bits    of the destination and first source SIMD & floating-point scalar register.
00000101..101011100.............
        ze     B   Pg Zm   Vdn  
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <dn>:number [0-31] of the source and destination SIMD&FP register, encoded in the "Vdn" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the source scalable vector register, encoded in the "Zm" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

clastb (vectors) - conditionally extract last element to vector register - From the second source vector register extract the    last active element, and then replicate that element to    destructively fill the destination and first source    vector. If there are no active elements then leave the    destination and source vector unmodified.
00000101..101001100.............
        ze     B   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

cls - count leading sign bits (predicated) - Count the number of consecutive sign bits, starting from the most significant bit in each active element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
00000100..011000101.............
        ze M opc   Pg Zn   Zd   
00000100..001000101.............
        ze M opc   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

clz - count leading zero bits (predicated) - Count the number of consecutive binary zero bits, starting from the most significant bit in each active element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
00000100..011001101.............
        ze M opc   Pg Zn   Zd   
00000100..001001101.............
        ze M opc   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

cmla (indexed) - complex integer multiply-add with rotate (indexed) - Multiply  the duplicated real components for rotations 0 and 180, or imaginary components for rotations 90 and 270, of the integral numbers in each 128-bit segment of the first source vector by the specified complex number in the corresponding the second source vector segment rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation. Then  add the products to the corresponding components of the complex numbers in the addend vector.  Destructively place  the results in the corresponding elements of the addend vector.   is unpredicated. These transformations permit the creation of a variety of multiply-add and multiply-subtract operations on complex numbers by combining two of these instructions with the same vector operands but with rotations that are 90 degrees apart. Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.
01000100101.....0110............
        ze i2Zm     otZn   Zda  
01000100111.....0110............
        ze 1Zm      otZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "16-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "16-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field.
 <const>
 rot | <const>
 00 | #0
 01 | #90
 10 | #180
 11 | #270

cmla (vectors) - complex integer multiply-add with rotate - Multiply  the duplicated real components for rotations 0 and 180, or imaginary components for rotations 90 and 270, of the integral numbers in  the first source vector by the corresponding complex number in the second source vector  rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation. Then  add the products to the corresponding components of the complex numbers in the addend vector.  Destructively place  the results in the corresponding elements of the addend vector.   is unpredicated. These transformations permit the creation of a variety of multiply-add and multiply-subtract operations on complex numbers by combining two of these instructions with the same vector operands but with rotations that are 90 degrees apart. Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.
01000100..0.....0010............
        ze Zm      potZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <const>
 rot | <const>
 00 | #0
 01 | #90
 10 | #180
 11 | #270

cmp<cc> (immediate) - compare vector to immediate - Compare active integer elements in the  source vector with an immediate, and place the boolean results of the specified comparison in the corresponding elements of the destination predicate.  Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..0.....100........0....
        ze imm5 p 2Pg Zn   ePd  
00100101..0.....000........1....
        ze imm5 p tPg Zn   ePd  
00100101..0.....000........0....
        ze imm5 p tPg Zn   ePd  
00100100..1.......0........1....
        ze imm7   tPg Zn   ePd  
00100100..1.......0........0....
        ze imm7   tPg Zn   ePd  
00100101..0.....001........0....
        ze imm5 p tPg Zn   ePd  
00100101..0.....001........1....
        ze imm5 p tPg Zn   ePd  
00100100..1.......1........0....
        ze imm7   tPg Zn   ePd  
00100100..1.......1........1....
        ze imm7   tPg Zn   ePd  
00100101..0.....100........1....
        ze imm5 p 2Pg Zn   ePd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <imm>:For the "Equal", "Greater than or equal", "Greater than", "Less than or equal", "Less than", and "Not equal" variants: is the signed immediate operand, in the range -16 to 15, encoded in the "imm5" field.
 <imm>:For the "Higher or same", "Higher", "Lower or same", and "Lower" variants: is the unsigned immediate operand, in the range 0 to 127, encoded in the "imm7" field.

cmp<cc> (vectors) - compare vectors - Compare active integer elements in the first source vector with corresponding elements in the second source vector, and place the boolean results of the specified comparison in the corresponding elements of the destination predicate.  Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100100..0.....101........0....
        ze Zm   p 2Pg Zn   ePd  
00100100..0.....100........1....
        ze Zm   p 2Pg Zn   ePd  
00100100..0.....100........0....
        ze Zm   p 2Pg Zn   ePd  
00100100..0.....000........1....
        ze Zm   p 2Pg Zn   ePd  
00100100..0.....000........0....
        ze Zm   p 2Pg Zn   ePd  
00100100..0.....101........1....
        ze Zm   p 2Pg Zn   ePd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

cmp<cc> (wide elements) - compare vector to 64-bit wide elements - Compare active integer elements in the first source vector with overlapping 64-bit doubleword elements in the second source vector, and place the boolean results of the specified comparison in the corresponding elements of the destination predicate.  Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100100..0.....001........0....
        ze Zm   p 2Pg Zn   ePd  
00100100..0.....010........1....
        ze Zm   U tPg Zn   ePd  
00100100..0.....010........0....
        ze Zm   U tPg Zn   ePd  
00100100..0.....110........1....
        ze Zm   U tPg Zn   ePd  
00100100..0.....110........0....
        ze Zm   U tPg Zn   ePd  
00100100..0.....011........0....
        ze Zm   U tPg Zn   ePd  
00100100..0.....011........1....
        ze Zm   U tPg Zn   ePd  
00100100..0.....111........0....
        ze Zm   U tPg Zn   ePd  
00100100..0.....111........1....
        ze Zm   U tPg Zn   ePd  
00100100..0.....001........1....
        ze Zm   p 2Pg Zn   ePd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | RESERVED
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

cmple (vectors) - compare signed less than or equal to vector, setting the condition flags - Compare active signed integer elements in the first source vector being less than or equal to corresponding signed elements in the second source vector, and place the boolean results of the  comparison in the corresponding elements of the destination predicate.  Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100100..0.....100........0....
        ze Zm   p 2Pg Zn   ePd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.

cmplo (vectors) - compare unsigned lower than vector, setting the condition flags - Compare active unsigned integer elements in the first source vector being lower than corresponding unsigned elements in the second source vector, and place the boolean results of the  comparison in the corresponding elements of the destination predicate.  Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100100..0.....000........1....
        ze Zm   p 2Pg Zn   ePd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.

cmpls (vectors) - compare unsigned lower or same as vector, setting the condition flags - Compare active unsigned integer elements in the first source vector being lower than or same as corresponding unsigned elements in the second source vector, and place the boolean results of the  comparison in the corresponding elements of the destination predicate.  Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100100..0.....000........0....
        ze Zm   p 2Pg Zn   ePd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.

cmplt (vectors) - compare signed less than vector, setting the condition flags - Compare active signed integer elements in the first source vector being less than corresponding signed elements in the second source vector, and place the boolean results of the  comparison in the corresponding elements of the destination predicate.  Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100100..0.....100........1....
        ze Zm   p 2Pg Zn   ePd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.

cnot - logically invert boolean condition in vector (predicated) - Logically invert the boolean value in each active element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. Boolean TRUE is any non-zero value in a source, and one in a result element. Boolean FALSE is always zero.
00000100..011011101.............
        ze M opc   Pg Zn   Zd   
00000100..001011101.............
        ze M opc   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

cnt - count non-zero bits (predicated) - Count non-zero bits in each active element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
00000100..011010101.............
        ze M opc   Pg Zn   Zd   
00000100..001010101.............
        ze M opc   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

cntb, cntd, cnth, cntw - set scalar to multiple of predicate constraint element count - Determines the number of active  elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then places the result in the   scalar destination. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001000010....111000..........
        ze  imm4     ptternRd   
000001001110....111000..........
        ze  imm4     ptternRd   
000001000110....111000..........
        ze  imm4     ptternRd   
000001001010....111000..........
        ze  imm4     ptternRd   
 <Xd>:64-bit name of the destination general-purpose register, encoded in the "Rd" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

cntp (predicate as counter) - set scalar to count from predicate-as-counter - Counts the number of true elements in the source predicate and places the scalar result in the destination general-purpose register.
00100101..10000010000.1.........
        ze   opc     l PNn Rd   
 <Xd>:64-bit name of the destination general-purpose register, encoded in the "Rd" field.
 <PNn>:name of the source scalable predicate register, with predicate-as-counter encoding, encoded in the "PNn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <vl>
 vl | <vl>
 0 | VLx2
 1 | VLx4

cntp (predicate) - set scalar to count of true predicate elements - Counts the number of active and true elements in the source predicate and places the scalar result in the destination general-purpose register. Inactive predicate elements are not counted.
00100101..10000010....0.........
        ze   opc  Pg   Pn  Rd   
 <Xd>:64-bit name of the destination general-purpose register, encoded in the "Rd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

compact - copy active vector elements to lower-numbered elements - In order of increasing element number, pack active elements from the source vector into increasing consecutive elements of the destination vector, setting any remaining elements to zero. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled, or FEAT_SME2p2 is implemented.
000001010.100001100.............
         z         Pg Zn   Zd   
000001011.100001100.............
         z         Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 sz | <T>
 0 | B
 1 | H
 <T>
 sz | <T>
 0 | S
 1 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

cpy (immediate, merging) - copy signed integer immediate to vector elements (merging) - Copy a signed integer immediate to each active element in the destination vector. Inactive elements in the destination vector register remain unmodified. The immediate operand is a signed value in the range -128 to +127, and for element widths of 16 bits or higher it may also be a signed multiple of 256 in the range -32768 to +32512 (excluding 0). The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<simm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".
00000101..01....01..............
        ze  Pg   Mhimm8    Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <imm>:Is a signed immediate in the range -128 to 127, encoded in the "imm8" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #8

cpy (immediate, zeroing) - copy signed integer immediate to vector elements (zeroing) - Copy a signed integer immediate to each active element in the destination vector. Inactive elements in the destination vector register are set to zero. The immediate operand is a signed value in the range -128 to +127, and for element widths of 16 bits or higher it may also be a signed multiple of 256 in the range -32768 to +32512 (excluding 0). The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<simm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".
00000101..01....00..............
        ze  Pg   Mhimm8    Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <imm>:Is a signed immediate in the range -128 to 127, encoded in the "imm8" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #8

cpy (scalar) - copy general-purpose register to vector elements (predicated) - Copy the general-purpose scalar source register to each active element in the destination vector. Inactive elements in the destination vector register remain unmodified.
00000101..101000101.............
        ze         Pg Rn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <R>
 size | <R>
 00 | W
 01 | W
 10 | W
 11 | X
 <n|SP>:number [0-30] of the general-purpose source register or the name SP (31), encoded in the "Rn" field.

cpy (simd&fp scalar) - copy simd&fp scalar register to vector elements (predicated) - Copy the SIMD & floating-point scalar source register to each active element in the destination vector. Inactive elements in the destination vector register remain unmodified.
00000101..100000100.............
        ze         Pg Vn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <n>:number [0-31] of the source SIMD&FP register, encoded in the "Vn" field.

ctermeq, ctermne - compare and terminate loop - Detect termination conditions in serialized vector loops.  Tests whether the comparison between the scalar source operands holds true and if not tests the state of the !Last condition flag (C) which indicates whether the previous flag-setting predicate instruction selected the last element of the vector partition. The Z and C condition flags are preserved by this instruction.  The N and V condition flags are set as a pair to generate one of the following conditions for a subsequent conditional instruction: The scalar source operands are 32-bit or 64-bit general-purpose registers of the same size.
001001011.1.....001000.....00000
        pz Rm         Rn   e    
001001011.1.....001000.....10000
        pz Rm         Rn   e    
 <R>
 sz | <R>
 0 | W
 1 | X
 <n>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field.
 <m>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

decb, decd, dech, decw (scalar) - decrement scalar by multiple of predicate constraint element count - Determines the number of active  elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement the   scalar destination. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001000011....111001..........
        ze  imm4     DtternRdn  
000001001111....111001..........
        ze  imm4     DtternRdn  
000001000111....111001..........
        ze  imm4     DtternRdn  
000001001011....111001..........
        ze  imm4     DtternRdn  
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

decd, dech, decw (vector) - decrement vector by multiple of predicate constraint element count - Determines the number of active  elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement all destination vector elements. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001111....110001..........
        ze  imm4     DtternZdn  
000001000111....110001..........
        ze  imm4     DtternZdn  
000001001011....110001..........
        ze  imm4     DtternZdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

decp (scalar) - decrement scalar by count of true predicate elements - Counts the number of true elements in the source predicate and then uses the result to decrement the   scalar destination.
00100101..1011011000100.........
        ze    pD     c2Pm  Rdn  
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <Pm>:name of the source scalable predicate register, encoded in the "Pm" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

decp (vector) - decrement vector by count of true predicate elements - Counts the number of true elements in the source predicate and then uses the result to decrement all destination vector elements. The predicate size specifier may be omitted in assembler    source code, but this is deprecated and will be    prohibited in a future release of the architecture.
00100101..1011011000000.........
        ze    pD     c2Pm  Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pm>:name of the source scalable predicate register, encoded in the "Pm" field.

dup (immediate) - broadcast signed immediate to vector elements (unpredicated) - Unconditionally broadcast the signed integer immediate into each element of the destination vector. is unpredicated. The immediate operand is a signed value in the range -128 to +127, and for element widths of 16 bits or higher it may also be a signed multiple of 256 in the range -32768 to +32512 (excluding 0). The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<simm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".
00100101..11100011..............
        ze   pc   himm8    Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm>:Is a signed immediate in the range -128 to 127, encoded in the "imm8" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #8

dup (indexed) - broadcast indexed element to vector (unpredicated) - Unconditionally broadcast the indexed source vector element into each element of the destination vector. is unpredicated. The immediate element index is in the range of 0 to 63 (bytes), 31 (halfwords), 15 (words), 7 (doublewords) or 3 (quadwords).  Selecting an element beyond the accessible vector length causes the destination vector to be set to zero.
00000101..1.....001000..........
        m2 tsz        Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tsz | <T>
 00000 | RESERVED
 xxxx1 | B
 xxx10 | H
 xx100 | S
 x1000 | D
 10000 | Q
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <imm>:immediate index, in the range 0 to one less than the number of elements in 512 bits, encoded in "imm2:tsz".

dup (scalar) - broadcast general-purpose register to vector elements (unpredicated) - Unconditionally broadcast the general-purpose scalar source register into each element of the destination vector. is unpredicated.
00000101..100000001110..........
        ze            Rn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <R>
 size | <R>
 00 | W
 01 | W
 10 | W
 11 | X
 <n|SP>:number [0-30] of the general-purpose source register or the name SP (31), encoded in the "Rn" field.

dupm - broadcast logical bitmask immediate to vector (unpredicated) - Unconditionally broadcast the logical bitmask immediate into each element of the destination vector. is unpredicated. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits.
00000101110000..................
              imm13        Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 imm13 | <T>
 0xxxxxx0xxxxx | S
 0xxxxxx10xxxx | H
 0xxxxxx110xxx | B
 0xxxxxx1110xx | B
 0xxxxxx11110x | B
 0xxxxxx11111x | RESERVED
 1xxxxxxxxxxxx | D
 <const>:Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.

dupq - broadcast indexed element within each quadword vector segment (unpredicated) - Unconditionally broadcast the indexed element within each 128-bit source vector segment to all elements of the corresponding destination vector segment. is unpredicated. The immediate element index is in the range of 0 to 15 (bytes), 7 (halfwords), 3 (words) or 1 (doublewords).
00000101001.....001001..........
           1tsz       Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tsz | <T>
 0000 | RESERVED
 xxx1 | B
 xx10 | H
 x100 | S
 1000 | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <imm>:immediate index, in the range 0 to one less than the number of elements in 128 bits, encoded in "i1:tsz".

eon - bitwise exclusive-or with inverted immediate (unpredicated) - Bitwise exclusive-OR an inverted immediate with each 64-bit element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits. is unpredicated.
00000101010000..................
        pc    imm13        Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 imm13 | <T>
 0xxxxxx0xxxxx | S
 0xxxxxx10xxxx | H
 0xxxxxx110xxx | B
 0xxxxxx1110xx | B
 0xxxxxx11110x | B
 0xxxxxx11111x | RESERVED
 1xxxxxxxxxxxx | D
 <const>:Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.

eor (immediate) - bitwise exclusive-or with immediate (unpredicated) - Bitwise exclusive-OR an immediate with each 64-bit element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits. is unpredicated.
00000101010000..................
        pc    imm13        Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 imm13 | <T>
 0xxxxxx0xxxxx | S
 0xxxxxx10xxxx | H
 0xxxxxx110xxx | B
 0xxxxxx1110xx | B
 0xxxxxx11110x | B
 0xxxxxx11111x | RESERVED
 1xxxxxxxxxxxx | D
 <const>:Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.

eor (predicates) - bitwise exclusive-or predicates - Bitwise exclusive-OR active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
001001010000....01....1....0....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

eor (vectors, predicated) - bitwise exclusive-or vectors (predicated) - Bitwise exclusive-OR active elements of the second source vector with corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..011001000.............
        ze   opc   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

eor (vectors, unpredicated) - bitwise exclusive-or vectors (unpredicated) - Bitwise exclusive-OR all elements of the second source vector with corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. is unpredicated.
00000100101.....001100..........
        pc Zm         Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

eor3 - bitwise exclusive-or of three vectors - Bitwise exclusive-OR the corresponding elements of all three source vectors, and destructively place the results in the corresponding elements of the destination and first source vector. is unpredicated.
00000100001.....001110..........
        pc Zm        2Zk   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Zk>:name of the third source scalable vector register, encoded in the "Zk" field.

eorbt - interleaving exclusive-or (bottom, top) - Interleaving exclusive-OR between the even-numbered elements of the first source vector register and the odd-numbered elements of the second source vector register, placing the result in the even-numbered elements of the destination vector, leaving the odd-numbered elements unchanged. is unpredicated.
01000101..0.....100100..........
        ze Zm        bZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

eorqv - bitwise exclusive-or reduction of quadword vector segments - Bitwise exclusive-OR of the same element numbers from each 128-bit source vector segment, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as all zeros.
00000100..011101001.............
        ze    pc   Pg Zn   Vd   
 <Vd>:name of the destination SIMD&FP register, encoded in the "Vd" field.
 <T>
 size | <T>
 00 | 16B
 01 | 8H
 10 | 4S
 11 | 2D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | B
 01 | H
 10 | S
 11 | D

eors - bitwise exclusive-or predicates, setting the condition flags - Bitwise exclusive-OR active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
001001010100....01....1....0....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

eortb - interleaving exclusive-or (top, bottom) - Interleaving exclusive-OR between the odd-numbered elements of the first source vector register and the even-numbered elements of the second source vector register, placing the result in the odd-numbered elements of the destination vector, leaving the even-numbered elements unchanged. is unpredicated.
01000101..0.....100101..........
        ze Zm        bZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

eorv - bitwise exclusive-or reduction to scalar - Bitwise exclusive-OR horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register.  Inactive elements in the source vector are treated as zero.
00000100..011001001.............
        ze    pc   Pg Zn   Vd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

expand - copy lower-numbered vector elements to active elements - In order of increasing element number, unpack consecutive elements from the source vector into increasing active elements of the destination vector, setting any inactive elements to zero. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled, or FEAT_SME2p2 is implemented.
00000101..110001100.............
        ze         Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

ext - extract vector from pair of vectors - Copy the indexed byte up to the last byte of the first source vector to the bottom of the result vector, then fill the remainder of the result starting from the first byte of the second source vector. The result is placed destructively in the destination and first source vector,    or constructively in the destination vector. is unpredicated. An index that is greater than or equal to the vector length in bytes is treated as zero, resulting in the first source vector being copied to the result unchanged.
00000101011.....000.............
           imm8h   m8lZn   Zd   
00000101001.....000.............
           imm8h   m8lZm   Zdn  
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn1>:name of the first scalable vector register of the source multi-vector group, encoded in the "Zn" field.
 <Zn2>:name of the second scalable vector register of the source multi-vector group, encoded in the "Zn" field.
 <imm>:unsigned immediate operand, in the range 0 to 255, encoded in the "imm8h:imm8l" fields.
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

extq - extract vector segment from each pair of quadword vector segments - For each 128-bit vector segment of the result, copy the indexed byte up to and including the last byte of the corresponding first source vector segment to the bottom of the result segment, then fill the remainder of the result segment starting from the first byte of the corresponding second source vector segment. The result segments are destructively placed in the corresponding first source vector segment. is unpredicated.
000001010110....001001..........
            imm4      Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <imm>:unsigned immediate operand, in the range 0 to 15, encoded in the "imm4" field.

f1cvt, f2cvt - 8-bit floating-point convert to half-precision - Convert each even-numbered 8-bit floating-point element of the source vector to half-precision while downscaling the value, and place the results in the overlapping 16-bit elements of the destination vector. F1CVT scales the values by 2-UInt(FPMR.LSCALE[3:0]). F2CVT scales the values by 2-UInt(FPMR.LSCALE2[3:0]). The 8-bit floating-point encoding format for F1CVT is selected by FPMR.F8S1. The 8-bit floating-point encoding format for F2CVT is selected by FPMR.F8S2. is unpredicated.
0110010100001000001100..........
               L    pcZn   Zd   
0110010100001000001101..........
               L    pcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

f1cvtlt, f2cvtlt - 8-bit floating-point convert to half-precision (top) - Convert each odd-numbered 8-bit floating-point element of the source vector to half-precision while downscaling the value, and place the results in the overlapping 16-bit elements of the destination vector. F1CVTLT scales the values by 2-UInt(FPMR.LSCALE[3:0]). F2CVTLT scales the values by 2-UInt(FPMR.LSCALE2[3:0]). The 8-bit floating-point encoding format for F1CVTLT is selected by FPMR.F8S1. The 8-bit floating-point encoding format for F2CVTLT is selected by FPMR.F8S2. is unpredicated.
0110010100001001001100..........
               L    pcZn   Zd   
0110010100001001001101..........
               L    pcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

fabd - floating-point absolute difference (predicated) - Compute the absolute difference of active floating-point elements of the second source vector and corresponding floating-point elements of the first source vector and destructively place the result in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01100101..001000100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fabs - floating-point absolute value (predicated) - Take the absolute value of each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. This clears the sign bit and cannot signal a floating-point exception.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
00000100..011100101.............
        ze M opc   Pg Zn   Zd   
00000100..001100101.............
        ze M opc   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

fac<cc> - floating-point absolute compare vectors - Compare active absolute values of floating-point elements in the first source vector with corresponding absolute values of elements in the second source vector, and place the boolean results of the specified comparison in the corresponding elements of the destination predicate.  Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
01100101..0.....111........1....
        ze Zm   p 2Pg Zn   3Pd  
01100101..0.....110........1....
        ze Zm   p 2Pg Zn   3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

facle - floating-point absolute compare less than or equal - Compare active absolute values of floating-point elements in the first source vector being less than or equal to corresponding absolute values of elements in the second source vector, and place the boolean results of the  comparison in the corresponding elements of the destination predicate.  Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
01100101..0.....110........1....
        ze Zm   p 2Pg Zn   3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.

faclt - floating-point absolute compare less than - Compare active absolute values of floating-point elements in the first source vector being less than corresponding absolute values of elements in the second source vector, and place the boolean results of the  comparison in the corresponding elements of the destination predicate.  Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
01100101..0.....111........1....
        ze Zm   p 2Pg Zn   3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.

fadd (immediate) - floating-point add immediate (predicated) - Add an immediate to each active floating-point element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate may take the value +0.5 or +1.0 only. Inactive elements in the destination vector register remain unmodified.
01100101..011000100...0000......
        ze   opc   Pg     1Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>
 i1 | <const>
 0 | #0.5
 1 | #1.0

fadd (vectors, predicated) - floating-point add vector (predicated) - Add active floating-point elements of the second source vector to corresponding floating-point elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01100101!= 00!= 00000000100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fadd (vectors, unpredicated) - floating-point add vector (unpredicated) - Add all floating-point elements of the second source vector to corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. is unpredicated.
01100101!= 00!= 000.....000000..........
        ze Zm      opcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fadda - floating-point add strictly-ordered reduction, accumulating in scalar - Floating-point add a SIMD&FP scalar source and all active lanes of the vector source and place the result destructively in the SIMD&FP scalar source register. Vector elements are processed strictly in order from low to high, with the scalar source providing the initial value. Inactive elements in the source vector are ignored. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01100101..011000001.............
        ze    pc   Pg Zm   Vdn  
 <V>
 size | <V>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <dn>:number [0-31] of the source and destination SIMD&FP register, encoded in the "Vdn" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the source scalable vector register, encoded in the "Zm" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D

faddp - floating-point add pairwise - Add pairs of adjacent floating-point elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector.
01100100..010000100.............
        ze   opc   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

faddqv - floating-point add recursive reduction of quadword vector segments - Floating-point addition of the same element numbers from each 128-bit source vector segment using a recursive pairwise reduction, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as +0.0.
01100100..010000101.............
        ze   opc   Pg Zn   Vd   
 <Vd>:name of the destination SIMD&FP register, encoded in the "Vd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | 8H
 10 | 4S
 11 | 2D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | H
 10 | S
 11 | D

faddv - floating-point add recursive reduction to scalar - Floating-point add horizontally over all lanes of a vector using a recursive pairwise reduction, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as +0.0.
01100101..000000001.............
        ze   opc   Pg Zn   Vd   
 <V>
 size | <V>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <d>:number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D

famax - floating-point absolute maximum (predicated) - Determine the maximum  absolute value from active floating-point elements of the second source vector and  the corresponding floating-point elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Regardless of the value of FPCR.AH, the behavior is as follows: Inactive elements in the destination vector register remain unmodified.
01100101..001110100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

famin - floating-point absolute minimum (predicated) - Determine the minimum  absolute value from active floating-point elements of the second source vector and  the corresponding floating-point elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Regardless of the value of FPCR.AH, the behavior is as follows: Inactive elements in the destination vector register remain unmodified.
01100101..001111100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fcadd - floating-point complex add with rotate (predicated) - Add the real and imaginary components of the active floating-point complex numbers from the first source vector to the complex numbers from the second source vector which have first been rotated by 90 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation, equivalent to multiplying the complex numbers in the second source vector by ±j beforehand. Destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified. Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.
01100100..00000.100.............
        ze     t   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <const>
 rot | <const>
 0 | #90
 1 | #270

fclamp - floating-point clamp to minimum/maximum number - Clamp each floating-point element in the destination vector to between the floating-point minimum value in the corresponding element of the first source vector and the floating-point maximum value in the corresponding element of the second source vector and destructively place the clamped results in the corresponding elements of the destination vector. Regardless of the value of FPCR.AH, the behavior is as follows for each minimum number and maximum number operation: is unpredicated.
01100100!= 00!= 001.....001001..........
        ze Zm         Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fcm<cc> (vectors) - floating-point compare vectors - Compare active floating-point elements in the first source vector with corresponding elements in the second source vector, and place the boolean results of the specified comparison in the corresponding elements of the destination predicate.  Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
01100101..0.....011........0....
        ze Zm   p hPg Zn   lPd  
01100101..0.....010........1....
        ze Zm   p hPg Zn   lPd  
01100101..0.....010........0....
        ze Zm   p hPg Zn   lPd  
01100101..0.....011........1....
        ze Zm   p hPg Zn   lPd  
01100101..0.....110........0....
        ze Zm   p 2Pg Zn   3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fcm<cc> (zero) - floating-point compare vector with zero - Compare active floating-point elements in the  source vector with zero, and place the boolean results of the specified comparison in the corresponding elements of the destination predicate.  Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
01100101..010010001........0....
        ze    qt   Pg Zn   ePd  
01100101..010000001........1....
        ze    qt   Pg Zn   ePd  
01100101..010000001........0....
        ze    qt   Pg Zn   ePd  
01100101..010001001........0....
        ze    qt   Pg Zn   ePd  
01100101..010001001........1....
        ze    qt   Pg Zn   ePd  
01100101..010011001........0....
        ze    qt   Pg Zn   ePd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

fcmla (indexed) - floating-point complex multiply-add by indexed values with rotate - Multiply the duplicated real components for rotations 0 and 180, or imaginary components for rotations 90 and 270, of the floating-point complex numbers in each 128-bit segment of the first source vector by the specified complex number in the corresponding the second source vector segment rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation. Then destructively add the products to the corresponding components of the complex numbers in the addend and destination vector, without intermediate rounding. These transformations permit the creation of a variety of multiply-add and multiply-subtract operations on complex numbers by combining two of these instructions with the same vector operands but with rotations that are 90 degrees apart. Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element. The complex numbers within the second source vector are specified using an immediate index which selects the same complex number position within each 128-bit vector segment.  The index range is from 0 to one less than the number of complex numbers per                         128-bit segment, encoded in 1 to 2 bits                         depending on the size of the complex number. is unpredicated.
01100100101.....0001............
        ze i2Zm     otZn   Zda  
01100100111.....0001............
        ze 1Zm      otZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "Half-precision" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "Single-precision" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "Half-precision" variant: is the index of a Real and Imaginary pair, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "Single-precision" variant: is the index of a Real and Imaginary pair, in the range 0 to 1, encoded in the "i1" field.
 <const>
 rot | <const>
 00 | #0
 01 | #90
 10 | #180
 11 | #270

fcmla (vectors) - floating-point complex multiply-add with rotate (predicated) - Multiply the duplicated real components for rotations 0 and 180, or imaginary components for rotations 90 and 270, of the floating-point complex numbers in  the first source vector by the corresponding complex number in the second source vector  rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation. Then destructively add the products to the corresponding components of the complex numbers in the addend and destination vector, without intermediate rounding. These transformations permit the creation of a variety of multiply-add and multiply-subtract operations on complex numbers by combining two of these instructions with the same vector operands but with rotations that are 90 degrees apart. Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element. Inactive elements in the destination vector register remain unmodified.
01100100..0.....0...............
        ze Zm    otPg Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <const>
 rot | <const>
 00 | #0
 01 | #90
 10 | #180
 11 | #270

fcmle (vectors) - floating-point compare less than or equal to vector - Compare active floating-point elements in the first source vector being less than or equal to corresponding elements in the second source vector, and place the boolean results of the  comparison in the corresponding elements of the destination predicate.  Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
01100101..0.....010........0....
        ze Zm   p hPg Zn   lPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.

fcmlt (vectors) - floating-point compare less than vector - Compare active floating-point elements in the first source vector being less than corresponding elements in the second source vector, and place the boolean results of the  comparison in the corresponding elements of the destination predicate.  Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
01100101..0.....010........1....
        ze Zm   p hPg Zn   lPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.

fcpy - copy 8-bit floating-point immediate to vector elements (predicated) - Copy a floating-point immediate into each active element in the destination vector. Inactive elements in the destination vector register remain unmodified.
00000101..01....110.............
        ze  Pg     imm8    Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <const>:Is a floating-point immediate value expressible as ±n÷16×2^r, where n and r are integers such that 16 ≤ n ≤ 31 and -3 ≤ r ≤ 4, i.e. a normalized binary floating-point encoding with 1 sign bit, 3-bit exponent, and 4-bit fractional part, encoded in the "imm8" field.

fcvt - floating-point convert precision (predicated) - Convert the size and precision of each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. Since the input and result types have a different size the smaller type is held unpacked in the least significant bits of elements of the larger size. When the input is the smaller type the upper bits of each source element are ignored. When the result is the smaller type the results are zero-extended to fill each destination element.
0110010110001001101.............
        pc    c2   Pg Zn   Zd   
0110010010011010101.............
        pc       c2Pg Zn   Zd   
0110010111001001101.............
        pc    c2   Pg Zn   Zd   
0110010011011010101.............
        pc       c2Pg Zn   Zd   
0110010110001000101.............
        pc    c2   Pg Zn   Zd   
0110010010011010100.............
        pc       c2Pg Zn   Zd   
0110010111001011101.............
        pc    c2   Pg Zn   Zd   
0110010011011010111.............
        pc       c2Pg Zn   Zd   
0110010111001000101.............
        pc    c2   Pg Zn   Zd   
0110010011011010100.............
        pc       c2Pg Zn   Zd   
0110010111001010101.............
        pc    c2   Pg Zn   Zd   
0110010011011010110.............
        pc       c2Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

fcvtlt - floating-point up convert long (top, predicated) - Convert odd-numbered floating-point elements from the source vector to the next higher precision, and place the results in the active overlapping double-width elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
0110010010001001101.............
        pc    c2   Pg Zn   Zd   
0110010010000001101.............
        pc    c2   Pg Zn   Zd   
0110010011001011101.............
        pc    c2   Pg Zn   Zd   
0110010011000011101.............
        pc    c2   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

fcvtn - half-precision convert, narrow and interleave to 8-bit floating-point - Convert each half-precision element of the group of two source vectors to 8-bit floating-point while scaling the value by 2SInt(FPMR.NSCALE[4:0]), and place the two-way interleaved results in the corresponding 8-bit elements of the destination vector. The 8-bit floating-point encoding format is selected by FPMR.F8D. is unpredicated.
0110010100001010001100....0.....
                    pcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn1>:name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.
 <Zn2>:name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.

fcvtnb - single-precision convert, narrow and interleave to 8-bit floating-point (bottom) - Convert each single-precision element of the group of two source vectors to 8-bit floating-point while scaling the value by 2SInt(FPMR.NSCALE), and place the two-way interleaved results in the corresponding even-numbered 8-bit elements of the destination vector, zeroing the odd-numbered elements. The 8-bit floating-point encoding format is selected by FPMR.F8D. is unpredicated.
0110010100001010001101....0.....
                    T Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn1>:name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.
 <Zn2>:name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.

fcvtnt (predicated) - floating-point down convert and narrow (top, predicated) - Convert active floating-point elements from the source vector to the next lower precision, and place the results in the odd-numbered half-width elements of the destination vector, leaving the even-numbered elements unchanged.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
0110010010001000101.............
        pc    c2   Pg Zn   Zd   
0110010010000000101.............
        pc    c2   Pg Zn   Zd   
0110010011001010101.............
        pc    c2   Pg Zn   Zd   
0110010011000010101.............
        pc    c2   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

fcvtnt (unpredicated) - single-precision convert, narrow and interleave to 8-bit floating-point (top) - Convert each single-precision element of the group of two source vectors to 8-bit floating-point while scaling the value by 2SInt(FPMR.NSCALE), and place the two-way interleaved results in the corresponding odd-numbered 8-bit elements of the destination vector, leaving the even-numbered elements unchanged. The 8-bit floating-point encoding format is selected by FPMR.F8D. is unpredicated.
0110010100001010001111....0.....
                    T Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn1>:name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.
 <Zn2>:name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.

fcvtx - floating-point down convert, rounding to odd (predicated) - Convert active double-precision floating-point elements from the source vector to single-precision, rounding to Odd, and place the results in the even-numbered 32-bit elements of the destination vector, while setting the odd-numbered elements to zero.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. Rounding to Odd (aka Von Neumann rounding) permits a two-step conversion from double-precision to half-precision without incurring intermediate rounding errors.
0110010100001010101.............
        pc    c2   Pg Zn   Zd   
0110010000011010110.............
        pc       c2Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

fcvtxnt - floating-point down convert, rounding to odd (top, predicated) - Convert active double-precision floating-point elements from the source vector to single-precision, rounding to Odd, and place the results in the odd-numbered 32-bit elements of the destination vector, leaving the even-numbered elements unchanged.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. Rounding to Odd (aka Von Neumann rounding) permits a two-step conversion from double-precision to half-precision without incurring intermediate rounding errors.
0110010000001010101.............
        pc    c2   Pg Zn   Zd   
0110010000000010101.............
        pc    c2   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

fcvtzs - floating-point convert to signed integer, rounding toward zero (predicated) - Convert to the signed integer nearer to zero from each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. If the input and result types have a different size the smaller type is held unpacked in the least significant bits of elements of the larger size. When the input is the smaller type the upper bits of each source element are ignored. When the result is the smaller type the results are sign-extended to fill each destination element.
0110010101011010101.............
        pc   c2U   Pg Zn   Zd   
0110010001011110110.............
        pc     2 3UPg Zn   Zd   
0110010101011100101.............
        pc   c2U   Pg Zn   Zd   
0110010001011111100.............
        pc     2 3UPg Zn   Zd   
0110010101011110101.............
        pc   c2U   Pg Zn   Zd   
0110010001011111110.............
        pc     2 3UPg Zn   Zd   
0110010110011100101.............
        pc   c2U   Pg Zn   Zd   
0110010010011111100.............
        pc     2 3UPg Zn   Zd   
0110010111011100101.............
        pc   c2U   Pg Zn   Zd   
0110010011011111100.............
        pc     2 3UPg Zn   Zd   
0110010111011000101.............
        pc   c2U   Pg Zn   Zd   
0110010011011110100.............
        pc     2 3UPg Zn   Zd   
0110010111011110101.............
        pc   c2U   Pg Zn   Zd   
0110010011011111110.............
        pc     2 3UPg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

fcvtzu - floating-point convert to unsigned integer, rounding toward zero (predicated) - Convert to the unsigned integer nearer to zero from each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. If the input and result types have a different size the smaller type is held unpacked in the least significant bits of elements of the larger size. When the input is the smaller type the upper bits of each source element are ignored. When the result is the smaller type the results are zero-extended to fill each destination element.
0110010101011011101.............
        pc   c2U   Pg Zn   Zd   
0110010001011110111.............
        pc     2 3UPg Zn   Zd   
0110010101011101101.............
        pc   c2U   Pg Zn   Zd   
0110010001011111101.............
        pc     2 3UPg Zn   Zd   
0110010101011111101.............
        pc   c2U   Pg Zn   Zd   
0110010001011111111.............
        pc     2 3UPg Zn   Zd   
0110010110011101101.............
        pc   c2U   Pg Zn   Zd   
0110010010011111101.............
        pc     2 3UPg Zn   Zd   
0110010111011101101.............
        pc   c2U   Pg Zn   Zd   
0110010011011111101.............
        pc     2 3UPg Zn   Zd   
0110010111011001101.............
        pc   c2U   Pg Zn   Zd   
0110010011011110101.............
        pc     2 3UPg Zn   Zd   
0110010111011111101.............
        pc   c2U   Pg Zn   Zd   
0110010011011111111.............
        pc     2 3UPg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

fdiv - floating-point divide by vector (predicated) - Divide active floating-point elements of the first source vector by corresponding floating-point elements of the second source vector and destructively place the quotient in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01100101..001101100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fdivr - floating-point reversed divide by vector (predicated) - Reversed divide active floating-point elements of the second source vector by corresponding floating-point elements of the first source vector and destructively place the quotient in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01100101..001100100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fdot (2-way, indexed, fp16 to fp32) - half-precision floating-point indexed dot product - computes the fused sum-of-products of a pair of half-precision floating-point values held in each 32-bit element of the first source vector and a pair of half-precision floating-point values in an indexed 32-bit element of the second source vector, without intermediate rounding, and then destructively adds the single-precision sum-of-products to the corresponding single-precision element of the destination vector. The half-precision floating-point pairs within the second source vector are specified using an immediate index which selects the same pair position within each 128-bit vector segment. The index range is from 0 to 3. is unpredicated.
01100100001.....010000..........
         p i2Zm     c2Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index of a group of two 16-bit elements within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.

fdot (2-way, indexed, fp8 to fp16) - 8-bit floating-point indexed dot product to half-precision - computes the fused sum-of-products of a group of two 8-bit floating-point values held in each 16-bit element of the first source vector and a group of two 8-bit floating-point values in an indexed 16-bit element of the second source vector. The half-precision sum-of-products are scaled by 2-UInt(FPMR.LSCALE[3:0]), before being destructively added without intermediate rounding to the corresponding half-precision elements of the destination vector. The 8-bit floating-point groups within the second source vector are specified using an immediate index which selects the same group position within each 128-bit vector segment. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100001.....0100.1..........
         p 3hZm     l Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index of a group of two 8-bit elements within each 128-bit vector segment, in the range 0 to 7, encoded in the "i3h:i3l" fields.

fdot (2-way, vectors, fp16 to fp32) - half-precision floating-point dot product - computes the fused sum-of-products of a pair of half-precision floating-point values held in each 32-bit element of the first source and second source vectors, without intermediate rounding, and then destructively adds the single-precision sum-of-products to the corresponding single-precision element of the destination vector. is unpredicated.
01100100001.....100000..........
         p Zm        2Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fdot (2-way, vectors, fp8 to fp16) - 8-bit floating-point dot product to half-precision - computes the fused sum-of-products of a group of two 8-bit floating-point values held in each 16-bit element of the first source and second source vectors. The half-precision sum-of-products are scaled by 2-UInt(FPMR.LSCALE[3:0]), before being destructively added without intermediate rounding to the corresponding half-precision elements of the destination vector. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100001.....100001..........
         p Zm        2Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fdot (4-way, indexed) - 8-bit floating-point indexed dot product to single-precision - computes the fused sum-of-products of a group of four 8-bit floating-point values held in each 32-bit element of the first source vector and a group of four 8-bit floating-point values in an indexed 32-bit element of the second source vector. The single-precision sum-of-products are scaled by 2-UInt(FPMR.LSCALE), before being destructively added without intermediate rounding to the corresponding single-precision elements of the destination vector. The 8-bit floating-point groups within the second source vector are specified using an immediate index which selects the same group position within each 128-bit vector segment. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100011.....010001..........
         p i2Zm     c2Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index of a 32-bit group of four 8-bit values within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.

fdot (4-way, vectors) - 8-bit floating-point dot product to single-precision - computes the fused sum-of-products of a group of four 8-bit floating-point values held in each 32-bit element of the first source and second source vectors. The single-precision sum-of-products are scaled by 2-UInt(FPMR.LSCALE), before being destructively added without intermediate rounding to the corresponding single-precision elements of the destination vector. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100011.....100001..........
         p Zm        2Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fdup - broadcast 8-bit floating-point immediate to vector elements (unpredicated) - Unconditionally broadcast the floating-point immediate into each element of the destination vector. is unpredicated.
00100101..111001110.............
        ze   pc   2imm8    Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <const>:Is a floating-point immediate value expressible as ±n÷16×2^r, where n and r are integers such that 16 ≤ n ≤ 31 and -3 ≤ r ≤ 4, i.e. a normalized binary floating-point encoding with 1 sign bit, 3-bit exponent, and 4-bit fractional part, encoded in the "imm8" field.

fexpa - floating-point exponential accelerator - The FEXPA instruction computes an exponentiation acceleration operation on each floating-point element in the source vector, where the result sign is zero, the result exponent field is copied from a set of significant bits of the input fraction, and the result fraction is inserted from a lookup table indexed by the least-significant input fraction bits, and returns each result in the corresponding element of the destination vector. is fully defined by its bit-manipulation semantics, does not generate floating-point exceptions, and does not guarantee NaN propagation. For double-precision variants, the result element exponent is copied from the source element bits<16:6>, and the result fraction is set based on the source element to the rounded value of 252 × (2bits<5:0>/64 - 1). For single-precision variants, the result element exponent is copied from the source element bits<13:6>, and the result fraction is set based on the source element to the rounded value of 223 × (2bits<5:0>/64 - 1). For half-precision variants, the result element exponent is copied from the source element bits<9:5>, and the result fraction is set based on the source element to the rounded value of 210 × (2bits<4:0>/32 - 1). is unpredicated. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled, or FEAT_SME2p2 is implemented.
00000100..100000101110..........
        ze opc        Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

firstp - scalar index of first true predicate element (predicated) - Determines the index of the first active and true element of the source predicate, or minus one if there are no active and true elements, and places the scalar result in the destination general-purpose register.
00100101..10000110....0.........
        ze   opc  Pg   Pn  Rd   
 <Xd>:64-bit name of the destination general-purpose register, encoded in the "Rd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

flogb - floating-point base 2 logarithm as integer - returns the signed integer base 2 logarithm of each floating-point input element |x|  after normalization. This is the unbiased exponent of x used in the representation of the floating-point value, such that, for positive x, x = significand × 2exponent. The integer results are placed in elements of the destination vector which have the same width (esize) as the floating-point input elements: Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
0110010100011..0101.............
        pc   zeU   Pg Zn   Zd   
01100100000111101...............
        pc     2 zePg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

fmad - floating-point fused multiply-add vectors (predicated), writing multiplicand [zdn = za + zdn * zm] - Multiply the corresponding active floating-point elements of the first and second source vectors and add to elements of the third (addend) vector without intermediate rounding. Destructively place the  results in the destination and first source (multiplicand) vector.  Inactive elements in the destination vector register remain unmodified.
01100101..1.....100.............
        ze Za    NpPg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Za>:name of the third source scalable vector register, encoded in the "Za" field.

fmax (immediate) - floating-point maximum with immediate (predicated) - Determine the maximum of an immediate and each active floating-point element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate may take the value +0.0 or +1.0 only. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows: Inactive elements in the destination vector register remain unmodified.
01100101..011110100...0000......
        ze   opc   Pg     1Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>
 i1 | <const>
 0 | #0.0
 1 | #1.0

fmax (vectors) - floating-point maximum (predicated) - Determine the maximum of active floating-point elements of the second source vector and corresponding floating-point elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows: Inactive elements in the destination vector register remain unmodified.
01100101!= 00!= 00000110100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmaxnm (immediate) - floating-point maximum number with immediate (predicated) - Determine the maximum number value of an immediate and each active floating-point element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate may take the value +0.0 or +1.0 only. Regardless of the value of FPCR.AH, the behavior is as follows: Inactive elements in the destination vector register remain unmodified.
01100101..011100100...0000......
        ze   opc   Pg     1Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>
 i1 | <const>
 0 | #0.0
 1 | #1.0

fmaxnm (vectors) - floating-point maximum number (predicated) - Determine the maximum number value of active floating-point elements of the second source vector and corresponding floating-point elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Regardless of the value of FPCR.AH, the behavior is as follows: Inactive elements in the destination vector register remain unmodified.
01100101!= 00!= 00000100100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmaxnmp - floating-point maximum number pairwise - Compute the maximum value of each pair of adjacent floating-point elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector. Regardless of the value of FPCR.AH, the behavior is as follows for each pairwise operation:
01100100..010100100.............
        ze   opc   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmaxnmqv - floating-point maximum number recursive reduction of quadword vector segments - Floating-point maximum number of the same element numbers from each 128-bit source vector segment using a recursive pairwise reduction, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as the default NaN. Regardless of the value of FPCR.AH, the behavior is as follows:
01100100..010100101.............
        ze   opc   Pg Zn   Vd   
 <Vd>:name of the destination SIMD&FP register, encoded in the "Vd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | 8H
 10 | 4S
 11 | 2D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | H
 10 | S
 11 | D

fmaxnmv - floating-point maximum number recursive reduction to scalar - Floating-point maximum number horizontally over all lanes of a vector using a recursive pairwise reduction, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as the default NaN. Regardless of the value of FPCR.AH, the behavior is as follows:
01100101..000100001.............
        ze   opc   Pg Zn   Vd   
 <V>
 size | <V>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <d>:number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D

fmaxp - floating-point maximum pairwise - Compute the maximum value of each pair of adjacent floating-point elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector. When FPCR.AH is 0, the behavior is as follows for each pairwise operation: When FPCR.AH is 1, the behavior is as follows for each pairwise operation:
01100100..010110100.............
        ze   opc   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmaxqv - floating-point maximum reduction of quadword vector segments - Floating-point maximum of the same element numbers from each 128-bit source vector segment using a recursive pairwise reduction, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as -Infinity. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows:
01100100..010110101.............
        ze   opc   Pg Zn   Vd   
 <Vd>:name of the destination SIMD&FP register, encoded in the "Vd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | 8H
 10 | 4S
 11 | 2D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | H
 10 | S
 11 | D

fmaxv - floating-point maximum recursive reduction to scalar - Floating-point maximum horizontally over all lanes of a vector using a recursive pairwise reduction, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as -Infinity. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows:
01100101..000110001.............
        ze   opc   Pg Zn   Vd   
 <V>
 size | <V>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <d>:number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D

fmin (immediate) - floating-point minimum with immediate (predicated) - Determine the minimum of an immediate and each active floating-point element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate may take the value +0.0 or +1.0 only. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows: Inactive elements in the destination vector register remain unmodified.
01100101..011111100...0000......
        ze   opc   Pg     1Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>
 i1 | <const>
 0 | #0.0
 1 | #1.0

fmin (vectors) - floating-point minimum (predicated) - Determine the minimum of active floating-point elements of the second source vector and corresponding floating-point elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows: Inactive elements in the destination vector register remain unmodified.
01100101!= 00!= 00000111100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fminnm (immediate) - floating-point minimum number with immediate (predicated) - Determine the minimum number value of an immediate and each active floating-point element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate may take the value +0.0 or +1.0 only. Regardless of the value of FPCR.AH, the behavior is as follows: Inactive elements in the destination vector register remain unmodified.
01100101..011101100...0000......
        ze   opc   Pg     1Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>
 i1 | <const>
 0 | #0.0
 1 | #1.0

fminnm (vectors) - floating-point minimum number (predicated) - Determine the minimum number value of active floating-point elements of the second source vector and corresponding floating-point elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Regardless of the value of FPCR.AH, the behavior is as follows: Inactive elements in the destination vector register remain unmodified.
01100101!= 00!= 00000101100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fminnmp - floating-point minimum number pairwise - Compute the minimum value of each pair of adjacent floating-point elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector. Regardless of the value of FPCR.AH, the behavior is as follows for each pairwise operation:
01100100..010101100.............
        ze   opc   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fminnmqv - floating-point minimum number recursive reduction of quadword vector segments - Floating-point minimum number of the same element numbers from each 128-bit source vector segment using a recursive pairwise reduction, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as the default NaN. Regardless of the value of FPCR.AH, the behavior is as follows:
01100100..010101101.............
        ze   opc   Pg Zn   Vd   
 <Vd>:name of the destination SIMD&FP register, encoded in the "Vd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | 8H
 10 | 4S
 11 | 2D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | H
 10 | S
 11 | D

fminnmv - floating-point minimum number recursive reduction to scalar - Floating-point minimum number horizontally over all lanes of a vector using a recursive pairwise reduction, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as the default NaN. Regardless of the value of FPCR.AH, the behavior is as follows:
01100101..000101001.............
        ze   opc   Pg Zn   Vd   
 <V>
 size | <V>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <d>:number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D

fminp - floating-point minimum pairwise - Compute the minimum value of each pair of adjacent floating-point elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector. When FPCR.AH is 0, the behavior is as follows for each pairwise operation: When FPCR.AH is 1, the behavior is as follows for each pairwise operation:
01100100..010111100.............
        ze   opc   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fminqv - floating-point minimum recursive reduction of quadword vector segments - Floating-point minimum of the same element numbers from each 128-bit source vector segment using a recursive pairwise reduction, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as +Infinity. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows:
01100100..010111101.............
        ze   opc   Pg Zn   Vd   
 <Vd>:name of the destination SIMD&FP register, encoded in the "Vd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | 8H
 10 | 4S
 11 | 2D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | H
 10 | S
 11 | D

fminv - floating-point minimum recursive reduction to scalar - Floating-point minimum horizontally over all lanes of a vector using a recursive pairwise reduction, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as +Infinity. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows:
01100101..000111001.............
        ze   opc   Pg Zn   Vd   
 <V>
 size | <V>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <d>:number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D

fmla (indexed) - floating-point fused multiply-add by indexed elements (zda = zda + zn * zm[indexed]) - Multiply all floating-point elements within each 128-bit segment of the first source vector by the specified element in the corresponding second source vector segment.  The products are then destructively added without intermediate rounding to the corresponding elements of the addend and destination vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 1 to 3 bits                         depending on the size of the element. is unpredicated.
011001000.1.....000000..........
         h 3lZm     2pZn   Zda  
01100100101.....000000..........
        ze i2Zm     2pZn   Zda  
01100100111.....000000..........
        ze 1Zm      2pZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "Half-precision" and "Single-precision" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "Double-precision" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "Half-precision" variant: is the immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "Single-precision" variant: is the immediate index, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "Double-precision" variant: is the immediate index, in the range 0 to 1, encoded in the "i1" field.

fmla (vectors) - floating-point fused multiply-add vectors (predicated), writing addend [zda = zda + zn * zm] - Multiply the corresponding active floating-point elements of the first and second source vectors and add to elements of the third source (addend) vector without intermediate rounding.  Destructively place the  results in the destination and third source (addend) vector.  Inactive elements in the destination vector register remain unmodified.
01100101!= 00!= 001.....000.............
        ze Zm    NpPg Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmlalb (indexed, fp16 to fp32) - half-precision floating-point multiply-add long to single-precision (bottom, indexed) - This half-precision floating-point multiply-add long instruction widens the even-numbered half-precision elements in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to single-precision format and then destructively multiplies and adds these values without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding half-precision elements in the first source vector. is unpredicated.
01100100101.....0100.0..........
         2 3hZm   p lTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

fmlalb (indexed, fp8 to fp16) - 8-bit floating-point multiply-add long to half-precision (bottom, indexed) - This 8-bit floating-point multiply-add long instruction widens the even 8-bit elements in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to half-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE[3:0]) before being destructively added without intermediate rounding to the half-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the first source vector. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100001.....0101............
        T  4hZm     4lZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 15, encoded in the "i4h:i4l" fields.

fmlalb (vectors, fp16 to fp32) - half-precision floating-point multiply-add long to single-precision (bottom) - This half-precision floating-point multiply-add long instruction widens the even-numbered half-precision elements in the first source vector and the corresponding elements in the second source vector to single-precision format and then destructively multiplies and adds these values without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding half-precision elements in the source vectors. is unpredicated.
01100100101.....100000..........
         2 Zm     p  TZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmlalb (vectors, fp8 to fp16) - 8-bit floating-point multiply-add long to half-precision (bottom) - This 8-bit floating-point multiply-add long instruction widens the even 8-bit elements in the first and second source vectors to half-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE[3:0]) before being destructively added without intermediate rounding to the half-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the source vectors. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100101.....100010..........
           Zm      T  Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmlallbb (indexed) - 8-bit floating-point multiply-add long long to single-precision (bottom bottom, indexed) - This 8-bit floating-point multiply-add long-long instruction widens the first 8-bit element of each 32-bit container in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE) before being destructively added without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the first source vector. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100001.....1100............
        TT 4hZm     4lZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 15, encoded in the "i4h:i4l" fields.

fmlallbb (vectors) - 8-bit floating-point multiply-add long long to single-precision (bottom bottom) - This 8-bit floating-point multiply-add long-long instruction widens the first 8-bit element of each 32-bit container in the first and second source vectors to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE) before being destructively added without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the source vectors. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100001.....100010..........
           Zm     TT  Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmlallbt (indexed) - 8-bit floating-point multiply-add long long to single-precision (bottom top, indexed) - This 8-bit floating-point multiply-add long-long instruction widens the second 8-bit element of each 32-bit container in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE) before being destructively added without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the first source vector. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100011.....1100............
        TT 4hZm     4lZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 15, encoded in the "i4h:i4l" fields.

fmlallbt (vectors) - 8-bit floating-point multiply-add long long to single-precision (bottom top) - This 8-bit floating-point multiply-add long-long instruction widens the second 8-bit element of each 32-bit container in the first and second source vectors to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE) before being destructively added without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the source vectors. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100001.....100110..........
           Zm     TT  Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmlalltb (indexed) - 8-bit floating-point multiply-add long long to single-precision (top bottom, indexed) - This 8-bit floating-point multiply-add long-long instruction widens the third 8-bit element of each 32-bit container in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE) before being destructively added without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the first source vector. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100101.....1100............
        TT 4hZm     4lZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 15, encoded in the "i4h:i4l" fields.

fmlalltb (vectors) - 8-bit floating-point multiply-add long long to single-precision (top bottom) - This 8-bit floating-point multiply-add long-long instruction widens the third 8-bit element of each 32-bit container in the first and second source vectors to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE) before being destructively added without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the source vectors. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100001.....101010..........
           Zm     TT  Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmlalltt (indexed) - 8-bit floating-point multiply-add long long to single-precision (top top, indexed) - This 8-bit floating-point multiply-add long-long instruction widens the fourth 8-bit element of each 32-bit container in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE) before being destructively added without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the first source vector. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100111.....1100............
        TT 4hZm     4lZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 15, encoded in the "i4h:i4l" fields.

fmlalltt (vectors) - 8-bit floating-point multiply-add long long to single-precision (top top) - This 8-bit floating-point multiply-add long-long instruction widens the fourth 8-bit element of each 32-bit container in the first and second source vectors to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE) before being destructively added without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the source vectors. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100001.....101110..........
           Zm     TT  Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmlalt (indexed, fp16 to fp32) - half-precision floating-point multiply-add long to single-precision (top, indexed) - This half-precision floating-point multiply-add long instruction widens the odd-numbered half-precision elements in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to single-precision format and then destructively multiplies and adds these values without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding half-precision elements in the first source vector. is unpredicated.
01100100101.....0100.1..........
         2 3hZm   p lTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

fmlalt (indexed, fp8 to fp16) - 8-bit floating-point multiply-add long to half-precision (top, indexed) - This 8-bit floating-point multiply-add long instruction widens the odd 8-bit elements in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to half-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE[3:0]) before being destructively added without intermediate rounding to the half-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the first source vector. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100101.....0101............
        T  4hZm     4lZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 15, encoded in the "i4h:i4l" fields.

fmlalt (vectors, fp16 to fp32) - half-precision floating-point multiply-add long to single-precision (top) - This half-precision floating-point multiply-add long instruction widens the odd-numbered half-precision elements in the first source vector and the corresponding elements in the second source vector to single-precision format and then destructively multiplies and adds these values without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding half-precision elements in the source vectors. is unpredicated.
01100100101.....100001..........
         2 Zm     p  TZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmlalt (vectors, fp8 to fp16) - 8-bit floating-point multiply-add long to half-precision (top) - This 8-bit floating-point multiply-add long instruction widens the odd 8-bit elements in the first and second source vectors to half-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE[3:0]) before being destructively added without intermediate rounding to the half-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the source vectors. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated.
01100100101.....100110..........
           Zm      T  Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmls (indexed) - floating-point fused multiply-subtract by indexed elements (zda = zda + -zn * zm[indexed]) - Multiply all floating-point elements within each 128-bit segment of the first source vector by the specified element in the corresponding second source vector segment.  The products are then destructively subtracted without intermediate rounding from the corresponding elements of the addend and destination vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 1 to 3 bits                         depending on the size of the element. is unpredicated.
011001000.1.....000001..........
         h 3lZm     2pZn   Zda  
01100100101.....000001..........
        ze i2Zm     2pZn   Zda  
01100100111.....000001..........
        ze 1Zm      2pZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "Half-precision" and "Single-precision" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "Double-precision" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "Half-precision" variant: is the immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "Single-precision" variant: is the immediate index, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "Double-precision" variant: is the immediate index, in the range 0 to 1, encoded in the "i1" field.

fmls (vectors) - floating-point fused multiply-subtract vectors (predicated), writing addend [zda = zda + -zn * zm] - Multiply the corresponding active floating-point elements of the first and second source vectors and subtract from elements of the third source (addend) vector without intermediate rounding.  Destructively place the  results in the destination and third source (addend) vector.  Inactive elements in the destination vector register remain unmodified.
01100101!= 00!= 001.....001.............
        ze Zm    NpPg Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmlslb (indexed) - half-precision floating-point multiply-subtract long from single-precision (bottom, indexed) - This half-precision floating-point multiply-subtract long instruction widens the even-numbered half-precision elements in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to single-precision format and then destructively multiplies and subtracts these values without intermediate rounding from the single-precision elements of the destination vector that overlap with the corresponding half-precision elements in the first source vector. is unpredicated.
01100100101.....0110.0..........
         2 3hZm   p lTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

fmlslb (vectors) - half-precision floating-point multiply-subtract long from single-precision (bottom) - This half-precision floating-point multiply-subtract long instruction widens the even-numbered half-precision elements in the first source vector and the corresponding elements in the second source vector to single-precision format and then destructively multiplies and subtracts these values without intermediate rounding from the single-precision elements of the destination vector that overlap with the corresponding half-precision elements in the source vectors. is unpredicated.
01100100101.....101000..........
         2 Zm     p  TZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmlslt (indexed) - half-precision floating-point multiply-subtract long from single-precision (top, indexed) - This half-precision floating-point multiply-subtract long instruction widens the odd-numbered half-precision elements in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to single-precision format and then destructively multiplies and subtracts these values without intermediate rounding from the single-precision elements of the destination vector that overlap with the corresponding half-precision elements in the first source vector. is unpredicated.
01100100101.....0110.1..........
         2 3hZm   p lTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

fmlslt (vectors) - half-precision floating-point multiply-subtract long from single-precision (top) - This half-precision floating-point multiply-subtract long instruction widens the odd-numbered half-precision elements in the first source vector and the corresponding elements in the second source vector to single-precision format and then destructively multiplies and subtracts these values without intermediate rounding from the single-precision elements of the destination vector that overlap with the corresponding half-precision elements in the source vectors. is unpredicated.
01100100101.....101001..........
         2 Zm     p  TZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmmla (non-widening) - floating-point matrix multiply-accumulate - The floating-point matrix multiply-accumulate instruction supports single-precision and double-precision data types in a 2×2 matrix contained in segments of 128 or 256 bits, respectively. It multiplies the 2×2 matrix in each segment of the first source vector by the 2×2 matrix in the corresponding segment of the second source vector. The resulting 2×2 matrix product is then destructively added to the matrix accumulator held in the corresponding segment of the addend and destination vector. This is equivalent to performing a 2-way dot product per destination element. is unpredicated. The single-precision variant is vector length agnostic. The double-precision variant requires that the Effective SVE vector length is at least 256 bits. ID_AA64ZFR0_EL1.F32MM indicates whether the single-precision variant is implemented. ID_AA64ZFR0_EL1.F64MM indicates whether the double-precision variant is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01100100101.....111001..........
        pc Zm         Zn   Zda  
01100100111.....111001..........
        pc Zm         Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmmla (widening, fp16 to fp32) - half-precision floating-point matrix multiply-accumulate to single-precision - This half-precision widening matrix multiply-accumulate instruction performs two fused sums-of-products within each two pairs of adjacent half-precision elements while multiplying the 2×4 matrix of half-precision values held in each 128-bit segment of the first source vector by the 4×2 matrix of half-precision values in the corresponding segment of the second source vector. The intermediate sums-of-products are rounded before they are summed, and their intermediate sum is rounded before accumulation into the 2×2 single-precision matrix in the corresponding segment of the destination vector. This is equivalent to performing a 4-way dot product per destination element. is unpredicated. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01100100001.....111001..........
        pc Zm         Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmmla (widening, fp8 to fp16) - 8-bit floating-point matrix multiply-accumulate to half-precision - This 8-bit floating-point widening matrix multiply-accumulate instruction performs the fused sum-of-products within each four adjacent 8-bit elements while multiplying the 2×4 matrix of 8-bit floating-point values held in each 64-bit segment of the first source vector with the 4×2 matrix of 8-bit floating-point values in the corresponding segment of the second source vector. The half-precision sum-of-products are scaled by 2-UInt(FPMR.LSCALE[3:0]), before being destructively added without intermediate rounding to the 2×2 half-precision matrix in the corresponding segment of the destination vector. This is equivalent to accumulating 4-way dot product per destination element. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01100100011.....111000..........
         p Zm         Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmmla (widening, fp8 to fp32) - 8-bit floating-point matrix multiply-accumulate to single-precision - This 8-bit floating-point widening matrix multiply-accumulate instruction performs the fused sum-of-products within each eight adjacent 8-bit elements while multiplying the 2×8 matrix of 8-bit floating-point values held in each 128-bit segment of the first source vector with the 8×2 matrix of 8-bit floating-point values in the corresponding segment of the second source vector. The single-precision sum-of-products are scaled by 2-UInt(FPMR.LSCALE), before being destructively added without intermediate rounding to the 2×2 single-precision matrix in the corresponding segment of the destination vector. This is equivalent to accumulating 8-way dot product per destination element. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively. is unpredicated. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01100100001.....111000..........
         p Zm         Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmov (immediate, predicated) - move 8-bit floating-point immediate to vector elements (predicated) - Move a floating-point immediate into each active element in the destination vector. Inactive elements in the destination vector register remain unmodified.
00000101..01....110.............
        ze  Pg     imm8    Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <const>:Is a floating-point immediate value expressible as ±n÷16×2^r, where n and r are integers such that 16 ≤ n ≤ 31 and -3 ≤ r ≤ 4, i.e. a normalized binary floating-point encoding with 1 sign bit, 3-bit exponent, and 4-bit fractional part, encoded in the "imm8" field.

fmov (immediate, unpredicated) - move 8-bit floating-point immediate to vector elements (unpredicated) - Unconditionally broadcast the floating-point immediate into each element of the destination vector. is unpredicated.
00100101..111001110.............
        ze   pc   2imm8    Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <const>:Is a floating-point immediate value expressible as ±n÷16×2^r, where n and r are integers such that 16 ≤ n ≤ 31 and -3 ≤ r ≤ 4, i.e. a normalized binary floating-point encoding with 1 sign bit, 3-bit exponent, and 4-bit fractional part, encoded in the "imm8" field.

fmov (zero, predicated) - move floating-point +0.0 to vector elements (predicated) - Move floating-point constant +0.0 to each active element in the destination vector. Inactive elements in the destination vector register remain unmodified.
00000101..01....01000000000.....
        ze  Pg   Mhimm8    Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.

fmov (zero, unpredicated) - move floating-point +0.0 to vector elements (unpredicated) - Unconditionally broadcast the floating-point constant +0.0 into each element of the destination vector. is unpredicated.
00100101..11100011000000000.....
        ze   pc   himm8    Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D

fmsb - floating-point fused multiply-subtract vectors (predicated), writing multiplicand [zdn = za + -zdn * zm] - Multiply the corresponding active floating-point elements of the first and second source vectors and subtract from elements of the third (addend) vector without intermediate rounding. Destructively place the  results in the destination and first source (multiplicand) vector.  Inactive elements in the destination vector register remain unmodified.
01100101..1.....101.............
        ze Za    NpPg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Za>:name of the third source scalable vector register, encoded in the "Za" field.

fmul (immediate) - floating-point multiply by immediate (predicated) - Multiply by an immediate each active floating-point element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate may take the value +0.5 or +2.0 only. Inactive elements in the destination vector register remain unmodified.
01100101..011010100...0000......
        ze   opc   Pg     1Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>
 i1 | <const>
 0 | #0.5
 1 | #2.0

fmul (indexed) - floating-point multiply by indexed elements - Multiply all floating-point elements within each 128-bit segment of the first source vector by the specified element in the corresponding second source vector segment.  The results are placed in the corresponding elements of the destination vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 1 to 3 bits                         depending on the size of the element. is unpredicated.
011001000.1.....001000..........
         h 3lZm     2 Zn   Zd   
01100100101.....001000..........
        ze i2Zm     2 Zn   Zd   
01100100111.....001000..........
        ze 1Zm      2 Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "Half-precision" and "Single-precision" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "Double-precision" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "Half-precision" variant: is the immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "Single-precision" variant: is the immediate index, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "Double-precision" variant: is the immediate index, in the range 0 to 1, encoded in the "i1" field.

fmul (vectors, predicated) - floating-point multiply vectors (predicated) - Multiply active floating-point elements of the first source vector by corresponding floating-point elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01100101!= 00!= 00000010100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmul (vectors, unpredicated) - floating-point multiply vectors (unpredicated) - Multiply all elements of the first source vector by corresponding floating-point elements of the second source vector and place the results in the corresponding elements of the destination vector. is unpredicated.
01100101!= 00!= 000.....000010..........
        ze Zm      opcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fmulx - floating-point multiply-extended vectors (predicated) - Multiply active floating-point elements of the first source vector by corresponding floating-point elements of the second source vector except that ∞×0.0 gives 2.0 instead of NaN, and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified. The instruction can be used with FRECPX to safely convert arbitrary elements in mathematical vector space to unit       vectors or direction vectors with length 1.
01100101..001010100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fneg - floating-point negate (predicated) - Negate each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. This inverts the sign bit and cannot signal a floating-point exception.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
00000100..011101101.............
        ze M opc   Pg Zn   Zd   
00000100..001101101.............
        ze M opc   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

fnmad - floating-point negated fused multiply-add vectors (predicated), writing multiplicand [zdn = -za + -zdn * zm] - Multiply the corresponding active floating-point elements of the first and second source vectors and add to elements of the third (addend) vector without intermediate rounding. Destructively place the negated results in the destination and first source (multiplicand) vector.  Inactive elements in the destination vector register remain unmodified.
01100101..1.....110.............
        ze Za    NpPg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Za>:name of the third source scalable vector register, encoded in the "Za" field.

fnmla - floating-point negated fused multiply-add vectors (predicated), writing addend [zda = -zda + -zn * zm] - Multiply the corresponding active floating-point elements of the first and second source vectors and add to elements of the third source (addend) vector without intermediate rounding.  Destructively place the negated results in the destination and third source (addend) vector.  Inactive elements in the destination vector register remain unmodified.
01100101!= 00!= 001.....010.............
        ze Zm    NpPg Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fnmls - floating-point negated fused multiply-subtract vectors (predicated), writing addend [zda = -zda + zn * zm] - Multiply the corresponding active floating-point elements of the first and second source vectors and subtract from elements of the third source (addend) vector without intermediate rounding.  Destructively place the negated results in the destination and third source (addend) vector.  Inactive elements in the destination vector register remain unmodified.
01100101!= 00!= 001.....011.............
        ze Zm    NpPg Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fnmsb - floating-point negated fused multiply-subtract vectors (predicated), writing multiplicand [zdn = -za + zdn * zm] - Multiply the corresponding active floating-point elements of the first and second source vectors and subtract from elements of the third (addend) vector without intermediate rounding. Destructively place the negated results in the destination and first source (multiplicand) vector.  Inactive elements in the destination vector register remain unmodified.
01100101..1.....111.............
        ze Za    NpPg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Za>:name of the third source scalable vector register, encoded in the "Za" field.

frecpe - floating-point reciprocal estimate (unpredicated) - Find the approximate reciprocal of each floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. is unpredicated.
01100101..001110001100..........
        ze     p      Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

frecps - floating-point reciprocal step (unpredicated) - Multiply corresponding floating-point elements of the first and second source vectors, subtract the products from 2.0 without intermediate rounding and place the results in the corresponding elements of the destination vector. is unpredicated. can be used to perform a single Newton-Raphson iteration for calculating the reciprocal of a vector of floating-point values.
01100101..0.....000110..........
        ze Zm      opcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

frecpx - floating-point reciprocal exponent (predicated) - Invert the exponent and zero the fractional part of each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. The result of this instruction can be used with FMULX to convert arbitrary elements in mathematical vector space to "unit vectors" or "direction vectors" of length 1.
01100101..001100101.............
        ze    pc   Pg Zn   Zd   
01100100..011011100.............
        ze       pcPg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

frint32x - floating-point round to 32-bit integer, using current rounding mode (predicated) - Round to integral floating-point values that fit into a 32-bit integer size using the rounding mode that is determined by the FPCR from each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
01100101000100.1101.............
        pc    zU   Pg Zn   Zd   
01100100000111001.1.............
        pc     2 zUPg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 sz | <T>
 0 | S
 1 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

frint32z - floating-point round to 32-bit integer, toward zero (predicated) - Round to integral floating-point values that fit into a 32-bit integer size using the round towards zero rounding mode from each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
01100101000100.0101.............
        pc    zU   Pg Zn   Zd   
01100100000111001.0.............
        pc     2 zUPg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 sz | <T>
 0 | S
 1 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

frint64x - floating-point round to 64-bit integer, using current rounding mode (predicated) - Round to integral floating-point values that fit into a 64-bit integer size using the rounding mode that is determined by the FPCR from each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
01100101000101.1101.............
        pc    zU   Pg Zn   Zd   
01100100000111011.1.............
        pc     2 zUPg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 sz | <T>
 0 | S
 1 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

frint64z - floating-point round to 64-bit integer, toward zero (predicated) - Round to integral floating-point values that fit into a 64-bit integer size using the round towards zero rounding mode from each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
01100101000101.0101.............
        pc    zU   Pg Zn   Zd   
01100100000111011.0.............
        pc     2 zUPg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 sz | <T>
 0 | S
 1 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

frint<r> - floating-point round to integral value (predicated) - Round to an integral floating-point value with the specified rounding option from each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
01100101..000110101.............
        ze   opc   Pg Zn   Zd   
01100100..011001110.............
        ze     p c2Pg Zn   Zd   
01100101..000111101.............
        ze   opc   Pg Zn   Zd   
01100100..011001111.............
        ze     p c2Pg Zn   Zd   
01100101..000100101.............
        ze   opc   Pg Zn   Zd   
01100100..011001100.............
        ze     p c2Pg Zn   Zd   
01100101..000000101.............
        ze   opc   Pg Zn   Zd   
01100100..011000100.............
        ze     p c2Pg Zn   Zd   
01100101..000011101.............
        ze   opc   Pg Zn   Zd   
01100100..011000111.............
        ze     p c2Pg Zn   Zd   
01100101..000010101.............
        ze   opc   Pg Zn   Zd   
01100100..011000110.............
        ze     p c2Pg Zn   Zd   
01100101..000001101.............
        ze   opc   Pg Zn   Zd   
01100100..011000101.............
        ze     p c2Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

frsqrte - floating-point reciprocal square root estimate (unpredicated) - Find the approximate reciprocal square root of each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. is unpredicated.
01100101..001111001100..........
        ze     p      Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

frsqrts - floating-point reciprocal square root step (unpredicated) - Multiply corresponding floating-point elements of the first and second source vectors, subtract the products from 3.0 and divide the results by 2.0 without any intermediate rounding and place the results in the corresponding elements of the destination vector. is unpredicated. can be used to perform a single Newton-Raphson iteration for calculating the reciprocal square root of a vector of floating-point values.
01100101..0.....000111..........
        ze Zm      opcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fscale - floating-point adjust exponent by vector (predicated) - Multiply the active floating-point elements of the first source vector by 2.0 to the power of the signed integer values in the corresponding elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01100101!= 00!= 00001001100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fsqrt - floating-point square root (predicated) - Calculate the square root of each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
01100101..001101101.............
        ze    pc   Pg Zn   Zd   
01100100..011011101.............
        ze       pcPg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

fsub (immediate) - floating-point subtract immediate (predicated) - Subtract an immediate from each active floating-point element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate may take the value +0.5 or +1.0 only. Inactive elements in the destination vector register remain unmodified.
01100101..011001100...0000......
        ze   opc   Pg     1Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>
 i1 | <const>
 0 | #0.5
 1 | #1.0

fsub (vectors, predicated) - floating-point subtract vectors (predicated) - Subtract active floating-point elements of the second source vector from corresponding floating-point elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01100101!= 00!= 00000001100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fsub (vectors, unpredicated) - floating-point subtract vectors (unpredicated) - Subtract all floating-point elements of the second source vector from corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. is unpredicated.
01100101!= 00!= 000.....000001..........
        ze Zm      opcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

fsubr (immediate) - floating-point reversed subtract from immediate (predicated) - Reversed subtract from an immediate each active floating-point element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate may take the value +0.5 or +1.0 only. Inactive elements in the destination vector register remain unmodified.
01100101..011011100...0000......
        ze   opc   Pg     1Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>
 i1 | <const>
 0 | #0.5
 1 | #1.0

fsubr (vectors) - floating-point reversed subtract vectors (predicated) - Reversed subtract active floating-point elements of the first source vector from corresponding floating-point elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01100101..000011100.............
        ze  opc    Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

ftmad - floating-point trigonometric multiply-add coefficient - The FTMAD instruction multiplies each element of the first source vector by the absolute value of the corresponding element of the second source vector and performs a fused addition of each product with a value obtained from a table of hard-wired coefficients, and places the results destructively in the first source vector. is unpredicated. The coefficients are selected by a combination of the sign bit in the second source element and an immediate index in the range 0 to 7. FTMAD can be combined with FTSMUL and FTSSEL to compute values for sin(x) and cos(x). For more information, see FTSMUL. The coefficients are intended to provide accurate results for FTSMUL inputs in the range -π/4 < x ≤ π/4. For double-precision operations, the coefficients are: For single-precision operations, the coefficients are: For half-precision operations, the coefficients are: is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01100101..010...100000..........
        ze   mm3      Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <imm>:unsigned immediate operand, in the range 0 to 7, encoded in the "imm3" field.

ftsmul - floating-point trigonometric starting value - The FTSMUL instruction multiplies each element of the first source vector by itself, replaces the sign-bit of each product with the least-significant bit of the corresponding element of the second source vector, and places the results in the destination vector. is unpredicated. FTSMUL can be combined with FTMAD and FTSSEL to compute values for sin(x) and cos(x). The use of the second operand is consistent with it holding an integer corresponding to the desired sine-wave quadrant when used in conjunction with FTMAD. Note: FTSMUL, FTMAD, and FTSSEL can be used to compute values for sin(k) and correspondingly cos(k-π/2) via an intermediate value x, in the range -π/4 < x ≤ π/4, and a quadrant q where k = qπ/2 + x, using a Taylor Series approximation. FTSMUL can be used to compute x2, and to insert q<0> into the most-significant bit, indicating the desired odd versus even Taylor Series to be used in FTMAD. Repeated uses of FTMAD can be performed on this value with decreasing immediate index operands, to produce a single accumulated value approximating the Taylor Series result with a single outstanding factor. FTSSEL can be used to apply the final factor of x, 1.0, -x, or -1.0, dependent on the corresponding sine-wave quadrant q<1:0>, to produce a final sin() or cos() value. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01100101..0.....000011..........
        ze Zm      opcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

ftssel - floating-point trigonometric select coefficient - The FTSSEL instruction selects either the element of the first source vector or the value 1.0, based on bit<0> of the corresponding element of the second source element, negates the result if bit<1> of the corresponding element of the second source element is set, and places the results in the destination vector. is unpredicated. FTSSEL can be combined with FTSMUL and FTMAD to compute values for sin(k) and cos(k). For more information, see FTSMUL. The use of the second operand is consistent with it holding an integer corresponding to the desired sine-wave quadrant. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
00000100..1.....101100..........
        ze Zm        pZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

histcnt - count matching elements in vector - compares each active 32 or 64-bit element of the first source vector with all active elements with an element number less than or equal to its own in the second source vector, and places the count of matching elements in the corresponding element of the destination vector. Inactive elements in the destination vector are set to zero. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01000101..1.....110.............
        ze Zm      Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size<0> | <T>
 0 | S
 1 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

histseg - count matching elements in vector segments - compares each 8-bit byte element of the first source vector with all of the elements in the corresponding 128-bit segment of the second source vector and places the count of matching elements in the corresponding element of the destination vector. is unpredicated. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01000101..1.....101000..........
        ze Zm         Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

incb, incd, inch, incw (scalar) - increment scalar by multiple of predicate constraint element count - Determines the number of active  elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment the   scalar destination. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001000011....111000..........
        ze  imm4     DtternRdn  
000001001111....111000..........
        ze  imm4     DtternRdn  
000001000111....111000..........
        ze  imm4     DtternRdn  
000001001011....111000..........
        ze  imm4     DtternRdn  
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

incd, inch, incw (vector) - increment vector by multiple of predicate constraint element count - Determines the number of active  elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment all destination vector elements. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001111....110000..........
        ze  imm4     DtternZdn  
000001000111....110000..........
        ze  imm4     DtternZdn  
000001001011....110000..........
        ze  imm4     DtternZdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

incp (scalar) - increment scalar by count of true predicate elements - Counts the number of true elements in the source predicate and then uses the result to increment the   scalar destination.
00100101..1011001000100.........
        ze    pD     c2Pm  Rdn  
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <Pm>:name of the source scalable predicate register, encoded in the "Pm" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

incp (vector) - increment vector by count of true predicate elements - Counts the number of true elements in the source predicate and then uses the result to increment all destination vector elements. The predicate size specifier may be omitted in assembler    source code, but this is deprecated and will be    prohibited in a future release of the architecture.
00100101..1011001000000.........
        ze    pD     c2Pm  Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pm>:name of the source scalable predicate register, encoded in the "Pm" field.

index (immediate, scalar) - create index starting from immediate and incremented by general-purpose register - Populates the destination vector by setting the first element to the first signed immediate integer operand and monotonically incrementing the value by the second signed scalar integer operand for each subsequent element. The scalar source operand is a general-purpose register in which only the least significant bits corresponding to the vector element size are used and any remaining bits are ignored. is unpredicated.
00000100..1.....010010..........
        ze Rm         imm5 Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm>:signed immediate operand, in the range -16 to 15, encoded in the "imm5" field.
 <R>
 size | <R>
 00 | W
 01 | W
 10 | W
 11 | X
 <m>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

index (immediates) - create index starting from and incremented by immediate - Populates the destination vector by setting the first element to the first signed immediate integer operand and monotonically incrementing the value by the second signed immediate integer operand for each subsequent element.  is unpredicated.
00000100..1.....010000..........
        ze imm5b      imm5 Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm1>:first signed immediate operand, in the range -16 to 15, encoded in the "imm5" field.
 <imm2>:second signed immediate operand, in the range -16 to 15, encoded in the "imm5b" field.

index (scalar, immediate) - create index starting from general-purpose register and incremented by immediate - Populates the destination vector by setting the first element to the first signed scalar integer operand and monotonically incrementing the value by the second signed immediate integer operand for each subsequent element. The scalar source operand is a general-purpose register in which only the least significant bits corresponding to the vector element size are used and any remaining bits are ignored. is unpredicated.
00000100..1.....010001..........
        ze imm5       Rn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <R>
 size | <R>
 00 | W
 01 | W
 10 | W
 11 | X
 <n>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field.
 <imm>:signed immediate operand, in the range -16 to 15, encoded in the "imm5" field.

index (scalars) - create index starting from and incremented by general-purpose register - Populates the destination vector by setting the first element to the first signed scalar integer operand and monotonically incrementing the value by the second signed scalar integer operand for each subsequent element. The scalar source operands are general-purpose registers in which only the least significant bits corresponding to the vector element size are used and any remaining bits are ignored. is unpredicated.
00000100..1.....010011..........
        ze Rm         Rn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <R>
 size | <R>
 00 | W
 01 | W
 10 | W
 11 | X
 <n>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field.
 <m>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

insr (scalar) - insert general-purpose register in shifted vector - Shift the destination vector left by one element, and then place a copy of the least-significant bits of the general-purpose register in element 0 of the destination vector.  is unpredicated.
00000101..100100001110..........
        ze            Rm   Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <R>
 size | <R>
 00 | W
 01 | W
 10 | W
 11 | X
 <m>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

insr (simd&fp scalar) - insert simd&fp scalar register in shifted vector - Shift the destination vector left by one element, and then place a copy of the SIMD&FP scalar register in element 0 of the destination vector. is unpredicated.
00000101..110100001110..........
        ze            Vm   Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <m>:number [0-31] of the source SIMD&FP register, encoded in the "Vm" field.

lasta (scalar) - extract element after last to general-purpose register - If there is an active element then extract the element after the last active element modulo the number of elements from the final source vector register. If there are no active elements, extract element zero. Then zero-extend and place the extracted element in the destination general-purpose register.
00000101..100000101.............
        ze     B   Pg Zn   Rd   
 <R>
 size | <R>
 00 | W
 01 | W
 10 | W
 11 | X
 <d>:number [0-30] of the destination general-purpose register or the name ZR (31), encoded in the "Rd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

lasta (simd&fp scalar) - extract element after last to simd&fp scalar register - If there is an active element then extract the element after the last active element modulo the number of elements from the final source vector register. If there are no active elements, extract element zero. Then  place the extracted element in the destination SIMD&FP scalar register.
00000101..100010100.............
        ze     B   Pg Zn   Vd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

lastb (scalar) - extract last element to general-purpose register - If there is an active element then extract the  last active element  from the final source vector register. If there are no active elements, extract the highest-numbered element. Then zero-extend and place the extracted element in the destination general-purpose register.
00000101..100001101.............
        ze     B   Pg Zn   Rd   
 <R>
 size | <R>
 00 | W
 01 | W
 10 | W
 11 | X
 <d>:number [0-30] of the destination general-purpose register or the name ZR (31), encoded in the "Rd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

lastb (simd&fp scalar) - extract last element to simd&fp scalar register - If there is an active element then extract the  last active element  from the final source vector register. If there are no active elements, extract the highest-numbered element. Then  place the extracted element in the destination SIMD&FP register.
00000101..100011100.............
        ze     B   Pg Zn   Vd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

lastp - scalar index of last true predicate element (predicated) - Determines the index of the last active and true element of the source predicate, or minus one if there are no active and true elements, and places the scalar result in the destination general-purpose register.
00100101..10001010....0.........
        ze   opc  Pg   Pn  Rd   
 <Xd>:64-bit name of the destination general-purpose register, encoded in the "Rd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

ld1b (scalar plus immediate, consecutive registers) - contiguous load of bytes to multiple consecutive vectors (immediate index) - Contiguous load of unsigned bytes to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
101000000100....000............0
            imm4 szPNgRn   Zt  N
101000000100....100...........00
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ld1b (scalar plus immediate, single register) - contiguous load unsigned bytes to vector (immediate index) - Contiguous load    of unsigned bytes to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
101001000000....101.............
       type imm4   Pg Rn   Zt   
101001000010....101.............
       type imm4   Pg Rn   Zt   
101001000100....101.............
       type imm4   Pg Rn   Zt   
101001000110....101.............
       type imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ld1b (scalar plus scalar, consecutive registers) - contiguous load of bytes to multiple consecutive vectors (scalar index) - Contiguous load of unsigned bytes to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
10100000000.....000............0
           Rm    szPNgRn   Zt  N
10100000000.....100...........00
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ld1b (scalar plus scalar, single register) - contiguous load unsigned bytes to vector (scalar index) - Contiguous load    of unsigned bytes to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
10100100000!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
10100100001!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
10100100010!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
10100100011!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld1b (scalar plus vector) - gather load unsigned bytes to vector (vector index) - Gather load  of unsigned bytes to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally        sign or zero-extended from 32 to 64 bits. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
110001000.0.....010.............
       szs Zm    UfPg Rn   Zt   
100001000.0.....010.............
       pcs Zm    UfPg Rn   Zt   
11000100010.....110.............
       sz  Zm    UfPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

ld1b (vector plus immediate) - gather load unsigned bytes to vector (immediate index) - Gather load  of unsigned bytes to active elements of a vector register from memory addresses generated by a  vector base plus immediate index. The index is in the range 0 to 31. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000100001.....110.............
       sz  imm5  UfPg Zn   Zt   
11000100001.....110.............
       sz  imm5  UfPg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, in the range 0 to 31, defaulting to 0, encoded in the "imm5" field.

ld1d (scalar plus immediate, consecutive registers) - contiguous load of doublewords to multiple consecutive vectors (immediate index) - Contiguous load of unsigned doublewords to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
101000000100....011............0
            imm4 szPNgRn   Zt  N
101000000100....111...........00
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ld1d (scalar plus immediate, single register) - contiguous load unsigned doublewords to vector (immediate index) - Contiguous load    of unsigned doublewords to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
101001011110....101.............
       type imm4   Pg Rn   Zt   
101001011001....001.............
       pe   imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ld1d (scalar plus scalar, consecutive registers) - contiguous load of doublewords to multiple consecutive vectors (scalar index) - Contiguous load of unsigned doublewords to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
10100000000.....011............0
           Rm    szPNgRn   Zt  N
10100000000.....111...........00
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ld1d (scalar plus scalar, single register) - contiguous load unsigned doublewords to vector (scalar index) - Contiguous load    of unsigned doublewords to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 8 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10100101111!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
10100101100!= 11111!= 11111!= 11111!= 11111!= 11111100.............
       pe  Rm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld1d (scalar plus vector) - gather load doublewords to vector (vector index) - Gather load  of  doublewords to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then optionally multiplied by 8. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
110001011.1.....010.............
       pcs Zm    UfPg Rn   Zt   
110001011.0.....010.............
       szs Zm    UfPg Rn   Zt   
11000101111.....110.............
       pc  Zm    UfPg Rn   Zt   
11000101110.....110.............
       sz  Zm    UfPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

ld1d (vector plus immediate) - gather load doublewords to vector (immediate index) - Gather load  of  doublewords to active elements of a vector register from memory addresses generated by a  vector base plus immediate index. The index is a multiple of 8 in the range 0 to 248. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11000101101.....110.............
       sz  imm5  UfPg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 8 in the range 0 to 248, defaulting to 0, encoded in the "imm5" field.

ld1h (scalar plus immediate, consecutive registers) - contiguous load of halfwords to multiple consecutive vectors (immediate index) - Contiguous load of unsigned halfwords to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
101000000100....001............0
            imm4 szPNgRn   Zt  N
101000000100....101...........00
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ld1h (scalar plus immediate, single register) - contiguous load unsigned halfwords to vector (immediate index) - Contiguous load    of unsigned halfwords to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
101001001010....101.............
       type imm4   Pg Rn   Zt   
101001001100....101.............
       type imm4   Pg Rn   Zt   
101001001110....101.............
       type imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ld1h (scalar plus scalar, consecutive registers) - contiguous load of halfwords to multiple consecutive vectors (scalar index) - Contiguous load of unsigned halfwords to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
10100000000.....001............0
           Rm    szPNgRn   Zt  N
10100000000.....101...........00
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ld1h (scalar plus scalar, single register) - contiguous load unsigned halfwords to vector (scalar index) - Contiguous load    of unsigned halfwords to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 2 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
10100100101!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
10100100110!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
10100100111!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld1h (scalar plus vector) - gather load unsigned halfwords to vector (vector index) - Gather load  of unsigned halfwords to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then optionally multiplied by 2. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
100001001.1.....010.............
         s Zm    UfPg Rn   Zt   
110001001.1.....010.............
       pcs Zm    UfPg Rn   Zt   
110001001.0.....010.............
       szs Zm    UfPg Rn   Zt   
100001001.0.....010.............
       pcs Zm    UfPg Rn   Zt   
11000100111.....110.............
       pc  Zm    UfPg Rn   Zt   
11000100110.....110.............
       sz  Zm    UfPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

ld1h (vector plus immediate) - gather load unsigned halfwords to vector (immediate index) - Gather load  of unsigned halfwords to active elements of a vector register from memory addresses generated by a  vector base plus immediate index. The index is a multiple of 2 in the range 0 to 62. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000100101.....110.............
       sz  imm5  UfPg Zn   Zt   
11000100101.....110.............
       sz  imm5  UfPg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 62, defaulting to 0, encoded in the "imm5" field.

ld1q - gather load quadwords - Gather load of quadwords to active elements of a vector register from memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11000100000.....101.............
           Rm      Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

ld1rb - load and broadcast unsigned byte to vector - Load a single unsigned byte from a memory address generated by a 64-bit scalar base address plus an immediate offset which is in the range 0 to 63. Broadcast the loaded data into all active elements of the destination vector, setting the inactive elements to zero. If all elements are inactive then the instruction will not perform a read from Device memory or cause a data abort.
1000010001......100.............
       eh imm6   elPg Rn   Zt   
1000010001......101.............
       eh imm6   elPg Rn   Zt   
1000010001......110.............
       eh imm6   elPg Rn   Zt   
1000010001......111.............
       eh imm6   elPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional unsigned immediate byte offset, in the range 0 to 63, defaulting to 0, encoded in the "imm6" field.

ld1rd - load and broadcast doubleword to vector - Load a single  doubleword from a memory address generated by a 64-bit scalar base address plus an immediate offset which is a multiple of 8 in the range 0 to 504. Broadcast the loaded data into all active elements of the destination vector, setting the inactive elements to zero. If all elements are inactive then the instruction will not perform a read from Device memory or cause a data abort.
1000010111......111.............
       eh imm6   elPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 8 in the range 0 to 504, defaulting to 0, encoded in the "imm6" field.

ld1rh - load and broadcast unsigned halfword to vector - Load a single unsigned halfword from a memory address generated by a 64-bit scalar base address plus an immediate offset which is a multiple of 2 in the range 0 to 126. Broadcast the loaded data into all active elements of the destination vector, setting the inactive elements to zero. If all elements are inactive then the instruction will not perform a read from Device memory or cause a data abort.
1000010011......101.............
       eh imm6   elPg Rn   Zt   
1000010011......110.............
       eh imm6   elPg Rn   Zt   
1000010011......111.............
       eh imm6   elPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 126, defaulting to 0, encoded in the "imm6" field.

ld1rob (scalar plus immediate) - contiguous load and replicate thirty-two bytes (immediate index) - Load thirty-two contiguous  bytes to elements of a 256-bit (octaword) vector from the memory address generated by a 64-bit scalar base address and immediate index that is a multiple of 32 in the range -256 to +224 added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting 256-bit vector is then replicated to fill the destination vector.  The instruction requires that the Effective SVE vector length is at least 256 bits. Only the first thirty-two predicate elements are used and higher    numbered predicate elements are ignored. ID_AA64ZFR0_EL1.F64MM indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
101001000010....001.............
       szsz imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate byte offset, a multiple of 32 in the range -256 to 224, defaulting to 0, encoded in the "imm4" field.

ld1rob (scalar plus scalar) - contiguous load and replicate thirty-two bytes (scalar index) - Load thirty-two contiguous  bytes to elements of a 256-bit (octaword) vector from the memory address generated by a 64-bit scalar base address and scalar index which is      added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting 256-bit vector is then replicated to fill the destination vector.  The instruction requires that the Effective SVE vector length is at least 256 bits. Only the first thirty-two predicate elements are used and higher    numbered predicate elements are ignored. ID_AA64ZFR0_EL1.F64MM indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10100100001!= 11111!= 11111!= 11111!= 11111!= 11111000.............
       szszRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld1rod (scalar plus immediate) - contiguous load and replicate four doublewords (immediate index) - Load four contiguous  doublewords to elements of a 256-bit (octaword) vector from the memory address generated by a 64-bit scalar base address and immediate index that is a multiple of 32 in the range -256 to +224 added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting 256-bit vector is then replicated to fill the destination vector.  The instruction requires that the Effective SVE vector length is at least 256 bits. Only the first four predicate elements are used and higher    numbered predicate elements are ignored. ID_AA64ZFR0_EL1.F64MM indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
101001011010....001.............
       szsz imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate byte offset, a multiple of 32 in the range -256 to 224, defaulting to 0, encoded in the "imm4" field.

ld1rod (scalar plus scalar) - contiguous load and replicate four doublewords (scalar index) - Load four contiguous  doublewords to elements of a 256-bit (octaword) vector from the memory address generated by a 64-bit scalar base address and scalar index which is      multiplied by 8 and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting 256-bit vector is then replicated to fill the destination vector.  The instruction requires that the Effective SVE vector length is at least 256 bits. Only the first four predicate elements are used and higher    numbered predicate elements are ignored. ID_AA64ZFR0_EL1.F64MM indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10100101101!= 11111!= 11111!= 11111!= 11111!= 11111000.............
       szszRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld1roh (scalar plus immediate) - contiguous load and replicate sixteen halfwords (immediate index) - Load sixteen contiguous  halfwords to elements of a 256-bit (octaword) vector from the memory address generated by a 64-bit scalar base address and immediate index that is a multiple of 32 in the range -256 to +224 added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting 256-bit vector is then replicated to fill the destination vector.  The instruction requires that the Effective SVE vector length is at least 256 bits. Only the first sixteen predicate elements are used and higher    numbered predicate elements are ignored. ID_AA64ZFR0_EL1.F64MM indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
101001001010....001.............
       szsz imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate byte offset, a multiple of 32 in the range -256 to 224, defaulting to 0, encoded in the "imm4" field.

ld1roh (scalar plus scalar) - contiguous load and replicate sixteen halfwords (scalar index) - Load sixteen contiguous  halfwords to elements of a 256-bit (octaword) vector from the memory address generated by a 64-bit scalar base address and scalar index which is      multiplied by 2 and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting 256-bit vector is then replicated to fill the destination vector.  The instruction requires that the Effective SVE vector length is at least 256 bits. Only the first sixteen predicate elements are used and higher    numbered predicate elements are ignored. ID_AA64ZFR0_EL1.F64MM indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10100100101!= 11111!= 11111!= 11111!= 11111!= 11111000.............
       szszRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld1row (scalar plus immediate) - contiguous load and replicate eight words (immediate index) - Load eight contiguous  words to elements of a 256-bit (octaword) vector from the memory address generated by a 64-bit scalar base address and immediate index that is a multiple of 32 in the range -256 to +224 added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting 256-bit vector is then replicated to fill the destination vector.  The instruction requires that the Effective SVE vector length is at least 256 bits. Only the first eight predicate elements are used and higher    numbered predicate elements are ignored. ID_AA64ZFR0_EL1.F64MM indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
101001010010....001.............
       szsz imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate byte offset, a multiple of 32 in the range -256 to 224, defaulting to 0, encoded in the "imm4" field.

ld1row (scalar plus scalar) - contiguous load and replicate eight words (scalar index) - Load eight contiguous  words to elements of a 256-bit (octaword) vector from the memory address generated by a 64-bit scalar base address and scalar index which is      multiplied by 4 and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting 256-bit vector is then replicated to fill the destination vector.  The instruction requires that the Effective SVE vector length is at least 256 bits. Only the first eight predicate elements are used and higher    numbered predicate elements are ignored. ID_AA64ZFR0_EL1.F64MM indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10100101001!= 11111!= 11111!= 11111!= 11111!= 11111000.............
       szszRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld1rqb (scalar plus immediate) - contiguous load and replicate sixteen bytes (immediate index) - Load sixteen contiguous  bytes to elements of a short, 128-bit (quadword) vector from the memory address generated by a 64-bit scalar base address and immediate index that is a multiple of 16 in the range -128 to +112 added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting short vector is then replicated to fill the long destination vector. Only the first sixteen predicate elements are used and higher    numbered predicate elements are ignored.
101001000000....001.............
       szsz imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate byte offset, a multiple of 16 in the range -128 to 112, defaulting to 0, encoded in the "imm4" field.

ld1rqb (scalar plus scalar) - contiguous load and replicate sixteen bytes (scalar index) - Load sixteen contiguous  bytes to elements of a short, 128-bit (quadword) vector from the memory address generated by a 64-bit scalar base address and scalar index which is      added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting short vector is then replicated to fill the long destination vector. Only the first sixteen predicate elements are used and higher    numbered predicate elements are ignored.
10100100000!= 11111!= 11111!= 11111!= 11111!= 11111000.............
       szszRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld1rqd (scalar plus immediate) - contiguous load and replicate two doublewords (immediate index) - Load two contiguous  doublewords to elements of a short, 128-bit (quadword) vector from the memory address generated by a 64-bit scalar base address and immediate index that is a multiple of 16 in the range -128 to +112 added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting short vector is then replicated to fill the long destination vector. Only the first two predicate elements are used and higher    numbered predicate elements are ignored.
101001011000....001.............
       szsz imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate byte offset, a multiple of 16 in the range -128 to 112, defaulting to 0, encoded in the "imm4" field.

ld1rqd (scalar plus scalar) - contiguous load and replicate two doublewords (scalar index) - Load two contiguous  doublewords to elements of a short, 128-bit (quadword) vector from the memory address generated by a 64-bit scalar base address and scalar index which is      multiplied by 8 and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting short vector is then replicated to fill the long destination vector. Only the first two predicate elements are used and higher    numbered predicate elements are ignored.
10100101100!= 11111!= 11111!= 11111!= 11111!= 11111000.............
       szszRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld1rqh (scalar plus immediate) - contiguous load and replicate eight halfwords (immediate index) - Load eight contiguous  halfwords to elements of a short, 128-bit (quadword) vector from the memory address generated by a 64-bit scalar base address and immediate index that is a multiple of 16 in the range -128 to +112 added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting short vector is then replicated to fill the long destination vector. Only the first eight predicate elements are used and higher    numbered predicate elements are ignored.
101001001000....001.............
       szsz imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate byte offset, a multiple of 16 in the range -128 to 112, defaulting to 0, encoded in the "imm4" field.

ld1rqh (scalar plus scalar) - contiguous load and replicate eight halfwords (scalar index) - Load eight contiguous  halfwords to elements of a short, 128-bit (quadword) vector from the memory address generated by a 64-bit scalar base address and scalar index which is      multiplied by 2 and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting short vector is then replicated to fill the long destination vector. Only the first eight predicate elements are used and higher    numbered predicate elements are ignored.
10100100100!= 11111!= 11111!= 11111!= 11111!= 11111000.............
       szszRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld1rqw (scalar plus immediate) - contiguous load and replicate four words (immediate index) - Load four contiguous  words to elements of a short, 128-bit (quadword) vector from the memory address generated by a 64-bit scalar base address and immediate index that is a multiple of 16 in the range -128 to +112 added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting short vector is then replicated to fill the long destination vector. Only the first four predicate elements are used and higher    numbered predicate elements are ignored.
101001010000....001.............
       szsz imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate byte offset, a multiple of 16 in the range -128 to 112, defaulting to 0, encoded in the "imm4" field.

ld1rqw (scalar plus scalar) - contiguous load and replicate four words (scalar index) - Load four contiguous  words to elements of a short, 128-bit (quadword) vector from the memory address generated by a 64-bit scalar base address and scalar index which is      multiplied by 4 and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero. The resulting short vector is then replicated to fill the long destination vector. Only the first four predicate elements are used and higher    numbered predicate elements are ignored.
10100101000!= 11111!= 11111!= 11111!= 11111!= 11111000.............
       szszRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld1rsb - load and broadcast signed byte to vector - Load a single signed byte from a memory address generated by a 64-bit scalar base address plus an immediate offset which is in the range 0 to 63. Broadcast the loaded data into all active elements of the destination vector, setting the inactive elements to zero. If all elements are inactive then the instruction will not perform a read from Device memory or cause a data abort.
1000010111......110.............
       eh imm6   elPg Rn   Zt   
1000010111......101.............
       eh imm6   elPg Rn   Zt   
1000010111......100.............
       eh imm6   elPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional unsigned immediate byte offset, in the range 0 to 63, defaulting to 0, encoded in the "imm6" field.

ld1rsh - load and broadcast signed halfword to vector - Load a single signed halfword from a memory address generated by a 64-bit scalar base address plus an immediate offset which is a multiple of 2 in the range 0 to 126. Broadcast the loaded data into all active elements of the destination vector, setting the inactive elements to zero. If all elements are inactive then the instruction will not perform a read from Device memory or cause a data abort.
1000010101......101.............
       eh imm6   elPg Rn   Zt   
1000010101......100.............
       eh imm6   elPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 126, defaulting to 0, encoded in the "imm6" field.

ld1rsw - load and broadcast signed word to vector - Load a single signed word from a memory address generated by a 64-bit scalar base address plus an immediate offset which is a multiple of 4 in the range 0 to 252. Broadcast the loaded data into all active elements of the destination vector, setting the inactive elements to zero. If all elements are inactive then the instruction will not perform a read from Device memory or cause a data abort.
1000010011......100.............
       eh imm6   elPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 252, defaulting to 0, encoded in the "imm6" field.

ld1rw - load and broadcast unsigned word to vector - Load a single unsigned word from a memory address generated by a 64-bit scalar base address plus an immediate offset which is a multiple of 4 in the range 0 to 252. Broadcast the loaded data into all active elements of the destination vector, setting the inactive elements to zero. If all elements are inactive then the instruction will not perform a read from Device memory or cause a data abort.
1000010101......110.............
       eh imm6   elPg Rn   Zt   
1000010101......111.............
       eh imm6   elPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 252, defaulting to 0, encoded in the "imm6" field.

ld1sb (scalar plus immediate) - contiguous load signed bytes to vector (immediate index) - Contiguous load    of signed bytes to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
101001011100....101.............
       type imm4   Pg Rn   Zt   
101001011010....101.............
       type imm4   Pg Rn   Zt   
101001011000....101.............
       type imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ld1sb (scalar plus scalar) - contiguous load signed bytes to vector (scalar index) - Contiguous load    of signed bytes to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
10100101110!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
10100101101!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
10100101100!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld1sb (scalar plus vector) - gather load signed bytes to vector (vector index) - Gather load  of signed bytes to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally        sign or zero-extended from 32 to 64 bits. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
110001000.0.....000.............
       szs Zm    UfPg Rn   Zt   
100001000.0.....000.............
       pcs Zm    UfPg Rn   Zt   
11000100010.....100.............
       sz  Zm    UfPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

ld1sb (vector plus immediate) - gather load signed bytes to vector (immediate index) - Gather load  of signed bytes to active elements of a vector register from memory addresses generated by a  vector base plus immediate index. The index is in the range 0 to 31. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000100001.....100.............
       sz  imm5  UfPg Zn   Zt   
11000100001.....100.............
       sz  imm5  UfPg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, in the range 0 to 31, defaulting to 0, encoded in the "imm5" field.

ld1sh (scalar plus immediate) - contiguous load signed halfwords to vector (immediate index) - Contiguous load    of signed halfwords to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
101001010010....101.............
       type imm4   Pg Rn   Zt   
101001010000....101.............
       type imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ld1sh (scalar plus scalar) - contiguous load signed halfwords to vector (scalar index) - Contiguous load    of signed halfwords to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 2 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
10100101001!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
10100101000!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld1sh (scalar plus vector) - gather load signed halfwords to vector (vector index) - Gather load  of signed halfwords to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then optionally multiplied by 2. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
100001001.1.....000.............
         s Zm    UfPg Rn   Zt   
110001001.1.....000.............
       pcs Zm    UfPg Rn   Zt   
110001001.0.....000.............
       szs Zm    UfPg Rn   Zt   
100001001.0.....000.............
       pcs Zm    UfPg Rn   Zt   
11000100111.....100.............
       pc  Zm    UfPg Rn   Zt   
11000100110.....100.............
       sz  Zm    UfPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

ld1sh (vector plus immediate) - gather load signed halfwords to vector (immediate index) - Gather load  of signed halfwords to active elements of a vector register from memory addresses generated by a  vector base plus immediate index. The index is a multiple of 2 in the range 0 to 62. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000100101.....100.............
       sz  imm5  UfPg Zn   Zt   
11000100101.....100.............
       sz  imm5  UfPg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 62, defaulting to 0, encoded in the "imm5" field.

ld1sw (scalar plus immediate) - contiguous load signed words to vector (immediate index) - Contiguous load    of signed words to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
101001001000....101.............
       type imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ld1sw (scalar plus scalar) - contiguous load signed words to vector (scalar index) - Contiguous load    of signed words to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 4 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
10100100100!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld1sw (scalar plus vector) - gather load signed words to vector (vector index) - Gather load  of signed words to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then optionally multiplied by 4. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
110001010.1.....000.............
       pcs Zm    UfPg Rn   Zt   
110001010.0.....000.............
       szs Zm    UfPg Rn   Zt   
11000101011.....100.............
       pc  Zm    UfPg Rn   Zt   
11000101010.....100.............
       sz  Zm    UfPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

ld1sw (vector plus immediate) - gather load signed words to vector (immediate index) - Gather load  of signed words to active elements of a vector register from memory addresses generated by a  vector base plus immediate index. The index is a multiple of 4 in the range 0 to 124. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11000101001.....100.............
       sz  imm5  UfPg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 124, defaulting to 0, encoded in the "imm5" field.

ld1w (scalar plus immediate, consecutive registers) - contiguous load of words to multiple consecutive vectors (immediate index) - Contiguous load of unsigned words to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
101000000100....010............0
            imm4 szPNgRn   Zt  N
101000000100....110...........00
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ld1w (scalar plus immediate, single register) - contiguous load unsigned words to vector (immediate index) - Contiguous load    of unsigned words to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
101001010100....101.............
       type imm4   Pg Rn   Zt   
101001010110....101.............
       type imm4   Pg Rn   Zt   
101001010001....001.............
       pe   imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ld1w (scalar plus scalar, consecutive registers) - contiguous load of words to multiple consecutive vectors (scalar index) - Contiguous load of unsigned words to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
10100000000.....010............0
           Rm    szPNgRn   Zt  N
10100000000.....110...........00
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ld1w (scalar plus scalar, single register) - contiguous load unsigned words to vector (scalar index) - Contiguous load    of unsigned words to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 4 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10100101010!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
10100101011!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       typeRm      Pg Rn   Zt   
10100101000!= 11111!= 11111!= 11111!= 11111!= 11111100.............
       pe  Rm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld1w (scalar plus vector) - gather load unsigned words to vector (vector index) - Gather load  of unsigned words to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then optionally multiplied by 4. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
100001010.1.....010.............
         s Zm    UfPg Rn   Zt   
110001010.1.....010.............
       pcs Zm    UfPg Rn   Zt   
110001010.0.....010.............
       szs Zm    UfPg Rn   Zt   
100001010.0.....010.............
       pcs Zm    UfPg Rn   Zt   
11000101011.....110.............
       pc  Zm    UfPg Rn   Zt   
11000101010.....110.............
       sz  Zm    UfPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

ld1w (vector plus immediate) - gather load unsigned words to vector (immediate index) - Gather load  of unsigned words to active elements of a vector register from memory addresses generated by a  vector base plus immediate index. The index is a multiple of 4 in the range 0 to 124. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000101001.....110.............
       sz  imm5  UfPg Zn   Zt   
11000101001.....110.............
       sz  imm5  UfPg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 124, defaulting to 0, encoded in the "imm5" field.

ld2b (scalar plus immediate) - contiguous load two-byte structures to two vectors (immediate index) - Contiguous load two-byte structures, each to the same element number in two vector registers from the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 2 in the range -16 to 14 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  bytes in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the two destination vector registers.
101001000010....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.

ld2b (scalar plus scalar) - contiguous load two-byte structures to two vectors (scalar index) - Contiguous load two-byte structures, each to the same element number in two vector registers from the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register    and added to the base address.   After each structure access the index value is   incremented by two.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  bytes in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the two destination vector registers.
10100100001!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld2d (scalar plus immediate) - contiguous load two-doubleword structures to two vectors (immediate index) - Contiguous load two-doubleword structures, each to the same element number in two vector registers from the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 2 in the range -16 to 14 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  doublewords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the two destination vector registers.
101001011010....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.

ld2d (scalar plus scalar) - contiguous load two-doubleword structures to two vectors (scalar index) - Contiguous load two-doubleword structures, each to the same element number in two vector registers from the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by two.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  doublewords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the two destination vector registers.
10100101101!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld2h (scalar plus immediate) - contiguous load two-halfword structures to two vectors (immediate index) - Contiguous load two-halfword structures, each to the same element number in two vector registers from the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 2 in the range -16 to 14 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  halfwords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the two destination vector registers.
101001001010....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.

ld2h (scalar plus scalar) - contiguous load two-halfword structures to two vectors (scalar index) - Contiguous load two-halfword structures, each to the same element number in two vector registers from the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by two.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  halfwords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the two destination vector registers.
10100100101!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld2q (scalar plus immediate) - contiguous load two-quadword structures to two vectors (immediate index) - Contiguous load two-quadword structures, each to the same element number in two vector registers from the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 2 in the range -16 to 14 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  quadwords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the two destination vector registers.
101001001001....111.............
       um   imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.

ld2q (scalar plus scalar) - contiguous load two-quadword structures to two vectors (scalar index) - Contiguous load two-quadword structures, each to the same element number in two vector registers from the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by two.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  quadwords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the two destination vector registers.
10100100101!= 11111!= 11111!= 11111!= 11111!= 11111100.............
       um  Rm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld2w (scalar plus immediate) - contiguous load two-word structures to two vectors (immediate index) - Contiguous load two-word structures, each to the same element number in two vector registers from the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 2 in the range -16 to 14 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  words in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the two destination vector registers.
101001010010....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.

ld2w (scalar plus scalar) - contiguous load two-word structures to two vectors (scalar index) - Contiguous load two-word structures, each to the same element number in two vector registers from the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by two.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  words in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the two destination vector registers.
10100101001!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld3b (scalar plus immediate) - contiguous load three-byte structures to three vectors (immediate index) - Contiguous load three-byte structures, each to the same element number in three vector registers from the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 3 in the range -24 to 21 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  bytes in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the three destination vector registers.
101001000100....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 3 in the range -24 to 21, defaulting to 0, encoded in the "imm4" field.

ld3b (scalar plus scalar) - contiguous load three-byte structures to three vectors (scalar index) - Contiguous load three-byte structures, each to the same element number in three vector registers from the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register    and added to the base address.   After each structure access the index value is   incremented by three.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  bytes in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the three destination vector registers.
10100100010!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld3d (scalar plus immediate) - contiguous load three-doubleword structures to three vectors (immediate index) - Contiguous load three-doubleword structures, each to the same element number in three vector registers from the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 3 in the range -24 to 21 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  doublewords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the three destination vector registers.
101001011100....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 3 in the range -24 to 21, defaulting to 0, encoded in the "imm4" field.

ld3d (scalar plus scalar) - contiguous load three-doubleword structures to three vectors (scalar index) - Contiguous load three-doubleword structures, each to the same element number in three vector registers from the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by three.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  doublewords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the three destination vector registers.
10100101110!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld3h (scalar plus immediate) - contiguous load three-halfword structures to three vectors (immediate index) - Contiguous load three-halfword structures, each to the same element number in three vector registers from the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 3 in the range -24 to 21 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  halfwords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the three destination vector registers.
101001001100....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 3 in the range -24 to 21, defaulting to 0, encoded in the "imm4" field.

ld3h (scalar plus scalar) - contiguous load three-halfword structures to three vectors (scalar index) - Contiguous load three-halfword structures, each to the same element number in three vector registers from the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by three.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  halfwords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the three destination vector registers.
10100100110!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld3q (scalar plus immediate) - contiguous load three-quadword structures to three vectors (immediate index) - Contiguous load three-quadword structures, each to the same element number in three vector registers from the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 3 in the range -24 to 21 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  quadwords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the three destination vector registers.
101001010001....111.............
       um   imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 3 in the range -24 to 21, defaulting to 0, encoded in the "imm4" field.

ld3q (scalar plus scalar) - contiguous load three-quadword structures to three vectors (scalar index) - Contiguous load three-quadword structures, each to the same element number in three vector registers from the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by three.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  quadwords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the three destination vector registers.
10100101001!= 11111!= 11111!= 11111!= 11111!= 11111100.............
       um  Rm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld3w (scalar plus immediate) - contiguous load three-word structures to three vectors (immediate index) - Contiguous load three-word structures, each to the same element number in three vector registers from the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 3 in the range -24 to 21 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  words in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the three destination vector registers.
101001010100....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 3 in the range -24 to 21, defaulting to 0, encoded in the "imm4" field.

ld3w (scalar plus scalar) - contiguous load three-word structures to three vectors (scalar index) - Contiguous load three-word structures, each to the same element number in three vector registers from the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by three.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  words in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the three destination vector registers.
10100101010!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld4b (scalar plus immediate) - contiguous load four-byte structures to four vectors (immediate index) - Contiguous load four-byte structures, each to the same element number in four vector registers from the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 4 in the range -32 to 28 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  bytes in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the four destination vector registers.
101001000110....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.

ld4b (scalar plus scalar) - contiguous load four-byte structures to four vectors (scalar index) - Contiguous load four-byte structures, each to the same element number in four vector registers from the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register    and added to the base address.   After each structure access the index value is   incremented by four.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  bytes in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the four destination vector registers.
10100100011!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld4d (scalar plus immediate) - contiguous load four-doubleword structures to four vectors (immediate index) - Contiguous load four-doubleword structures, each to the same element number in four vector registers from the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 4 in the range -32 to 28 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  doublewords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the four destination vector registers.
101001011110....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.

ld4d (scalar plus scalar) - contiguous load four-doubleword structures to four vectors (scalar index) - Contiguous load four-doubleword structures, each to the same element number in four vector registers from the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by four.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  doublewords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the four destination vector registers.
10100101111!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld4h (scalar plus immediate) - contiguous load four-halfword structures to four vectors (immediate index) - Contiguous load four-halfword structures, each to the same element number in four vector registers from the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 4 in the range -32 to 28 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  halfwords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the four destination vector registers.
101001001110....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.

ld4h (scalar plus scalar) - contiguous load four-halfword structures to four vectors (scalar index) - Contiguous load four-halfword structures, each to the same element number in four vector registers from the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by four.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  halfwords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the four destination vector registers.
10100100111!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld4q (scalar plus immediate) - contiguous load four-quadword structures to four vectors (immediate index) - Contiguous load four-quadword structures, each to the same element number in four vector registers from the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 4 in the range -32 to 28 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  quadwords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the four destination vector registers.
101001011001....111.............
       um   imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.

ld4q (scalar plus scalar) - contiguous load four-quadword structures to four vectors (scalar index) - Contiguous load four-quadword structures, each to the same element number in four vector registers from the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by four.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  quadwords in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the four destination vector registers.
10100101101!= 11111!= 11111!= 11111!= 11111!= 11111100.............
       um  Rm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ld4w (scalar plus immediate) - contiguous load four-word structures to four vectors (immediate index) - Contiguous load four-word structures, each to the same element number in four vector registers from the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 4 in the range -32 to 28 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  words in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the four destination vector registers.
101001010110....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.

ld4w (scalar plus scalar) - contiguous load four-word structures to four vectors (scalar index) - Contiguous load four-word structures, each to the same element number in four vector registers from the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by four.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  words in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the four destination vector registers.
10100101011!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ldff1b (scalar plus scalar) - contiguous load first-fault unsigned bytes to vector (scalar index) - Contiguous load with first-faulting behavior   of unsigned bytes to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10100100000.....011.............
       typeRm      Pg Rn   Zt   
10100100001.....011.............
       typeRm      Pg Rn   Zt   
10100100010.....011.............
       typeRm      Pg Rn   Zt   
10100100011.....011.............
       typeRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

ldff1b (scalar plus vector) - gather load first-fault unsigned bytes to vector (vector index) - Gather load with first-faulting behavior of unsigned bytes to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally        sign or zero-extended from 32 to 64 bits. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
110001000.0.....011.............
       szs Zm    UfPg Rn   Zt   
100001000.0.....011.............
       pcs Zm    UfPg Rn   Zt   
11000100010.....111.............
       sz  Zm    UfPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

ldff1b (vector plus immediate) - gather load first-fault unsigned bytes to vector (immediate index) - Gather load with first-faulting behavior of unsigned bytes to active elements of a vector register from memory addresses generated by a  vector base plus immediate index. The index is in the range 0 to 31. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000100001.....111.............
       sz  imm5  UfPg Zn   Zt   
11000100001.....111.............
       sz  imm5  UfPg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, in the range 0 to 31, defaulting to 0, encoded in the "imm5" field.

ldff1d (scalar plus scalar) - contiguous load first-fault doublewords to vector (scalar index) - Contiguous load with first-faulting behavior   of  doublewords to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 8 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10100101111.....011.............
       typeRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

ldff1d (scalar plus vector) - gather load first-fault doublewords to vector (vector index) - Gather load with first-faulting behavior of  doublewords to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then optionally multiplied by 8. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
110001011.1.....011.............
       pcs Zm    UfPg Rn   Zt   
110001011.0.....011.............
       szs Zm    UfPg Rn   Zt   
11000101111.....111.............
       pc  Zm    UfPg Rn   Zt   
11000101110.....111.............
       sz  Zm    UfPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

ldff1d (vector plus immediate) - gather load first-fault doublewords to vector (immediate index) - Gather load with first-faulting behavior of  doublewords to active elements of a vector register from memory addresses generated by a  vector base plus immediate index. The index is a multiple of 8 in the range 0 to 248. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11000101101.....111.............
       sz  imm5  UfPg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 8 in the range 0 to 248, defaulting to 0, encoded in the "imm5" field.

ldff1h (scalar plus scalar) - contiguous load first-fault unsigned halfwords to vector (scalar index) - Contiguous load with first-faulting behavior   of unsigned halfwords to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 2 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10100100101.....011.............
       typeRm      Pg Rn   Zt   
10100100110.....011.............
       typeRm      Pg Rn   Zt   
10100100111.....011.............
       typeRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

ldff1h (scalar plus vector) - gather load first-fault unsigned halfwords to vector (vector index) - Gather load with first-faulting behavior of unsigned halfwords to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then optionally multiplied by 2. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
100001001.1.....011.............
         s Zm    UfPg Rn   Zt   
110001001.1.....011.............
       pcs Zm    UfPg Rn   Zt   
110001001.0.....011.............
       szs Zm    UfPg Rn   Zt   
100001001.0.....011.............
       pcs Zm    UfPg Rn   Zt   
11000100111.....111.............
       pc  Zm    UfPg Rn   Zt   
11000100110.....111.............
       sz  Zm    UfPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

ldff1h (vector plus immediate) - gather load first-fault unsigned halfwords to vector (immediate index) - Gather load with first-faulting behavior of unsigned halfwords to active elements of a vector register from memory addresses generated by a  vector base plus immediate index. The index is a multiple of 2 in the range 0 to 62. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000100101.....111.............
       sz  imm5  UfPg Zn   Zt   
11000100101.....111.............
       sz  imm5  UfPg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 62, defaulting to 0, encoded in the "imm5" field.

ldff1sb (scalar plus scalar) - contiguous load first-fault signed bytes to vector (scalar index) - Contiguous load with first-faulting behavior   of signed bytes to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10100101110.....011.............
       typeRm      Pg Rn   Zt   
10100101101.....011.............
       typeRm      Pg Rn   Zt   
10100101100.....011.............
       typeRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

ldff1sb (scalar plus vector) - gather load first-fault signed bytes to vector (vector index) - Gather load with first-faulting behavior of signed bytes to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally        sign or zero-extended from 32 to 64 bits. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
110001000.0.....001.............
       szs Zm    UfPg Rn   Zt   
100001000.0.....001.............
       pcs Zm    UfPg Rn   Zt   
11000100010.....101.............
       sz  Zm    UfPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

ldff1sb (vector plus immediate) - gather load first-fault signed bytes to vector (immediate index) - Gather load with first-faulting behavior of signed bytes to active elements of a vector register from memory addresses generated by a  vector base plus immediate index. The index is in the range 0 to 31. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000100001.....101.............
       sz  imm5  UfPg Zn   Zt   
11000100001.....101.............
       sz  imm5  UfPg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, in the range 0 to 31, defaulting to 0, encoded in the "imm5" field.

ldff1sh (scalar plus scalar) - contiguous load first-fault signed halfwords to vector (scalar index) - Contiguous load with first-faulting behavior   of signed halfwords to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 2 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10100101001.....011.............
       typeRm      Pg Rn   Zt   
10100101000.....011.............
       typeRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

ldff1sh (scalar plus vector) - gather load first-fault signed halfwords to vector (vector index) - Gather load with first-faulting behavior of signed halfwords to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then optionally multiplied by 2. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
100001001.1.....001.............
         s Zm    UfPg Rn   Zt   
110001001.1.....001.............
       pcs Zm    UfPg Rn   Zt   
110001001.0.....001.............
       szs Zm    UfPg Rn   Zt   
100001001.0.....001.............
       pcs Zm    UfPg Rn   Zt   
11000100111.....101.............
       pc  Zm    UfPg Rn   Zt   
11000100110.....101.............
       sz  Zm    UfPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

ldff1sh (vector plus immediate) - gather load first-fault signed halfwords to vector (immediate index) - Gather load with first-faulting behavior of signed halfwords to active elements of a vector register from memory addresses generated by a  vector base plus immediate index. The index is a multiple of 2 in the range 0 to 62. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000100101.....101.............
       sz  imm5  UfPg Zn   Zt   
11000100101.....101.............
       sz  imm5  UfPg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 62, defaulting to 0, encoded in the "imm5" field.

ldff1sw (scalar plus scalar) - contiguous load first-fault signed words to vector (scalar index) - Contiguous load with first-faulting behavior   of signed words to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 4 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10100100100.....011.............
       typeRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

ldff1sw (scalar plus vector) - gather load first-fault signed words to vector (vector index) - Gather load with first-faulting behavior of signed words to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then optionally multiplied by 4. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
110001010.1.....001.............
       pcs Zm    UfPg Rn   Zt   
110001010.0.....001.............
       szs Zm    UfPg Rn   Zt   
11000101011.....101.............
       pc  Zm    UfPg Rn   Zt   
11000101010.....101.............
       sz  Zm    UfPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

ldff1sw (vector plus immediate) - gather load first-fault signed words to vector (immediate index) - Gather load with first-faulting behavior of signed words to active elements of a vector register from memory addresses generated by a  vector base plus immediate index. The index is a multiple of 4 in the range 0 to 124. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11000101001.....101.............
       sz  imm5  UfPg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 124, defaulting to 0, encoded in the "imm5" field.

ldff1w (scalar plus scalar) - contiguous load first-fault unsigned words to vector (scalar index) - Contiguous load with first-faulting behavior   of unsigned words to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 4 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10100101010.....011.............
       typeRm      Pg Rn   Zt   
10100101011.....011.............
       typeRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

ldff1w (scalar plus vector) - gather load first-fault unsigned words to vector (vector index) - Gather load with first-faulting behavior of unsigned words to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then optionally multiplied by 4. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
100001010.1.....011.............
         s Zm    UfPg Rn   Zt   
110001010.1.....011.............
       pcs Zm    UfPg Rn   Zt   
110001010.0.....011.............
       szs Zm    UfPg Rn   Zt   
100001010.0.....011.............
       pcs Zm    UfPg Rn   Zt   
11000101011.....111.............
       pc  Zm    UfPg Rn   Zt   
11000101010.....111.............
       sz  Zm    UfPg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

ldff1w (vector plus immediate) - gather load first-fault unsigned words to vector (immediate index) - Gather load with first-faulting behavior of unsigned words to active elements of a vector register from memory addresses generated by a  vector base plus immediate index. The index is a multiple of 4 in the range 0 to 124. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000101001.....111.............
       sz  imm5  UfPg Zn   Zt   
11000101001.....111.............
       sz  imm5  UfPg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 124, defaulting to 0, encoded in the "imm5" field.

ldnf1b - contiguous load non-fault unsigned bytes to vector (immediate index) - Contiguous load  with non-faulting behavior  of unsigned bytes to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
101001000001....101.............
       type imm4   Pg Rn   Zt   
101001000011....101.............
       type imm4   Pg Rn   Zt   
101001000101....101.............
       type imm4   Pg Rn   Zt   
101001000111....101.............
       type imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ldnf1d - contiguous load non-fault doublewords to vector (immediate index) - Contiguous load  with non-faulting behavior  of  doublewords to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
101001011111....101.............
       type imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ldnf1h - contiguous load non-fault unsigned halfwords to vector (immediate index) - Contiguous load  with non-faulting behavior  of unsigned halfwords to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
101001001011....101.............
       type imm4   Pg Rn   Zt   
101001001101....101.............
       type imm4   Pg Rn   Zt   
101001001111....101.............
       type imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ldnf1sb - contiguous load non-fault signed bytes to vector (immediate index) - Contiguous load  with non-faulting behavior  of signed bytes to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
101001011101....101.............
       type imm4   Pg Rn   Zt   
101001011011....101.............
       type imm4   Pg Rn   Zt   
101001011001....101.............
       type imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ldnf1sh - contiguous load non-fault signed halfwords to vector (immediate index) - Contiguous load  with non-faulting behavior  of signed halfwords to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
101001010011....101.............
       type imm4   Pg Rn   Zt   
101001010001....101.............
       type imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ldnf1sw - contiguous load non-fault signed words to vector (immediate index) - Contiguous load  with non-faulting behavior  of signed words to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
101001001001....101.............
       type imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ldnf1w - contiguous load non-fault unsigned words to vector (immediate index) - Contiguous load  with non-faulting behavior  of unsigned words to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
101001010101....101.............
       type imm4   Pg Rn   Zt   
101001010111....101.............
       type imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ldnt1b (scalar plus immediate, consecutive registers) - contiguous load non-temporal of bytes to multiple consecutive vectors (immediate index) - Contiguous load non-temporal of bytes to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
101000000100....000............1
            imm4 szPNgRn   Zt  N
101000000100....100...........01
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ldnt1b (scalar plus immediate, single register) - contiguous load non-temporal bytes to vector (immediate index) - Contiguous load   non-temporal of  bytes to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
101001000000....111.............
       sz   imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ldnt1b (scalar plus scalar, consecutive registers) - contiguous load non-temporal of bytes to multiple consecutive vectors (scalar index) - Contiguous load non-temporal of bytes to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
10100000000.....000............1
           Rm    szPNgRn   Zt  N
10100000000.....100...........01
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ldnt1b (scalar plus scalar, single register) - contiguous load non-temporal bytes to vector (scalar index) - Contiguous load   non-temporal of  bytes to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
10100100000!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       sz  Rm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ldnt1b (vector plus scalar) - gather load non-temporal unsigned bytes - Gather load non-temporal of unsigned bytes to active elements of a vector register from memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset.  Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000100000.....101.............
       sz  Rm     UPg Zn   Zt   
11000100000.....110.............
       sz  Rm    U Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

ldnt1d (scalar plus immediate, consecutive registers) - contiguous load non-temporal of doublewords to multiple consecutive vectors (immediate index) - Contiguous load non-temporal of doublewords to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
101000000100....011............1
            imm4 szPNgRn   Zt  N
101000000100....111...........01
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ldnt1d (scalar plus immediate, single register) - contiguous load non-temporal doublewords to vector (immediate index) - Contiguous load   non-temporal of  doublewords to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
101001011000....111.............
       sz   imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ldnt1d (scalar plus scalar, consecutive registers) - contiguous load non-temporal of doublewords to multiple consecutive vectors (scalar index) - Contiguous load non-temporal of doublewords to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
10100000000.....011............1
           Rm    szPNgRn   Zt  N
10100000000.....111...........01
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ldnt1d (scalar plus scalar, single register) - contiguous load non-temporal doublewords to vector (scalar index) - Contiguous load   non-temporal of  doublewords to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 8 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
10100101100!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       sz  Rm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ldnt1d (vector plus scalar) - gather load non-temporal unsigned doublewords - Gather load non-temporal of  doublewords to active elements of a vector register from memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset.  Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11000101100.....110.............
       sz  Rm    U Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

ldnt1h (scalar plus immediate, consecutive registers) - contiguous load non-temporal of halfwords to multiple consecutive vectors (immediate index) - Contiguous load non-temporal of halfwords to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
101000000100....001............1
            imm4 szPNgRn   Zt  N
101000000100....101...........01
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ldnt1h (scalar plus immediate, single register) - contiguous load non-temporal halfwords to vector (immediate index) - Contiguous load   non-temporal of  halfwords to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
101001001000....111.............
       sz   imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ldnt1h (scalar plus scalar, consecutive registers) - contiguous load non-temporal of halfwords to multiple consecutive vectors (scalar index) - Contiguous load non-temporal of halfwords to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
10100000000.....001............1
           Rm    szPNgRn   Zt  N
10100000000.....101...........01
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ldnt1h (scalar plus scalar, single register) - contiguous load non-temporal halfwords to vector (scalar index) - Contiguous load   non-temporal of  halfwords to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 2 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
10100100100!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       sz  Rm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ldnt1h (vector plus scalar) - gather load non-temporal unsigned halfwords - Gather load non-temporal of unsigned halfwords to active elements of a vector register from memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset.  Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000100100.....101.............
       sz  Rm     UPg Zn   Zt   
11000100100.....110.............
       sz  Rm    U Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

ldnt1sb - gather load non-temporal signed bytes - Gather load non-temporal of signed bytes to active elements of a vector register from memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset.  Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000100000.....100.............
       sz  Rm     UPg Zn   Zt   
11000100000.....100.............
       sz  Rm    U Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

ldnt1sh - gather load non-temporal signed halfwords - Gather load non-temporal of signed halfwords to active elements of a vector register from memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset.  Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000100100.....100.............
       sz  Rm     UPg Zn   Zt   
11000100100.....100.............
       sz  Rm    U Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

ldnt1sw - gather load non-temporal signed words - Gather load non-temporal of signed words to active elements of a vector register from memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset.  Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11000101000.....100.............
       sz  Rm    U Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

ldnt1w (scalar plus immediate, consecutive registers) - contiguous load non-temporal of words to multiple consecutive vectors (immediate index) - Contiguous load non-temporal of words to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
101000000100....010............1
            imm4 szPNgRn   Zt  N
101000000100....110...........01
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ldnt1w (scalar plus immediate, single register) - contiguous load non-temporal words to vector (immediate index) - Contiguous load   non-temporal of  words to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
101001010000....111.............
       sz   imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

ldnt1w (scalar plus scalar, consecutive registers) - contiguous load non-temporal of words to multiple consecutive vectors (scalar index) - Contiguous load non-temporal of words to elements of two or four consecutive vector registers from the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
10100000000.....010............1
           Rm    szPNgRn   Zt  N
10100000000.....110...........01
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

ldnt1w (scalar plus scalar, single register) - contiguous load non-temporal words to vector (scalar index) - Contiguous load   non-temporal of  words to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 4 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
10100101000!= 11111!= 11111!= 11111!= 11111!= 11111110.............
       sz  Rm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

ldnt1w (vector plus scalar) - gather load non-temporal unsigned words - Gather load non-temporal of unsigned words to active elements of a vector register from memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset.  Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000101000.....101.............
       sz  Rm     UPg Zn   Zt   
11000101000.....110.............
       sz  Rm    U Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

ldr (predicate) - load predicate register - Load a predicate register from a memory address generated by a 64-bit scalar base, plus an immediate offset in the range -256 to 255 which is multiplied by the current predicate register size in bytes. is unpredicated. The load is performed as contiguous byte accesses, each containing 8 consecutive predicate bits in ascending element order, with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then a general-purpose base register must be aligned to 2 bytes. For programmer convenience, an assembler must also accept       a predicate-as-counter register name for the destination       predicate register.
1000010110......000........0....
          imm9h    m9lRn    Pt  
 <Pt>:name of the destination scalable predicate register, encoded in the "Pt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9h:imm9l" fields.

ldr (vector) - load vector register - Load a vector register from a memory address generated by a 64-bit scalar base, plus an immediate offset in the range -256 to 255 which is multiplied by the current vector register size in bytes. is unpredicated. The load is performed as contiguous byte accesses,  with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then the base register must be aligned to 16 bytes.
1000010110......010.............
          imm9h    m9lRn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9h:imm9l" fields.

lsl (immediate, predicated) - logical shift left by immediate (predicated) - Shift left by immediate each active element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate shift amount is an unsigned value in the range 0 to number of bits per element minus 1. Inactive elements in the destination vector register remain unmodified.
00000100..000011100.............
        zh  pcLU   Pg zlmm3Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>:immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3".

lsl (immediate, unpredicated) - logical shift left by immediate (unpredicated) - Shift left by immediate each element of the source vector, and place the results in the corresponding elements of the destination vector. The immediate shift amount is an unsigned value in the range 0 to number of bits per element minus 1. is unpredicated.
00000100..1.....100111..........
        zh zlmm3    pcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <const>:immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3".

lsl (vectors) - logical shift left by vector (predicated) - Shift left active elements of the first source vector by corresponding elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount operand is a vector of unsigned elements in which all bits are significant, and not used modulo the element size.  Inactive elements in the destination vector register remain unmodified.
00000100..010011100.............
        ze   RLU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

lsl (wide elements, predicated) - logical shift left by 64-bit wide elements (predicated) - Shift left active elements of the first source vector by corresponding overlapping 64-bit elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount is a vector of unsigned 64-bit doubleword elements in which all bits are significant, and not used modulo the destination element size. Inactive elements in the destination vector register remain unmodified.
00000100..011011100.............
        ze   RLU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | RESERVED
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

lsl (wide elements, unpredicated) - logical shift left by 64-bit wide elements (unpredicated) - Shift left all elements of the first source vector by corresponding overlapping 64-bit elements of the second source vector and place the first in the corresponding elements of the destination vector. The shift amount is a vector of unsigned 64-bit doubleword elements in which all bits are significant, and not used modulo the destination element size. Inactive elements in the destination vector register remain unmodified.
00000100..1.....100011..........
        ze Zm       pcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | RESERVED
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

lslr - reversed logical shift left by vector (predicated) - Reversed shift left active elements of the second source vector by corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount operand is a vector of unsigned elements in which all bits are significant, and not used modulo the element size.  Inactive elements in the destination vector register remain unmodified.
00000100..010111100.............
        ze   RLU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

lsr (immediate, predicated) - logical shift right by immediate (predicated) - Shift right by immediate, inserting zeroes, each active element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. Inactive elements in the destination vector register remain unmodified.
00000100..000001100.............
        zh  pcLU   Pg zlmm3Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

lsr (immediate, unpredicated) - logical shift right by immediate (unpredicated) - Shift right by immediate, inserting zeroes, each element of the source vector, and place the results in the corresponding elements of the destination vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
00000100..1.....100101..........
        zh zlmm3     UZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

lsr (vectors) - logical shift right by vector (predicated) - Shift right, inserting zeroes, active elements of the first source vector by corresponding elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount operand is a vector of unsigned elements in which all bits are significant, and not used modulo the element size. Inactive elements in the destination vector register remain unmodified.
00000100..010001100.............
        ze   RLU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

lsr (wide elements, predicated) - logical shift right by 64-bit wide elements (predicated) - Shift right, inserting zeroes, active elements of the first source vector by corresponding overlapping 64-bit elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount is a vector of unsigned 64-bit doubleword elements in which all bits are significant, and not used modulo the destination element size. Inactive elements in the destination vector register remain unmodified.
00000100..011001100.............
        ze   RLU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | RESERVED
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

lsr (wide elements, unpredicated) - logical shift right by 64-bit wide elements (unpredicated) - Shift right, inserting zeroes, all elements of the first source vector by corresponding overlapping 64-bit elements of the second source vector and place the first in the corresponding elements of the destination vector. The shift amount is a vector of unsigned 64-bit doubleword elements in which all bits are significant, and not used modulo the destination element size. is unpredicated.
00000100..1.....100001..........
        ze Zm        UZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | RESERVED
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

lsrr - reversed logical shift right by vector (predicated) - Reversed shift right, inserting zeroes, active elements of the second source vector by corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount operand is a vector of unsigned elements in which all bits are significant, and not used modulo the element size.  Inactive elements in the destination vector register remain unmodified.
00000100..010101100.............
        ze   RLU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

luti2 - lookup table read with 2-bit indices - copies indexed 8-bit or 16-bit elements from the low 128 bits of the table vector to the destination vector using packed 2-bit indices from a segment of the source vector. A segment corresponds to a portion of the source vector that is consumed in order to fill the destination vector. The segment is selected by the vector segment index. is unpredicated.
01000101..1.....101100..........
        i2 Zm         Zn   Zd   
01000101..1.....101.10..........
        3h Zm      l  Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the table vector register, encoded in the "Zn" field.
 <Zm>:name of the source scalable vector register, encoded in the "Zm" field.
 <index>:For the "Byte" variant: is the vector segment index, in the range 0 to 3, encoded in the "i2" field.
 <index>:For the "Halfword" variant: is the vector segment index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

luti4 - lookup table read with 4-bit indices - copies indexed 8-bit or 16-bit elements from the low 128 or 256 bits of the table vector,       or from the low 128 bits of the two table vectors to the destination vector using packed 4-bit indices from a segment of the source vector. A segment corresponds to a portion of the source vector that is consumed in order to fill the destination vector. The segment is selected by the vector segment index. is unpredicated.
01000101.11.....101001..........
        1  Zm         Zn   Zd   
01000101..1.....101101..........
        i2 Zm       p Zn   Zd   
01000101..1.....101111..........
        i2 Zm       p Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the table vector register, encoded in the "Zn" field.
 <Zm>:name of the source scalable vector register, encoded in the "Zm" field.
 <index>:For the "Byte, single register table" variant: is the vector segment index, in the range 0 to 1, encoded in the "i1" field.
 <index>:For the "Halfword, single register table" and "Halfword, two register table" variants: is the vector segment index, in the range 0 to 3, encoded in the "i2" field.
 <Zn1>:name of the first table vector register, encoded as "Zn".
 <Zn2>:name of the second table vector register, encoded as "Zn" plus 1 modulo 32.

mad - multiply-add vectors (predicated), writing multiplicand [zdn = za + zdn * zm] - Multiply the corresponding active  elements of the first and second source vectors and add to elements of the third (addend) vector. Destructively place the  results in the destination and first source (multiplicand) vector.  Inactive elements in the destination vector register remain unmodified.
00000100..0.....110.............
        ze Zm     pPg Za   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Za>:name of the third source scalable vector register, encoded in the "Za" field.

madpt - multiply-add checked pointer vectors, writing multiplicand [zdn = za + zdn * zm] - Multiply with overflow check the elements of the first and second source vectors and add with pointer check to elements of the third (addend) vector.  Destructively place the results in the destination and first source (multiplicand) vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01000100110.....110110..........
        pc Zm       c2Za   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Za>:name of the third source scalable vector register, encoded in the "Za" field.

match - detect any matching elements, setting the condition flags - compares each active 8-bit or 16-bit character in the first source vector with all of the characters in the corresponding 128-bit segment of the second source vector. Where the first source element detects any matching characters in the second segment it places true in the corresponding element of the destination predicate, otherwise false. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01000101..1.....100........0....
        ze Zm      Pg Zn   pPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size<0> | <T>
 0 | B
 1 | H
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

mla (indexed) - multiply-add to accumulator (indexed) - Multiply all integer elements within each 128-bit segment of the first source vector by the specified element in the corresponding second source vector segment.  The products are then destructively added to the corresponding elements of the addend and destination vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 1 to 3 bits                         depending on the size of the element. is unpredicated.
010001000.1.....000010..........
         h 3lZm      SZn   Zda  
01000100101.....000010..........
        ze i2Zm      SZn   Zda  
01000100111.....000010..........
        ze 1Zm       SZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "16-bit" and "32-bit" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "16-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field.

mla (vectors) - multiply-add vectors (predicated), writing addend [zda = zda + zn * zm] - Multiply the corresponding active  elements of the first and second source vectors and add to elements of the third source (addend) vector.  Destructively place the  results in the destination and third source (addend) vector.  Inactive elements in the destination vector register remain unmodified.
00000100..0.....010.............
        ze Zm     pPg Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

mlapt - multiply-add checked pointer vectors, writing addend [zda = zda + zn * zm] - Multiply with overflow check the elements of the first and second source vectors and add pointer check to elements of the third source (addend) vector.  Destructively place the results in the destination and third source (addend) vector. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01000100110.....110100..........
        pc Zm       c2Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

mls (indexed) - multiply-subtract from accumulator (indexed) - Multiply all integer elements within each 128-bit segment of the first source vector by the specified element in the corresponding second source vector segment.  The products are then destructively subtracted from the corresponding elements of the addend and destination vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 1 to 3 bits                         depending on the size of the element. is unpredicated.
010001000.1.....000011..........
         h 3lZm      SZn   Zda  
01000100101.....000011..........
        ze i2Zm      SZn   Zda  
01000100111.....000011..........
        ze 1Zm       SZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "16-bit" and "32-bit" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "16-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field.

mls (vectors) - multiply-subtract vectors (predicated), writing addend [zda = zda - zn * zm] - Multiply the corresponding active  elements of the first and second source vectors and subtract from elements of the third source (addend) vector.  Destructively place the  results in the destination and third source (addend) vector.  Inactive elements in the destination vector register remain unmodified.
00000100..0.....011.............
        ze Zm     pPg Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

mov - move logical bitmask immediate to vector (unpredicated) - Unconditionally broadcast the logical bitmask immediate into each element of the destination vector. is unpredicated. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits.
00000101110000..................
              imm13        Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 imm13 | <T>
 0xxxxxx0xxxxx | S
 0xxxxxx10xxxx | H
 0xxxxxx110xxx | B
 0xxxxxx1110xx | B
 0xxxxxx11110x | B
 0xxxxxx11111x | RESERVED
 1xxxxxxxxxxxx | D
 <const>:Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.

mov - move predicate (unpredicated) - Read all elements from the source predicate and place in the destination predicate. is unpredicated. Does not set the condition flags. For programmer convenience, an assembler must also accept       predicate-as-counter register names for the source and destination       predicate registers.
001001011000....01....0....0....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.

mov (immediate, merging) - move signed integer immediate to vector elements (merging) - Move a signed integer immediate to each active element in the destination vector. Inactive elements in the destination vector register remain unmodified. The immediate operand is a signed value in the range -128 to +127, and for element widths of 16 bits or higher it may also be a signed multiple of 256 in the range -32768 to +32512 (excluding 0). The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<simm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".
00000101..01....01..............
        ze  Pg   Mhimm8    Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <imm>:Is a signed immediate in the range -128 to 127, encoded in the "imm8" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #8

mov (immediate, unpredicated) - move signed immediate to vector elements (unpredicated) - Unconditionally broadcast the signed integer immediate into each element of the destination vector. is unpredicated. The immediate operand is a signed value in the range -128 to +127, and for element widths of 16 bits or higher it may also be a signed multiple of 256 in the range -32768 to +32512 (excluding 0). The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<simm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".
00100101..11100011..............
        ze   pc   himm8    Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm>:Is a signed immediate in the range -128 to 127, encoded in the "imm8" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #8

mov (immediate, zeroing) - move signed integer immediate to vector elements (zeroing) - Move a signed integer immediate to each active element in the destination vector. Inactive elements in the destination vector register are set to zero. The immediate operand is a signed value in the range -128 to +127, and for element widths of 16 bits or higher it may also be a signed multiple of 256 in the range -32768 to +32512 (excluding 0). The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<simm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".
00000101..01....00..............
        ze  Pg   Mhimm8    Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <imm>:Is a signed immediate in the range -128 to 127, encoded in the "imm8" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #8

mov (predicate, merging) - move predicates (merging) - Read active elements from the source predicate and place in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register remain unmodified. Does not set the condition flags.
001001010000....01....1....1....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.

mov (predicate, zeroing) - move predicates (zeroing) - Read active elements from the source predicate and place in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
001001010000....01....0....0....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.

mov (scalar, predicated) - move general-purpose register to vector elements (predicated) - Move the general-purpose scalar source register to each active element in the destination vector. Inactive elements in the destination vector register remain unmodified.
00000101..101000101.............
        ze         Pg Rn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <R>
 size | <R>
 00 | W
 01 | W
 10 | W
 11 | X
 <n|SP>:number [0-30] of the general-purpose source register or the name SP (31), encoded in the "Rn" field.

mov (scalar, unpredicated) - move general-purpose register to vector elements (unpredicated) - Unconditionally broadcast the general-purpose scalar source register into each element of the destination vector. is unpredicated.
00000101..100000001110..........
        ze            Rn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <R>
 size | <R>
 00 | W
 01 | W
 10 | W
 11 | X
 <n|SP>:number [0-30] of the general-purpose source register or the name SP (31), encoded in the "Rn" field.

mov (simd&fp scalar, predicated) - move simd&fp scalar register to vector elements (predicated) - Move the SIMD & floating-point scalar source register to each active element in the destination vector. Inactive elements in the destination vector register remain unmodified.
00000101..100000100.............
        ze         Pg Vn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <n>:number [0-31] of the source SIMD&FP register, encoded in the "Vn" field.

mov (simd&fp scalar, unpredicated) - move indexed element or simd&fp scalar to vector (unpredicated) - Unconditionally broadcast the SIMD&FP scalar into each element of the destination vector. is unpredicated.
00000101..1.....001000..........
        m2 tsz        Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tsz | <T>
 00000 | RESERVED
 xxxx1 | B
 xxx10 | H
 xx100 | S
 x1000 | D
 10000 | Q
 <V>
 tsz | <V>
 00000 | RESERVED
 xxxx1 | B
 xxx10 | H
 xx100 | S
 x1000 | D
 10000 | Q
 <n>:number [0-31] of the source SIMD&FP register, encoded in the "Zn" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <imm>:immediate index, in the range 0 to one less than the number of elements in 512 bits, encoded in "imm2:tsz".

mov (vector, predicated) - move vector elements (predicated) - Move elements from the source vector to the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.
00000101..1.....11..............
        ze Zm     Pv  Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pv>:name of the vector select predicate register, encoded in the "Pv" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

mov (vector, unpredicated) - move vector register (unpredicated) - Move vector register. is unpredicated.
00000100011.....001100..........
        pc Zm         Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

movprfx (predicated) - move prefix (predicated) - The predicated MOVPRFX instruction is a hint to hardware that the instruction may be combined with the destructive instruction which follows it in program order to create a single constructive operation.  Since it is a hint it is also permitted to be implemented as a discrete vector copy, and the result of executing the pair of instructions with or without combining is identical. The choice of combined versus discrete operation may vary dynamically. Unless the combination of a constructive operation with    merging predication is specifically required, it is strongly    recommended that for performance reasons software should    prefer to use the zeroing form of predicated MOVPRFX or    the unpredicated MOVPRFX instruction. Although the operation of the instruction is defined as a simple predicated vector copy, it is required that the prefixed instruction at PC+4 must be an SVE destructive binary or ternary instruction encoding, or a unary operation with merging predication, but excluding other MOVPRFX instructions. The prefixed instruction must specify the same predicate register, and  have the same maximum element size   (ignoring a fixed 64-bit "wide vector" operand), and the same destination vector as the MOVPRFX instruction. The prefixed instruction must not use the destination register in any other operand position, even if they have different names but refer to the same architectural register state. Any other use is UNPREDICTABLE.
00000100..01000.001.............
        ze   pcM   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <ZM>
 M | <ZM>
 0 | Z
 1 | M
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

movprfx (unpredicated) - move prefix (unpredicated) - The unpredicated MOVPRFX instruction is a hint to hardware that the instruction may be combined with the destructive instruction which follows it in program order to create a single constructive operation.  Since it is a hint it is also permitted to be implemented as a discrete vector copy, and the result of executing the pair of instructions with or without combining is identical. The choice of combined versus discrete operation may vary dynamically. Although the operation of the instruction is defined as a simple unpredicated vector copy, it is required that the prefixed instruction at PC+4 must be an SVE destructive binary or ternary instruction encoding, or a unary operation with merging predication, but excluding other MOVPRFX instructions. The prefixed instruction must specify    the same destination vector as the MOVPRFX instruction. The prefixed instruction must not use the destination register in any other operand position, even if they have different names but refer to the same architectural register state. Any other use is UNPREDICTABLE.
0000010000100000101111..........
        pc opc2       Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

movs (predicated) - move predicates (zeroing), setting the condition flags - Read active elements from the source predicate and place in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
001001010100....01....0....0....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.

movs (unpredicated) - move predicate (unpredicated), setting the condition flags - Read all elements from the source predicate and place in the destination predicate. is unpredicated. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
001001011100....01....0....0....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.

msb - multiply-subtract vectors (predicated), writing multiplicand [zdn = za - zdn * zm] - Multiply the corresponding active  elements of the first and second source vectors and subtract from elements of the third (addend) vector. Destructively place the  results in the destination and first source (multiplicand) vector.  Inactive elements in the destination vector register remain unmodified.
00000100..0.....111.............
        ze Zm     pPg Za   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Za>:name of the third source scalable vector register, encoded in the "Za" field.

mul (immediate) - multiply by immediate (unpredicated) - Multiply by an immediate each element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate is a signed 8-bit value in the range -128 to +127, inclusive. is unpredicated.
00100101..110000110.............
        ze   opc  2imm8    Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm>:signed immediate operand, in the range -128 to 127, encoded in the "imm8" field.

mul (indexed) - multiply (indexed) - Multiply all integer elements within each 128-bit segment of the first source vector by the specified element in the corresponding second source vector segment.  The results are placed in the corresponding elements of the destination vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 1 to 3 bits                         depending on the size of the element. is unpredicated.
010001000.1.....111110..........
         h 3lZm       Zn   Zd   
01000100101.....111110..........
        ze i2Zm       Zn   Zd   
01000100111.....111110..........
        ze 1Zm        Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "16-bit" and "32-bit" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "16-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field.

mul (vectors, predicated) - multiply vectors (predicated) - Multiply active elements of the first source vector by corresponding elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..010000000.............
        ze    HU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

mul (vectors, unpredicated) - multiply vectors (unpredicated) - Multiply all elements of the first source vector by corresponding elements of the second source vector and place the results in the corresponding elements of the destination vector. is unpredicated.
00000100..1.....011000..........
        ze Zm       pcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

nand - bitwise nand predicates - Bitwise NAND active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
001001011000....01....1....1....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

nands - bitwise nand predicates, setting the condition flags - Bitwise NAND active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
001001011100....01....1....1....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

nbsl - bitwise inverted select - Selects bits from the  first source vector where the corresponding bit in the third source vector is '1', and from the  second source vector where the corresponding bit in the third source vector is '0'. The inverted result is placed destructively in the destination and first source vector. is unpredicated.
00000100111.....001111..........
        pc Zm        2Zk   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Zk>:name of the third source scalable vector register, encoded in the "Zk" field.

neg - negate (predicated) - Negate the signed integer value in each active element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
00000100..010111101.............
        ze M opc   Pg Zn   Zd   
00000100..000111101.............
        ze M opc   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

nmatch - detect no matching elements, setting the condition flags - compares each active 8-bit or 16-bit character in the first source vector with all of the characters in the corresponding 128-bit segment of the second source vector. Where the first source element detects no matching characters in the second segment it places true in the corresponding element of the destination predicate, otherwise false. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01000101..1.....100........1....
        ze Zm      Pg Zn   pPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size<0> | <T>
 0 | B
 1 | H
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

nor - bitwise nor predicates - Bitwise NOR active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
001001011000....01....1....0....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

nors - bitwise nor predicates, setting the condition flags - Bitwise NOR active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
001001011100....01....1....0....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

not (predicate) - bitwise invert predicate - Bitwise invert each active element of the source predicate, and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
001001010000....01....1....0....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.

not (vector) - bitwise invert vector (predicated) - Bitwise invert each active element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
00000100..011110101.............
        ze M opc   Pg Zn   Zd   
00000100..001110101.............
        ze M opc   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

nots - bitwise invert predicate, setting the condition flags - Bitwise invert each active element of the source predicate, and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
001001010100....01....1....0....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.

orn (immediate) - bitwise inclusive or with inverted immediate (unpredicated) - Bitwise inclusive OR an inverted immediate with each 64-bit element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits. is unpredicated.
00000101000000..................
        pc    imm13        Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 imm13 | <T>
 0xxxxxx0xxxxx | S
 0xxxxxx10xxxx | H
 0xxxxxx110xxx | B
 0xxxxxx1110xx | B
 0xxxxxx11110x | B
 0xxxxxx11111x | RESERVED
 1xxxxxxxxxxxx | D
 <const>:Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.

orn (predicates) - bitwise inclusive or inverted predicate - Bitwise inclusive OR inverted active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
001001011000....01....0....1....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

orns - bitwise inclusive or inverted predicate, setting the condition flags - Bitwise inclusive OR inverted active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
001001011100....01....0....1....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

orqv - bitwise inclusive or reduction of quadword vector segments - Bitwise inclusive OR of the same element numbers from each 128-bit source vector segment, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as all zeros.
00000100..011100001.............
        ze    pc   Pg Zn   Vd   
 <Vd>:name of the destination SIMD&FP register, encoded in the "Vd" field.
 <T>
 size | <T>
 00 | 16B
 01 | 8H
 10 | 4S
 11 | 2D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | B
 01 | H
 10 | S
 11 | D

orr (immediate) - bitwise inclusive or with immediate (unpredicated) - Bitwise inclusive OR an immediate with each 64-bit element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits. is unpredicated.
00000101000000..................
        pc    imm13        Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 imm13 | <T>
 0xxxxxx0xxxxx | S
 0xxxxxx10xxxx | H
 0xxxxxx110xxx | B
 0xxxxxx1110xx | B
 0xxxxxx11110x | B
 0xxxxxx11111x | RESERVED
 1xxxxxxxxxxxx | D
 <const>:Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.

orr (predicates) - bitwise inclusive or predicates - Bitwise inclusive OR active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
001001011000....01....0....0....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

orr (vectors, predicated) - bitwise inclusive or vectors (predicated) - Bitwise inclusive OR active elements of the second source vector with corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..011000000.............
        ze   opc   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

orr (vectors, unpredicated) - bitwise inclusive or vectors (unpredicated) - Bitwise inclusive OR all elements of the second source vector with corresponding elements of the first source vector and place the first in the corresponding elements of the destination vector. is unpredicated.
00000100011.....001100..........
        pc Zm         Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

orrs - bitwise inclusive or predicates, setting the condition flags - Bitwise inclusive OR active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
001001011100....01....0....0....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

orv - bitwise inclusive or reduction to scalar - Bitwise inclusive OR horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register.  Inactive elements in the source vector are treated as zero.
00000100..011000001.............
        ze    pc   Pg Zn   Vd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

pext (predicate pair) - predicate extract pair from predicate-as-counter - Converts the source predicate-as-counter into a four register wide predicate-as-mask, and copies the two portions of the mask value selected by the portion index to the two destination predicate registers. A portion corresponds to a one predicate register fraction of the wider predicate-as-mask value.
00100101..1000000111010....1....
        ze             1PNn Pd  
 <Pd1>:name of the first destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pd2>:name of the second destination scalable predicate register, encoded in the "Pd" field.
 <PNn>:name of the first source scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNn" field.
 <imm>:portion index, in the range 0 to 1, encoded in the "i1" field.

pext (predicate) - predicate extract from predicate-as-counter - Converts the source predicate-as-counter into a four register wide predicate-as-mask, and copies the portion of the mask value selected by the portion index to the destination predicate register. A portion corresponds to a one predicate register fraction of the wider predicate-as-mask value.
00100101..100000011100.....1....
        ze            m2PNn Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <PNn>:name of the first source scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNn" field.
 <imm>:portion index, in the range 0 to 3, encoded in the "imm2" field.

pfalse - set all predicate elements to false - Set all elements in the destination predicate to false. For programmer convenience, an assembler       must also accept predicate-as-counter register name for the       destination predicate register.
0010010100011000111001000000....
        pS                  Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.

pfirst - set the first active predicate element to true - Sets the first active element in the destination predicate to true, otherwise elements from the source predicate are passed through unchanged. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101010110001100000....0....
        pS             Pg   Pdn 
 <Pdn>:name of the source and destination scalable predicate register, encoded in the "Pdn" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.

pmlal - multi-vector polynomial multiply long and accumulate vectors - Polynomial multiply over [0, 1] the corresponding even-numbered elements of the first and second source vectors, and bitwise exclusive-OR the result with the overlapping double-width elements of the first destination vector. Perform the same operation with odd-numbered elements of the source vectors, writing to the second destination vector. is unpredicated. is legal in Streaming SVE mode if both FEAT_SSVE_AES and FEAT_SVE_AES2 are implemented.
01000101001.....111111.........0
        ze Zm         Zn   Zda  
 <Zda1>:name of the first scalable vector register of the destination multi-vector group, encoded as "Zda" times 2.
 <Zda2>:name of the second scalable vector register of the destination multi-vector group, encoded as "Zda" times 2 plus 1.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

pmov (to predicate) - move predicate from vector - Copy a packed bitmap, where bit value 0b1 represents TRUE and bit value 0b0 represents FALSE, from a portion of the source vector register to elements of the destination SVE predicate register. Because the number of bits in an SVE predicate element scales with the vector element size, the behavior varies according to the specified element size. The portion index is optional, defaulting to 0 if omitted.
0000010100101010001110.....0....
        pc   c2       Zn    Pd  
000001011.101..0001110.....0....
         h   3l       Zn    Pd  
00000101001011.0001110.....0....
        pc    1       Zn    Pd  
0000010101101..0001110.....0....
        pc   i2       Zn    Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <imm>:For the "Doubleword" variant: is the optional portion index, in the range 0 to 7, defaulting to 0, encoded in the "i3h:i3l" fields.
 <imm>:For the "Halfword" variant: is the optional portion index, in the range 0 to 1, defaulting to 0, encoded in the "i1" field.
 <imm>:For the "Word" variant: is the optional portion index, in the range 0 to 3, defaulting to 0, encoded in the "i2" field.

pmov (to vector) - move predicate to vector - Copy the source SVE predicate register elements into the destination vector register as a packed bitmap with one bit per predicate element, where bit value 0b1 represents a TRUE predicate element, and bit value 0b0 represents a FALSE predicate element. Because the number of bits in an SVE predicate element scales with the vector element size, the behavior varies according to the specified element size. The portion index is optional, defaulting to 0 if omitted. When the index is zero, the instruction writes zeroes to the most significant VL-(VL/esize) bits of the destination vector register. When a non-zero index is specified, the packed bitmap is inserted into the destination vector register, and the unindexed blocks remain unchanged.
00000101001010110011100.........
        pc   c2        Pn  Zd   
000001011.101..10011100.........
         h   3l        Pn  Zd   
00000101001011.10011100.........
        pc    1        Pn  Zd   
0000010101101..10011100.........
        pc   i2        Pn  Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.
 <imm>:For the "Doubleword" variant: is the optional portion index, in the range 0 to 7, defaulting to 0, encoded in the "i3h:i3l" fields.
 <imm>:For the "Halfword" variant: is the optional portion index, in the range 0 to 1, defaulting to 0, encoded in the "i1" field.
 <imm>:For the "Word" variant: is the optional portion index, in the range 0 to 3, defaulting to 0, encoded in the "i2" field.

pmul - polynomial multiply vectors (unpredicated) - Polynomial multiply over [0, 1] all elements of the second source vector to corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. is unpredicated.
00000100001.....011001..........
        ze Zm       pcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

pmull - multi-vector polynomial multiply long - Polynomial multiply over [0, 1] the corresponding even-numbered elements of the first and second source vectors, and place the results in the overlapping double-width elements of the first destination vector. Perform the same operation with odd-numbered elements of the source vectors, writing to the second destination vector. is unpredicated. is legal in Streaming SVE mode if both FEAT_SSVE_AES and FEAT_SVE_AES2 are implemented.
01000101001.....111110.........0
        ze Zm         Zn   Zd   
 <Zd1>:name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.
 <Zd2>:name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

pmullb - polynomial multiply long (bottom) - Polynomial multiply over [0, 1] the corresponding even-numbered elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. is unpredicated. ID_AA64ZFR0_EL1.AES indicates whether the 128-bit element variant is implemented. The 128-bit element variant is legal in Streaming SVE mode if one of the following is true:
01000101!= 00!= 000.....011010..........
        ze Zm      pUTZn   Zd   
01000101000.....011010..........
        ze Zm      pUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 01 | H
 1x | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 01 | B
 1x | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

pmullt - polynomial multiply long (top) - Polynomial multiply over [0, 1] the corresponding odd-numbered elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. is unpredicated. ID_AA64ZFR0_EL1.AES indicates whether the 128-bit element variant is implemented. The 128-bit element variant is legal in Streaming SVE mode if one of the following is true:
01000101!= 00!= 000.....011011..........
        ze Zm      pUTZn   Zd   
01000101000.....011011..........
        ze Zm      pUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 01 | H
 1x | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 01 | B
 1x | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

pnext - find next active predicate - An instruction used to construct a loop which iterates over all true elements in the vector select predicate register. If all elements in the first source predicate register are false it determines the first true element in the vector select predicate register, otherwise it determines the next true element in the vector select predicate register that follows the last true element in the first source predicate register. All elements of the destination predicate register are set to false, except the element corresponding to the determined vector select element, if any, which is set to true. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..0110011100010....0....
        ze             Pv   Pdn 
 <Pdn>:name of the first source and destination scalable predicate register, encoded in the "Pdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pv>:name of the vector select predicate register, encoded in the "Pv" field.

prfb (scalar plus immediate) - contiguous prefetch bytes (immediate index) - Contiguous prefetch of byte elements from the memory address generated by a 64-bit scalar base and immediate index in the range -32 to 31 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.
1000010111......000........0....
          imm6   szPg Rn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -32 to 31, defaulting to 0, encoded in the "imm6" field.

prfb (scalar plus scalar) - contiguous prefetch bytes (scalar index) - Contiguous prefetch of byte elements from the memory address generated by a 64-bit scalar base and scalar index which is      added to the base address. After each     element prefetch     the index value is incremented,     but the index register is not updated.
10000100000!= 11111!= 11111!= 11111!= 11111!= 11111110........0....
       sz  Rm      Pg Rn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

prfb (scalar plus vector) - gather prefetch bytes (scalar plus vector) - Gather prefetch of  bytes from the active memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally        sign or zero-extended from 32 to 64 bits. Inactive addresses are not prefetched from memory. The <prfop> symbol specifies the prefetch hint as a combination of three options: access type PLD for load or PST for store; target cache level L1, L2 or L3; temporality (KEEP for temporal or STRM for non-temporal). is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
100001000.1.....000........0....
         s Zm    szPg Rn    rfop
110001000.1.....000........0....
         s Zm    szPg Rn    rfop
11000100011.....100........0....
           Zm    szPg Rn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

prfb (vector plus immediate) - gather prefetch bytes (vector plus immediate) - Gather prefetch of  bytes from the active memory addresses generated by a  vector base plus immediate index. The index is in the range 0 to 31. Inactive addresses are not prefetched from memory. The <prfop> symbol specifies the prefetch hint as a combination of three options: access type PLD for load or PST for store; target cache level L1, L2 or L3; temporality (KEEP for temporal or STRM for non-temporal). is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000100000.....111........0....
       sz  imm5    Pg Zn    rfop
11000100000.....111........0....
       sz  imm5    Pg Zn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, in the range 0 to 31, defaulting to 0, encoded in the "imm5" field.

prfd (scalar plus immediate) - contiguous prefetch doublewords (immediate index) - Contiguous prefetch of doubleword elements from the memory address generated by a 64-bit scalar base and immediate index in the range -32 to 31 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.
1000010111......011........0....
          imm6   szPg Rn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -32 to 31, defaulting to 0, encoded in the "imm6" field.

prfd (scalar plus scalar) - contiguous prefetch doublewords (scalar index) - Contiguous prefetch of doubleword elements from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 8 and added to the base address. After each     element prefetch     the index value is incremented,     but the index register is not updated.
10000101100!= 11111!= 11111!= 11111!= 11111!= 11111110........0....
       sz  Rm      Pg Rn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

prfd (scalar plus vector) - gather prefetch doublewords (scalar plus vector) - Gather prefetch of  doublewords from the active memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then multiplied by 8. Inactive addresses are not prefetched from memory. The <prfop> symbol specifies the prefetch hint as a combination of three options: access type PLD for load or PST for store; target cache level L1, L2 or L3; temporality (KEEP for temporal or STRM for non-temporal). is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
100001000.1.....011........0....
         s Zm    szPg Rn    rfop
110001000.1.....011........0....
         s Zm    szPg Rn    rfop
11000100011.....111........0....
           Zm    szPg Rn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

prfd (vector plus immediate) - gather prefetch doublewords (vector plus immediate) - Gather prefetch of  doublewords from the active memory addresses generated by a  vector base plus immediate index. The index is a multiple of 8 in the range 0 to 248. Inactive addresses are not prefetched from memory. The <prfop> symbol specifies the prefetch hint as a combination of three options: access type PLD for load or PST for store; target cache level L1, L2 or L3; temporality (KEEP for temporal or STRM for non-temporal). is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000101100.....111........0....
       sz  imm5    Pg Zn    rfop
11000101100.....111........0....
       sz  imm5    Pg Zn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 8 in the range 0 to 248, defaulting to 0, encoded in the "imm5" field.

prfh (scalar plus immediate) - contiguous prefetch halfwords (immediate index) - Contiguous prefetch of halfword elements from the memory address generated by a 64-bit scalar base and immediate index in the range -32 to 31 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.
1000010111......001........0....
          imm6   szPg Rn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -32 to 31, defaulting to 0, encoded in the "imm6" field.

prfh (scalar plus scalar) - contiguous prefetch halfwords (scalar index) - Contiguous prefetch of halfword elements from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 2 and added to the base address. After each     element prefetch     the index value is incremented,     but the index register is not updated.
10000100100!= 11111!= 11111!= 11111!= 11111!= 11111110........0....
       sz  Rm      Pg Rn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

prfh (scalar plus vector) - gather prefetch halfwords (scalar plus vector) - Gather prefetch of  halfwords from the active memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then multiplied by 2. Inactive addresses are not prefetched from memory. The <prfop> symbol specifies the prefetch hint as a combination of three options: access type PLD for load or PST for store; target cache level L1, L2 or L3; temporality (KEEP for temporal or STRM for non-temporal). is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
100001000.1.....001........0....
         s Zm    szPg Rn    rfop
110001000.1.....001........0....
         s Zm    szPg Rn    rfop
11000100011.....101........0....
           Zm    szPg Rn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

prfh (vector plus immediate) - gather prefetch halfwords (vector plus immediate) - Gather prefetch of  halfwords from the active memory addresses generated by a  vector base plus immediate index. The index is a multiple of 2 in the range 0 to 62. Inactive addresses are not prefetched from memory. The <prfop> symbol specifies the prefetch hint as a combination of three options: access type PLD for load or PST for store; target cache level L1, L2 or L3; temporality (KEEP for temporal or STRM for non-temporal). is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000100100.....111........0....
       sz  imm5    Pg Zn    rfop
11000100100.....111........0....
       sz  imm5    Pg Zn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 62, defaulting to 0, encoded in the "imm5" field.

prfw (scalar plus immediate) - contiguous prefetch words (immediate index) - Contiguous prefetch of word elements from the memory address generated by a 64-bit scalar base and immediate index in the range -32 to 31 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.
1000010111......010........0....
          imm6   szPg Rn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -32 to 31, defaulting to 0, encoded in the "imm6" field.

prfw (scalar plus scalar) - contiguous prefetch words (scalar index) - Contiguous prefetch of word elements from the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 4 and added to the base address. After each     element prefetch     the index value is incremented,     but the index register is not updated.
10000101000!= 11111!= 11111!= 11111!= 11111!= 11111110........0....
       sz  Rm      Pg Rn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

prfw (scalar plus vector) - gather prefetch words (scalar plus vector) - Gather prefetch of  words from the active memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then multiplied by 4. Inactive addresses are not prefetched from memory. The <prfop> symbol specifies the prefetch hint as a combination of three options: access type PLD for load or PST for store; target cache level L1, L2 or L3; temporality (KEEP for temporal or STRM for non-temporal). is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
100001000.1.....010........0....
         s Zm    szPg Rn    rfop
110001000.1.....010........0....
         s Zm    szPg Rn    rfop
11000100011.....110........0....
           Zm    szPg Rn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

prfw (vector plus immediate) - gather prefetch words (vector plus immediate) - Gather prefetch of  words from the active memory addresses generated by a  vector base plus immediate index. The index is a multiple of 4 in the range 0 to 124. Inactive addresses are not prefetched from memory. The <prfop> symbol specifies the prefetch hint as a combination of three options: access type PLD for load or PST for store; target cache level L1, L2 or L3; temporality (KEEP for temporal or STRM for non-temporal). is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
10000101000.....111........0....
       sz  imm5    Pg Zn    rfop
11000101000.....111........0....
       sz  imm5    Pg Zn    rfop
 <prfop>
 prfop | <prfop>
 0000 | PLDL1KEEP
 0001 | PLDL1STRM
 0010 | PLDL2KEEP
 0011 | PLDL2STRM
 0100 | PLDL3KEEP
 0101 | PLDL3STRM
 x11x | #uimm4
 1000 | PSTL1KEEP
 1001 | PSTL1STRM
 1010 | PSTL2KEEP
 1011 | PSTL2STRM
 1100 | PSTL3KEEP
 1101 | PSTL3STRM
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 124, defaulting to 0, encoded in the "imm5" field.

psel - predicate select between predicate register or all-false - If the indexed element of the second source predicate is true, place the contents of the first source predicate register into the destination predicate register, otherwise set the destination predicate to all-false. The indexed element is determined by the sum of a general-purpose index register and an immediate, modulo the number of elements. Does not set the condition flags. For programmer convenience, an assembler must       also accept predicate-as-counter register names for the destination       predicate register and the first source predicate register.
00100101..1.....01....0....0....
        1h szlRv  Pn  SPm   Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.
 <T>
 tszh | tszl | <T>
 0 | 000 | RESERVED
 x | xx1 | B
 x | x10 | H
 x | 100 | S
 1 | 000 | D
 <Wv>:32-bit name of the vector select register W12-W15, encoded in the "Rv" field.
 <imm>:element index, in the range 0 to one less than the number of vector elements in a 128-bit vector register, encoded in "i1:tszh:tszl".

ptest - set condition flags for predicate - Sets the First (N), None (Z), !Last (C) condition flags based on the predicate source register, and the V flag to zero.
001001010101000011....0....00000
        pS        Pg   Pn   opc2
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.

ptrue (predicate as counter) - initialise predicate-as-counter to all active - Set the destination predicate as all-active elements, using the predicate-as-counter encoding.
00100101..1000000111100000010...
        ze                   PNd
 <PNd>:name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

ptrue (predicate) - initialise predicate from named constraint - Set elements of the destination predicate to true if the element number satisfies the named predicate constraint, or to false otherwise.  If the constraint specifies more elements than are available at the current vector length then all elements of the destination predicate are set to false. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception. Does not set the condition flags.
00100101..011000111000.....0....
        ze     S      ttern Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL

ptrues - initialise predicate from named constraint and set the condition flags - Set elements of the destination predicate to true if the element number satisfies the named predicate constraint, or to false otherwise.  If the constraint specifies more elements than are available at the current vector length then all elements of the destination predicate are set to false. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..011001111000.....0....
        ze     S      ttern Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL

punpkhi, punpklo - unpack and widen half of predicate - Unpack elements from the lowest or highest half of the source predicate and place in elements of twice their size within the destination predicate.  is unpredicated.
00000101001100010100000....0....
               H       Pn   Pd  
00000101001100000100000....0....
               H       Pn   Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.

raddhnb - rounding add narrow high part (bottom) - Add each vector element of the first source vector to the corresponding vector element of the second source vector, and place the most significant rounded half of the result in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. is unpredicated.
01000101..1.....011010..........
        ze Zm      SRTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

raddhnt - rounding add narrow high part (top) - Add each vector element of the first source vector to the corresponding vector element of the second source vector, and place the most significant rounded half of the result in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. is unpredicated.
01000101..1.....011011..........
        ze Zm      SRTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

rax1 - bitwise rotate left by 1 and exclusive-or - Rotate each 64-bit element of the second source vector left by 1 and exclusive-OR with the corresponding elements of the first source vector. The results are placed in the corresponding elements of the destination vector. is unpredicated. ID_AA64ZFR0_EL1.SHA3 indicates whether this instruction is implemented. is illegal when       executed in Streaming SVE mode, unless FEAT_SME_FA64 is       implemented and enabled, or FEAT_SME2p1 is implemented.
01000101001.....111101..........
        ze Zm        pZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

rbit - reverse bits (predicated) - Reverse bits in each active element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
00000101..100111100.............
        ze    pc  ZPg Zn   Zd   
00000101..100111101.............
        ze    pc  ZPg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

rdffr (predicated) - return predicate of succesfully loaded elements - Read the first-fault register (FFR) and place active elements in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
00100101000110001111000....0....
        pS             Pg   Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.

rdffr (unpredicated) - read the first-fault register - Read the first-fault register (FFR) and place in the destination predicate without predication. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
0010010100011001111100000000....
        pS                  Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.

rdffrs - return predicate of succesfully loaded elements, setting the condition flags - Read the first-fault register (FFR) and place active elements in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
00100101010110001111000....0....
        pS             Pg   Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.

rdvl - read multiple of vector register size to scalar register - Multiply the current vector register size in bytes by an immediate in the range -32 to 31 and place the result in the 64-bit destination general-purpose register.
000001001011111101010...........
         p opc2      imm6  Rd   
 <Xd>:64-bit name of the destination general-purpose register, encoded in the "Rd" field.
 <imm>:signed immediate operand, in the range -32 to 31, encoded in the "imm6" field.

rev (predicate) - reverse all elements in a predicate - Reverse the order of all elements in the source predicate and place in the destination predicate. is unpredicated.
00000101..1101000100000....0....
        ze             Pn   Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.

rev (vector) - reverse all elements in a vector (unpredicated) - Reverse the order of all elements in the source vector and place in the destination vector. is unpredicated.
00000101..111000001110..........
        ze            Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

revb, revh, revw - reverse bytes / halfwords / words within elements (predicated) - Reverse the order of 8-bit bytes, 16-bit halfwords or 32-bit words within each active element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
00000101..100100100.............
        ze    pc  ZPg Zn   Zd   
00000101..100100101.............
        ze    pc  ZPg Zn   Zd   
00000101..100101100.............
        ze    pc  ZPg Zn   Zd   
00000101..100101101.............
        ze    pc  ZPg Zn   Zd   
00000101..100110100.............
        ze    pc  ZPg Zn   Zd   
00000101..100110101.............
        ze    pc  ZPg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <T>
 size<0> | <T>
 0 | S
 1 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

revd - reverse 64-bit doublewords in elements (predicated) - Reverse the order of 64-bit doublewords within each active element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
0000010100101110100.............
        ze        ZPg Zn   Zd   
0000010100101110101.............
        ze        ZPg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

rshrnb - rounding shift right narrow by immediate (bottom) - Shift each unsigned integer value in the source vector elements right by an immediate value, and place the rounded results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....000110..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

rshrnt - rounding shift right narrow by immediate (top) - Shift each unsigned integer value in the source vector elements right by an immediate value, and place the rounded results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....000111..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

rsubhnb - rounding subtract narrow high part (bottom) - Subtract each vector element of the second source vector from the corresponding vector element in the first source vector, and place the most significant rounded half of the result in the even-numbered half-width destination elements, while setting the odd-numbered half-width destination elements to zero. is unpredicated.
01000101..1.....011110..........
        ze Zm      SRTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

rsubhnt - rounding subtract narrow high part (top) - Subtract each vector element of the second source vector from the corresponding vector element in the first source vector, and place the most significant rounded half of the result in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. is unpredicated.
01000101..1.....011111..........
        ze Zm      SRTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

saba - signed absolute difference and accumulate - Compute the absolute difference between signed integer values in elements of the second source vector and corresponding elements of the first source vector, and add the difference to the corresponding elements of the destination vector. is unpredicated.
01000101..0.....111110..........
        ze Zm        UZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sabalb - signed absolute difference and accumulate long (bottom) - Compute the absolute difference between even-numbered signed integer values in elements of the second source vector and corresponding elements of the first source vector, and destructively add to the overlapping double-width elements of the addend vector. is unpredicated.
01000101..0.....110000..........
        ze Zm       UTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sabalt - signed absolute difference and accumulate long (top) - Compute the absolute difference between odd-numbered signed elements of the second source vector and corresponding elements of the first source vector, and destructively add to the overlapping double-width elements of the addend vector. is unpredicated.
01000101..0.....110001..........
        ze Zm       UTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sabd - signed absolute difference (predicated) - Compute the absolute difference between signed integer values in active elements of the second source vector and corresponding elements of the first source vector and destructively place the difference in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..001100000.............
        ze   pcU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sabdlb - signed absolute difference long (bottom) - Compute the absolute difference between even-numbered signed integer values in elements of the second source vector and corresponding elements of the first source vector, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....001100..........
        ze Zm     pSUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sabdlt - signed absolute difference long (top) - Compute the absolute difference between odd-numbered signed integer values in elements of the second source vector and corresponding elements of the first source vector, and place the results in overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....001101..........
        ze Zm     pSUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sadalp - signed add and accumulate long pairwise - Add pairs of adjacent signed integer values and accumulate the results into the overlapping double-width elements of the destination vector.
01000100..000100101.............
        ze     U   Pg Zn   Zda  
 <Zda>:name of the second source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S

saddlb - signed add long (bottom) - Add the corresponding even-numbered signed elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....000000..........
        ze Zm     pSUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

saddlbt - signed add long (bottom + top) - Add the even-numbered signed elements of the first source vector to the odd-numbered signed elements of the second source vector, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....100000..........
        ze Zm       SbZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

saddlt - signed add long (top) - Add the corresponding odd-numbered signed elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....000001..........
        ze Zm     pSUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

saddv - signed add reduction to scalar - Signed add horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register. Narrow elements are first sign-extended to 64 bits. Inactive elements in the source vector are treated as zero.
00000100..000000001.............
        ze    pU   Pg Zn   Vd   
 <Dd>:64-bit name of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | RESERVED

saddwb - signed add wide (bottom) - Add the even-numbered signed elements of the second source vector to the overlapping double-width elements of the first source vector and place the results in the corresponding double-width elements of the destination vector.  is unpredicated.
01000101..0.....010000..........
        ze Zm      SUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S

saddwt - signed add wide (top) - Add the odd-numbered signed elements of the second source vector to the overlapping double-width elements of the first source vector and place the results in the corresponding double-width elements of the destination vector.  is unpredicated.
01000101..0.....010001..........
        ze Zm      SUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S

sbclb - subtract with carry long (bottom) - Subtract the even-numbered elements of the first source vector and the inverted 1-bit carry from the least-significant bit of the odd-numbered elements of the second source vector from the even-numbered elements of the destination and accumulator vector. The 1-bit carry output is placed in the corresponding odd-numbered element of the destination vector.
010001011.0.....110100..........
         z Zm        TZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 sz | <T>
 0 | S
 1 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sbclt - subtract with carry long (top) - Subtract the odd-numbered elements of the first source vector and the inverted 1-bit carry from the least-significant bit of the odd-numbered elements of the second source vector from the even-numbered elements of the destination and accumulator vector. The 1-bit carry output is placed in the corresponding odd-numbered element of the destination vector.
010001011.0.....110101..........
         z Zm        TZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 sz | <T>
 0 | S
 1 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sclamp - signed clamp to minimum/maximum vector - Clamp each signed element in the destination vector to between the signed minimum value in the corresponding element of the first source vector and the signed maximum value in the corresponding element of the second source vector and destructively write the results in the corresponding elements of the destination vector. is unpredicated.
01000100..0.....110000..........
        ze Zm        UZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

scvtf - signed integer convert to floating-point (predicated) - Convert to floating-point from the signed integer in each active element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. If the input and result types have a different size the smaller type is held unpacked in the least significant bits of elements of the larger size. When the input is the smaller type the upper bits of each source element are ignored. When the result is the smaller type the results are zero-extended to fill each destination element.
0110010101010010101.............
        pc   c2U   Pg Zn   Zd   
0110010001011100110.............
        pc     2 3UPg Zn   Zd   
0110010101010100101.............
        pc   c2U   Pg Zn   Zd   
0110010001011101100.............
        pc     2 3UPg Zn   Zd   
0110010110010100101.............
        pc   c2U   Pg Zn   Zd   
0110010010011101100.............
        pc     2 3UPg Zn   Zd   
0110010111010000101.............
        pc   c2U   Pg Zn   Zd   
0110010011011100100.............
        pc     2 3UPg Zn   Zd   
0110010101010110101.............
        pc   c2U   Pg Zn   Zd   
0110010001011101110.............
        pc     2 3UPg Zn   Zd   
0110010111010100101.............
        pc   c2U   Pg Zn   Zd   
0110010011011101100.............
        pc     2 3UPg Zn   Zd   
0110010111010110101.............
        pc   c2U   Pg Zn   Zd   
0110010011011101110.............
        pc     2 3UPg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

sdiv - signed divide (predicated) - Signed divide active elements of the first source vector by corresponding elements of the second source vector and destructively place the quotient in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..010100000.............
        ze    RU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size<0> | <T>
 0 | S
 1 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sdivr - signed reversed divide (predicated) - Signed reversed divide active elements of the second source vector by corresponding elements of the first source vector and destructively place the quotient in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..010110000.............
        ze    RU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size<0> | <T>
 0 | S
 1 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sdot (2-way, indexed) - signed integer indexed dot product - The signed  integer indexed dot product instruction computes the dot product of a group of two signed 16-bit integer values held in each 32-bit element of the first source vector multiplied by a group of two signed 16-bit integer values in an indexed 32-bit element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit element of the destination vector. The groups within the second source vector are specified using an immediate index which selects the same group position within each 128-bit vector segment.  The index range is from 0 to 3. is unpredicated.
01000100100.....110010..........
           i2Zm      UZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index of a group of two 16-bit elements within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.

sdot (2-way, vectors) - signed integer dot product - The signed  integer  dot product instruction computes the dot product of a group of two signed 16-bit integer values held in each 32-bit element of the first source vector multiplied by a group of two signed 16-bit integer values in the corresponding 32-bit element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit element of the destination vector. is unpredicated.
01000100000.....110010..........
           Zm        UZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sdot (4-way, indexed) - signed integer indexed dot product - The signed  integer indexed dot product instruction computes the dot product of a group of four signed 8-bit or 16-bit integer values held in each 32-bit or 64-bit element of the first source vector multiplied by a group of four signed 8-bit or 16-bit integer values in an indexed 32-bit or 64-bit element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit or 64-bit element of the destination vector. The groups within the second source vector are specified using an immediate index which selects the same group position within each 128-bit vector segment.  The index range is from 0 to one less than the number of groups per                         128-bit segment, encoded in 1 to 2 bits                         depending on the size of the group. is unpredicated.
01000100101.....000000..........
        ze i2Zm      UZn   Zda  
01000100111.....000000..........
        ze 1Zm       UZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the immediate index of a 32-bit group of four 8-bit values within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "64-bit" variant: is the immediate index of a 64-bit group of four 16-bit values within each 128-bit vector segment, in the range 0 to 1, encoded in the "i1" field.

sdot (4-way, vectors) - signed integer dot product - The signed  integer  dot product instruction computes the dot product of a group of four signed 8-bit or 16-bit integer values held in each 32-bit or 64-bit element of the first source vector multiplied by a group of four signed 8-bit or 16-bit integer values in the corresponding 32-bit or 64-bit element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit or 64-bit element of the destination vector. is unpredicated.
01000100..0.....000000..........
        ze Zm        UZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size<0> | <T>
 0 | S
 1 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size<0> | <Tb>
 0 | B
 1 | H
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sel (predicates) - conditionally select elements from two predicates - Read active elements from the first source predicate and inactive elements from the second source predicate and place in the corresponding elements of the destination predicate. Does not set the condition flags.
001001010000....01....1....1....
        pS  Pm    Pg  2Pn  3Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <Pg>:name of the governing scalable predicate register, encoded in the "Pg" field.
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

sel (vectors) - conditionally select elements from two vectors - Select elements from the first source vector where the corresponding vector select predicate element is true, and from the second source vector where the predicate element is false, placing them in the corresponding elements of the destination vector.
00000101..1.....11..............
        ze Zm     Pv  Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pv>:name of the vector select predicate register, encoded in the "Pv" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

setffr - initialise the first-fault register to all true - Initialise the first-fault register (FFR) to all true prior to a sequence of first-fault or non-fault loads.  is unpredicated. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
00100101001011001001000000000000
        pc                      


shadd - signed halving addition - Add active signed elements of the first source vector to corresponding signed elements of the second source vector, shift right one bit, and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01000100..010000100.............
        ze   RSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

shrnb - shift right narrow by immediate (bottom) - Shift each unsigned integer value in the source vector elements right by an immediate value, and place the truncated results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....000100..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

shrnt - shift right narrow by immediate (top) - Shift each unsigned integer value in the source vector elements right by an immediate value, and place the truncated results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....000101..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

shsub - signed halving subtract - Subtract active signed elements of the second source vector from corresponding signed elements of the first source vector, shift right one bit, and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01000100..010010100.............
        ze   RSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

shsubr - signed halving subtract reversed vectors - Subtract active signed elements of the first source vector from corresponding signed elements of the second source vector, shift right one bit, and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01000100..010110100.............
        ze   RSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sli - shift left and insert (immediate) - Shift each source vector element left by an immediate value, and insert the result into the corresponding vector element in the destination vector register, merging the shifted bits from each source element with existing bits in each destination vector element. The immediate shift amount is an unsigned value in the range 0 to number of bits per element minus 1. is unpredicated.
01000101..0.....111101..........
        zh zlmm3     pZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <const>:immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3".

sm4e - sm4 encryption and decryption - The SM4E instruction reads 16 bytes of input data from each 128-bit segment of the first source vector, together with four iterations of 32-bit round keys from the corresponding 128-bit segments of the second source vector. Each block of data is encrypted by four rounds in accordance with the SM4 standard, and destructively placed in the corresponding segments of the first source vector. is unpredicated. ID_AA64ZFR0_EL1.SM4 indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
0100010100100011111000..........
        ze     p     2Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sm4ekey - sm4 key updates - The SM4EKEY instruction reads four rounds of 32-bit input key values from each 128-bit segment of the first source vector, along with four rounds of 32-bit constants from the corresponding 128-bit segment of the second source vector. The four rounds of output key values are derived in accordance with the SM4 standard, and placed in the corresponding segments of the destination vector. is unpredicated. ID_AA64ZFR0_EL1.SM4 indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01000101001.....111100..........
        ze Zm        pZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

smax (immediate) - signed maximum with immediate (unpredicated) - Determine the signed maximum of an immediate and each element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate is a signed 8-bit value in the range -128 to +127, inclusive. is unpredicated.
00100101..101000110.............
        ze     U  2imm8    Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm>:signed immediate operand, in the range -128 to 127, encoded in the "imm8" field.

smax (vectors) - signed maximum vectors (predicated) - Determine the signed maximum of active elements of the second source vector and corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..001000000.............
        ze   pcU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

smaxp - signed maximum pairwise - Compute the maximum value of each pair of adjacent signed integer elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector.
01000100..010100101.............
        ze   pcU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

smaxqv - signed maximum reduction of quadword vector segments - Signed maximum of the same element numbers from each 128-bit source vector segment, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as the minimum signed integer for the element size.
00000100..001100001.............
        ze    pU   Pg Zn   Vd   
 <Vd>:name of the destination SIMD&FP register, encoded in the "Vd" field.
 <T>
 size | <T>
 00 | 16B
 01 | 8H
 10 | 4S
 11 | 2D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | B
 01 | H
 10 | S
 11 | D

smaxv - signed maximum reduction to scalar - Signed maximum horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register.  Inactive elements in the source vector are treated as the minimum signed integer for the element size.
00000100..001000001.............
        ze    pU   Pg Zn   Vd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

smin (immediate) - signed minimum with immediate (unpredicated) - Determine the signed minimum of an immediate and each element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate is a signed 8-bit value in the range -128 to +127, inclusive. is unpredicated.
00100101..101010110.............
        ze     U  2imm8    Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm>:signed immediate operand, in the range -128 to 127, encoded in the "imm8" field.

smin (vectors) - signed minimum vectors (predicated) - Determine the signed minimum of active elements of the second source vector and corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..001010000.............
        ze   pcU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sminp - signed minimum pairwise - Compute the minimum value of each pair of adjacent signed integer elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector.
01000100..010110101.............
        ze   pcU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sminqv - signed minimum reduction of quadword vector segments - Signed minimum of the same element numbers from each 128-bit source vector segment, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as the maximum signed integer for the element size.
00000100..001110001.............
        ze    pU   Pg Zn   Vd   
 <Vd>:name of the destination SIMD&FP register, encoded in the "Vd" field.
 <T>
 size | <T>
 00 | 16B
 01 | 8H
 10 | 4S
 11 | 2D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | B
 01 | H
 10 | S
 11 | D

sminv - signed minimum reduction to scalar - Signed minimum horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register.  Inactive elements in the source vector are treated as the maximum signed integer for the element size.
00000100..001010001.............
        ze    pU   Pg Zn   Vd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

smlalb (indexed) - signed multiply-add long to accumulator (bottom, indexed) - Multiply the even-numbered signed elements within each 128-bit segment of the first source vector by the specified signed element in the corresponding second source vector segment and destructively add to the overlapping double-width elements of the addend vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....1000.0..........
        ze 3hZm   SUlTZn   Zda  
01000100111.....1000.0..........
        ze hZm    SUlTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

smlalb (vectors) - signed multiply-add long to accumulator (bottom) - Multiply the corresponding even-numbered signed elements of the first and second source vectors and destructively add to the overlapping double-width elements of the addend vector. is unpredicated.
01000100..0.....010000..........
        ze Zm      SUTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

smlalt (indexed) - signed multiply-add long to accumulator (top, indexed) - Multiply the odd-numbered signed elements within each 128-bit segment of the first source vector by the specified signed element in the corresponding second source vector segment and destructively add to the overlapping double-width elements of the addend vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....1000.1..........
        ze 3hZm   SUlTZn   Zda  
01000100111.....1000.1..........
        ze hZm    SUlTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

smlalt (vectors) - signed multiply-add long to accumulator (top) - Multiply the corresponding odd-numbered signed elements of the first and second source vectors and destructively add to the overlapping double-width elements of the addend vector. is unpredicated.
01000100..0.....010001..........
        ze Zm      SUTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

smlslb (indexed) - signed multiply-subtract long from accumulator (bottom, indexed) - Multiply the even-numbered signed elements within each 128-bit segment of the first source vector by the specified signed element in the corresponding second source vector segment and destructively subtract from the overlapping double-width elements of the addend vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....1010.0..........
        ze 3hZm   SUlTZn   Zda  
01000100111.....1010.0..........
        ze hZm    SUlTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

smlslb (vectors) - signed multiply-subtract long from accumulator (bottom) - Multiply the corresponding even-numbered signed elements of the first and second source vectors and destructively subtract from the overlapping double-width elements of the addend vector. is unpredicated.
01000100..0.....010100..........
        ze Zm      SUTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

smlslt (indexed) - signed multiply-subtract long from accumulator (top, indexed) - Multiply the odd-numbered signed elements within each 128-bit segment of the first source vector by the specified signed element in the corresponding second source vector segment and destructively subtract from the overlapping double-width elements of the addend vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....1010.1..........
        ze 3hZm   SUlTZn   Zda  
01000100111.....1010.1..........
        ze hZm    SUlTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

smlslt (vectors) - signed multiply-subtract long from accumulator (top) - Multiply the corresponding odd-numbered signed elements of the first and second source vectors and destructively subtract from the overlapping double-width elements of the addend vector. is unpredicated.
01000100..0.....010101..........
        ze Zm      SUTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

smmla - signed integer matrix multiply-accumulate - The signed  integer matrix multiply-accumulate instruction multiplies the 2×8 matrix of signed 8-bit integer values held in each 128-bit segment of the first source vector by the 8×2 matrix of signed 8-bit integer values in the corresponding segment of the second source vector. The resulting 2×2 widened 32-bit integer matrix product is then destructively added to the 32-bit integer matrix accumulator held in the corresponding segment of the addend and destination vector. This is equivalent to performing an 8-way dot product per destination element. is unpredicated. ID_AA64ZFR0_EL1.I8MM indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01000101000.....100110..........
        ns Zm         Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

smulh (predicated) - signed multiply returning high half (predicated) - Widening multiply signed integer values in active elements of the first source vector by corresponding elements of the second source vector and destructively place the high half of the result in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..010010000.............
        ze    HU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

smulh (unpredicated) - signed multiply returning high half (unpredicated) - Widening multiply signed integer values of all elements of the first source vector by corresponding elements of the second source vector and place the high half of the result in the corresponding elements of the destination vector. is unpredicated.
00000100..1.....011010..........
        ze Zm        UZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

smullb (indexed) - signed multiply long (bottom, indexed) - Multiply the even-numbered signed elements within each 128-bit segment of the first source vector by the specified signed element in the corresponding second source vector segment, and place the results in the overlapping double-width elements of the destination vector register. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....1100.0..........
        ze 3hZm    UlTZn   Zd   
01000100111.....1100.0..........
        ze hZm     UlTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

smullb (vectors) - signed multiply long (bottom) - Multiply the corresponding even-numbered signed elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....011100..........
        ze Zm      pUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

smullt (indexed) - signed multiply long (top, indexed) - Multiply the odd-numbered signed elements within each 128-bit segment of the first source vector by the specified element in the corresponding second source vector segment, and place the results in the overlapping double-width elements of the destination vector register. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....1100.1..........
        ze 3hZm    UlTZn   Zd   
01000100111.....1100.1..........
        ze hZm     UlTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

smullt (vectors) - signed multiply long (top) - Multiply the corresponding odd-numbered signed elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....011101..........
        ze Zm      pUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

splice - splice two vectors under predicate control - Select a region from the first source vector and copy it to the lowest-numbered elements of the result. Then set any remaining elements of the result to a copy of the lowest-numbered elements from the second source vector. The region is selected using the first and last true elements in the vector select predicate register. The result is placed destructively in the destination and first source vector,    or constructively in the destination vector.
00000101..101101100.............
        ze         Pv Zn   Zd   
00000101..101100100.............
        ze         Pv Zm   Zdn  
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pv>:name of the vector select predicate register P0-P7, encoded in the "Pv" field.
 <Zn1>:name of the first scalable vector register of the source multi-vector group, encoded in the "Zn" field.
 <Zn2>:name of the second scalable vector register of the source multi-vector group, encoded in the "Zn" field.
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqabs - signed saturating absolute value - Compute the absolute value of the signed integer in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
01000100..001000101.............
        ze  Q Zp   Pg Zn   Zd   
01000100..001010101.............
        ze  Q Zp   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

sqadd (immediate) - signed saturating add immediate (unpredicated) - Signed saturating add of an unsigned immediate to each element of the source vector, and destructively place the results in the corresponding elements of the  source vector. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated. The immediate is an unsigned value in the range 0 to 255, and for element widths of 16 bits or higher it may also be a positive multiple of 256 in the range 256 to 65280. The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<uimm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".
00100101..10010011..............
        ze     U  himm8    Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm>:Is an unsigned immediate in the range 0 to 255, encoded in the "imm8" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #8

sqadd (vectors, predicated) - signed saturating addition (predicated) - Add active signed elements of the first source vector to corresponding signed elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. Inactive elements in the destination vector register remain unmodified.
01000100..011000100.............
        ze   pSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqadd (vectors, unpredicated) - signed saturating add vectors (unpredicated) - Signed saturating add all elements of the second source vector to corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated.
00000100..1.....000100..........
        ze Zm        UZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqcadd - saturating complex integer add with rotate - Add the real and imaginary components of the integral complex numbers from the first source vector to the complex numbers from the second source vector which have first been rotated by 90 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation, equivalent to multiplying the complex numbers in the second source vector by ±j beforehand. Destructively place the results in the corresponding elements of the first source vector. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated. Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.
01000101..00000111011...........
        ze     p     tZm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <const>
 rot | <const>
 0 | #90
 1 | #270

sqcvtn - signed saturating extract narrow and interleave - Saturate the signed integer value in each element of the group of two source vectors to half the original source element width, and place the two-way interleaved results in the half-width destination elements. is unpredicated.
0100010100110001010000....0.....
         h zl       U Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn1>:name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.
 <Zn2>:name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.

sqcvtun - signed saturating unsigned extract narrow and interleave - Saturate the signed integer value in each element of the group of two source vectors to unsigned integer value that is half the original source element width, and place the two-way interleaved results in the half-width destination elements. is unpredicated.
0100010100110001010100....0.....
         h zl      pc Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn1>:name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.
 <Zn2>:name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.

sqdecb - signed saturating decrement scalar by multiple of 8-bit predicate constraint element count - Determines the number of active 8-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement the   scalar destination. The   result is   saturated to the      source general-purpose register's   signed integer range.   A 32-bit saturated result is then sign-extended to 64 bits. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001000010....111110..........
        ze fimm4    DUtternRdn  
000001000011....111110..........
        ze fimm4    DUtternRdn  
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

sqdecd (scalar) - signed saturating decrement scalar by multiple of 64-bit predicate constraint element count - Determines the number of active 64-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement the   scalar destination. The   result is   saturated to the      source general-purpose register's   signed integer range.   A 32-bit saturated result is then sign-extended to 64 bits. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001110....111110..........
        ze fimm4    DUtternRdn  
000001001111....111110..........
        ze fimm4    DUtternRdn  
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

sqdecd (vector) - signed saturating decrement vector by multiple of 64-bit predicate constraint element count - Determines the number of active 64-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement all destination vector elements. The   results are   saturated to the   64-bit    signed integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001110....110010..........
        ze  imm4    DUtternZdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

sqdech (scalar) - signed saturating decrement scalar by multiple of 16-bit predicate constraint element count - Determines the number of active 16-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement the   scalar destination. The   result is   saturated to the      source general-purpose register's   signed integer range.   A 32-bit saturated result is then sign-extended to 64 bits. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001000110....111110..........
        ze fimm4    DUtternRdn  
000001000111....111110..........
        ze fimm4    DUtternRdn  
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

sqdech (vector) - signed saturating decrement vector by multiple of 16-bit predicate constraint element count - Determines the number of active 16-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement all destination vector elements. The   results are   saturated to the   16-bit    signed integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001000110....110010..........
        ze  imm4    DUtternZdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

sqdecp (scalar) - signed saturating decrement scalar by count of true predicate elements - Counts the number of true elements in the source predicate and then uses the result to decrement the   scalar destination. The   result is   saturated to the      source general-purpose register's   signed integer range.   A 32-bit saturated result is then sign-extended to 64 bits.
00100101..1010101000100.........
        ze    DU     fpPm  Rdn  
00100101..1010101000110.........
        ze    DU     fpPm  Rdn  
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <Pm>:name of the source scalable predicate register, encoded in the "Pm" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

sqdecp (vector) - signed saturating decrement vector by count of true predicate elements - Counts the number of true elements in the source predicate and then uses the result to decrement all destination vector elements. The   results are   saturated to the   element    signed integer range. The predicate size specifier may be omitted in assembler    source code, but this is deprecated and will be    prohibited in a future release of the architecture.
00100101..1010101000000.........
        ze    DU     pcPm  Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pm>:name of the source scalable predicate register, encoded in the "Pm" field.

sqdecw (scalar) - signed saturating decrement scalar by multiple of 32-bit predicate constraint element count - Determines the number of active 32-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement the   scalar destination. The   result is   saturated to the      source general-purpose register's   signed integer range.   A 32-bit saturated result is then sign-extended to 64 bits. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001010....111110..........
        ze fimm4    DUtternRdn  
000001001011....111110..........
        ze fimm4    DUtternRdn  
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

sqdecw (vector) - signed saturating decrement vector by multiple of 32-bit predicate constraint element count - Determines the number of active 32-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement all destination vector elements. The   results are   saturated to the   32-bit    signed integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001010....110010..........
        ze  imm4    DUtternZdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

sqdmlalb (indexed) - signed saturating doubling multiply-add long to accumulator (bottom, indexed) - Multiply then double the even-numbered signed elements within each 128-bit segment of the first source vector and specified signed element in the corresponding second source vector segment. Each intermediate value is saturated to the double-width N-bit value's signed integer range -2(N-1)  to (2(N-1))-1. Then destructively add to the overlapping double-width elements of the addend and destination vector. Each destination element is saturated to the double-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....0010.0..........
        ze 3hZm    SlTZn   Zda  
01000100111.....0010.0..........
        ze hZm     SlTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

sqdmlalb (vectors) - signed saturating doubling multiply-add long to accumulator (bottom) - Multiply then double the corresponding even-numbered signed elements of the first and second source vectors. Each intermediate value is saturated to the double-width N-bit value's signed integer range -2(N-1)  to (2(N-1))-1. Then destructively add to the overlapping double-width elements of the addend and destination vector. Each destination element is saturated to the double-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated.
01000100..0.....011000..........
        ze Zm       STZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqdmlalbt - signed saturating doubling multiply-add long to accumulator (bottom × top) - Multiply then double the corresponding even-numbered signed elements of the first and odd-numbered signed elements of the second source vector. Each intermediate value is saturated to the double-width N-bit value's signed integer range -2(N-1)  to (2(N-1))-1. Then destructively add to the overlapping double-width elements of the addend and destination vector. Each destination element is saturated to the double-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated.
01000100..0.....000010..........
        ze Zm        SZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqdmlalt (indexed) - signed saturating doubling multiply-add long to accumulator (top, indexed) - Multiply then double the odd-numbered signed elements within each 128-bit segment of the first source vector and the specified signed element in the corresponding second source vector segment. Each intermediate value is saturated to the double-width N-bit value's signed integer range -2(N-1)  to (2(N-1))-1. Then destructively add to the overlapping double-width elements of the addend and destination vector. Each destination element is saturated to the double-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....0010.1..........
        ze 3hZm    SlTZn   Zda  
01000100111.....0010.1..........
        ze hZm     SlTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

sqdmlalt (vectors) - signed saturating doubling multiply-add long to accumulator (top) - Multiply then double the corresponding odd-numbered signed elements of the first and second source vectors. Each intermediate value is saturated to the double-width N-bit value's signed integer range -2(N-1)  to (2(N-1))-1. Then destructively add to the overlapping double-width elements of the addend and destination vector. Each destination element is saturated to the double-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated.
01000100..0.....011001..........
        ze Zm       STZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqdmlslb (indexed) - signed saturating doubling multiply-subtract long from accumulator (bottom, indexed) - Multiply then double the even-numbered signed elements within each 128-bit segment of the first source vector and the specified signed element in the corresponding second source vector segment. Each intermediate value is saturated to the double-width N-bit value's signed integer range -2(N-1)  to (2(N-1))-1. Then destructively subtract from the overlapping double-width elements of the addend and destination vector. Each destination element is saturated to the double-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....0011.0..........
        ze 3hZm    SlTZn   Zda  
01000100111.....0011.0..........
        ze hZm     SlTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

sqdmlslb (vectors) - signed saturating doubling multiply-subtract long from accumulator (bottom) - Multiply then double the corresponding even-numbered signed elements of the first and second source vectors. Each intermediate value is saturated to the double-width N-bit value's signed integer range -2(N-1)  to (2(N-1))-1. Then destructively subtract from the overlapping double-width elements of the addend and destination vector. Each destination element is saturated to the double-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated.
01000100..0.....011010..........
        ze Zm       STZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqdmlslbt - signed saturating doubling multiply-subtract long from accumulator (bottom × top) - Multiply then double the corresponding even-numbered signed elements of the first and odd-numbered signed elements of the second source vector. Each intermediate value is saturated to the double-width N-bit value's signed integer range -2(N-1)  to (2(N-1))-1. Then destructively subtract from the overlapping double-width elements of the addend and destination vector. Each destination element is saturated to the double-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated.
01000100..0.....000011..........
        ze Zm        SZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqdmlslt (indexed) - signed saturating doubling multiply-subtract long from accumulator (top, indexed) - Multiply then double the odd-numbered signed elements within each 128-bit segment of the first source vector and the specified signed element in the corresponding second source vector segment. Each intermediate value is saturated to the double-width N-bit value's signed integer range -2(N-1)  to (2(N-1))-1. Then destructively subtract from the overlapping double-width elements of the addend and destination vector. Each destination element is saturated to the double-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....0011.1..........
        ze 3hZm    SlTZn   Zda  
01000100111.....0011.1..........
        ze hZm     SlTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

sqdmlslt (vectors) - signed saturating doubling multiply-subtract long from accumulator (top) - Multiply then double the corresponding odd-numbered signed elements of the first and second source vectors. Each intermediate value is saturated to the double-width N-bit value's signed integer range -2(N-1)  to (2(N-1))-1. Then destructively subtract from the overlapping double-width elements of the addend and destination vector. Each destination element is saturated to the double-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated.
01000100..0.....011011..........
        ze Zm       STZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqdmulh (indexed) - signed saturating doubling multiply high (indexed) - Multiply all signed elements within each 128-bit segment of the first source vector by the specified signed element in the corresponding second source vector segment, double and place the most significant half of the result in the corresponding elements of the destination vector register. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 1 to 3 bits                         depending on the size of the element.
010001000.1.....111100..........
         h 3lZm      RZn   Zd   
01000100101.....111100..........
        ze i2Zm      RZn   Zd   
01000100111.....111100..........
        ze 1Zm       RZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "16-bit" and "32-bit" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "16-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field.

sqdmulh (vectors) - signed saturating doubling multiply high (unpredicated) - Multiply then double the corresponding signed elements of the first and second source vectors, and place the most significant half of the results in the corresponding elements of the destination vector register. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated.
00000100..1.....011100..........
        ze Zm        RZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqdmullb (indexed) - signed saturating doubling multiply long (bottom, indexed) - Multiply then double the even-numbered signed elements within each 128-bit segment of the first source vector and the specified element in the corresponding second source vector segment, and place the results in overlapping double-width elements of the destination vector register. Each result element is saturated to the double-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....1110.0..........
        ze 3hZm     lTZn   Zd   
01000100111.....1110.0..........
        ze hZm      lTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

sqdmullb (vectors) - signed saturating doubling multiply long (bottom) - Multiply the corresponding even-numbered signed elements of the first and second source vectors, double and place the results in the overlapping double-width elements of the destination vector. Each result element is saturated to the double-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated.
01000101..0.....011000..........
        ze Zm      pUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqdmullt (indexed) - signed saturating doubling multiply long (top, indexed) - Multiply then double the odd-numbered signed elements within each 128-bit segment of the first source vector and the specified element in the corresponding second source vector segment, and place the results in overlapping double-width elements of the destination vector register. Each result element is saturated to the double-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....1110.1..........
        ze 3hZm     lTZn   Zd   
01000100111.....1110.1..........
        ze hZm      lTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

sqdmullt (vectors) - signed saturating doubling multiply long (top) - Multiply the corresponding odd-numbered signed elements of the first and second source vectors, double and place the results in the overlapping double-width elements of the destination vector. Each result element is saturated to the double-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated.
01000101..0.....011001..........
        ze Zm      pUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqincb - signed saturating increment scalar by multiple of 8-bit predicate constraint element count - Determines the number of active 8-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment the   scalar destination. The   result is   saturated to the      source general-purpose register's   signed integer range.   A 32-bit saturated result is then sign-extended to 64 bits. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001000010....111100..........
        ze fimm4    DUtternRdn  
000001000011....111100..........
        ze fimm4    DUtternRdn  
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

sqincd (scalar) - signed saturating increment scalar by multiple of 64-bit predicate constraint element count - Determines the number of active 64-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment the   scalar destination. The   result is   saturated to the      source general-purpose register's   signed integer range.   A 32-bit saturated result is then sign-extended to 64 bits. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001110....111100..........
        ze fimm4    DUtternRdn  
000001001111....111100..........
        ze fimm4    DUtternRdn  
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

sqincd (vector) - signed saturating increment vector by multiple of 64-bit predicate constraint element count - Determines the number of active 64-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment all destination vector elements. The   results are   saturated to the   64-bit    signed integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001110....110000..........
        ze  imm4    DUtternZdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

sqinch (scalar) - signed saturating increment scalar by multiple of 16-bit predicate constraint element count - Determines the number of active 16-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment the   scalar destination. The   result is   saturated to the      source general-purpose register's   signed integer range.   A 32-bit saturated result is then sign-extended to 64 bits. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001000110....111100..........
        ze fimm4    DUtternRdn  
000001000111....111100..........
        ze fimm4    DUtternRdn  
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

sqinch (vector) - signed saturating increment vector by multiple of 16-bit predicate constraint element count - Determines the number of active 16-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment all destination vector elements. The   results are   saturated to the   16-bit    signed integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001000110....110000..........
        ze  imm4    DUtternZdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

sqincp (scalar) - signed saturating increment scalar by count of true predicate elements - Counts the number of true elements in the source predicate and then uses the result to increment the   scalar destination. The   result is   saturated to the      source general-purpose register's   signed integer range.   A 32-bit saturated result is then sign-extended to 64 bits.
00100101..1010001000100.........
        ze    DU     fpPm  Rdn  
00100101..1010001000110.........
        ze    DU     fpPm  Rdn  
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <Pm>:name of the source scalable predicate register, encoded in the "Pm" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

sqincp (vector) - signed saturating increment vector by count of true predicate elements - Counts the number of true elements in the source predicate and then uses the result to increment all destination vector elements. The   results are   saturated to the   element    signed integer range. The predicate size specifier may be omitted in assembler    source code, but this is deprecated and will be    prohibited in a future release of the architecture.
00100101..1010001000000.........
        ze    DU     pcPm  Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pm>:name of the source scalable predicate register, encoded in the "Pm" field.

sqincw (scalar) - signed saturating increment scalar by multiple of 32-bit predicate constraint element count - Determines the number of active 32-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment the   scalar destination. The   result is   saturated to the      source general-purpose register's   signed integer range.   A 32-bit saturated result is then sign-extended to 64 bits. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001010....111100..........
        ze fimm4    DUtternRdn  
000001001011....111100..........
        ze fimm4    DUtternRdn  
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

sqincw (vector) - signed saturating increment vector by multiple of 32-bit predicate constraint element count - Determines the number of active 32-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment all destination vector elements. The   results are   saturated to the   32-bit    signed integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001010....110000..........
        ze  imm4    DUtternZdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

sqneg - signed saturating negate - Negate the signed integer value in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
01000100..001001101.............
        ze  Q Zp   Pg Zn   Zd   
01000100..001011101.............
        ze  Q Zp   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

sqrdcmlah (indexed) - saturating rounding doubling complex integer multiply-add high with rotate (indexed) - Multiply without saturation the duplicated real components for rotations 0 and 180, or imaginary components for rotations 90 and 270, of the integral numbers in each 128-bit segment of the first source vector by the specified complex number in the corresponding the second source vector segment rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation. Then double and add the products to the corresponding components of the complex numbers in the addend vector.  Destructively place the most significant rounded half of the results in the corresponding elements of the addend vector.  Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated. These transformations permit the creation of a variety of multiply-add and multiply-subtract operations on complex numbers by combining two of these instructions with the same vector operands but with rotations that are 90 degrees apart. Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.
01000100101.....0111............
        ze i2Zm     otZn   Zda  
01000100111.....0111............
        ze 1Zm      otZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "16-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "16-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field.
 <const>
 rot | <const>
 00 | #0
 01 | #90
 10 | #180
 11 | #270

sqrdcmlah (vectors) - saturating rounding doubling complex integer multiply-add high with rotate - Multiply without saturation the duplicated real components for rotations 0 and 180, or imaginary components for rotations 90 and 270, of the integral numbers in  the first source vector by the corresponding complex number in the second source vector  rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation. Then double and add the products to the corresponding components of the complex numbers in the addend vector.  Destructively place the most significant rounded half of the results in the corresponding elements of the addend vector.  Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated. These transformations permit the creation of a variety of multiply-add and multiply-subtract operations on complex numbers by combining two of these instructions with the same vector operands but with rotations that are 90 degrees apart. Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.
01000100..0.....0011............
        ze Zm      potZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <const>
 rot | <const>
 00 | #0
 01 | #90
 10 | #180
 11 | #270

sqrdmlah (indexed) - signed saturating rounding doubling multiply-add high to accumulator (indexed) - Multiply then double all signed elements within each 128-bit segment of the first source vector and the specified signed element of the corresponding second source vector segment, and destructively add the rounded high half of each result to the corresponding elements of the addend and destination vector. Each destination element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 1 to 3 bits                         depending on the size of the element.
010001000.1.....000100..........
         h 3lZm      SZn   Zda  
01000100101.....000100..........
        ze i2Zm      SZn   Zda  
01000100111.....000100..........
        ze 1Zm       SZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "16-bit" and "32-bit" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "16-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field.

sqrdmlah (vectors) - signed saturating rounding doubling multiply-add high to accumulator (unpredicated) - Multiply then double the corresponding signed elements of the first and second source vectors, and destructively add the rounded high half of each result to the corresponding elements of the addend and destination vector. Each destination element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated.
01000100..0.....011100..........
        ze Zm        SZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqrdmlsh (indexed) - signed saturating rounding doubling multiply-subtract high from accumulator (indexed) - Multiply then double all signed elements within each 128-bit segment of the first source vector and the specified signed element of the corresponding second source vector segment, and destructively subtract the rounded high half of each result to the corresponding elements of the addend and destination vector. Each destination element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 1 to 3 bits                         depending on the size of the element.
010001000.1.....000101..........
         h 3lZm      SZn   Zda  
01000100101.....000101..........
        ze i2Zm      SZn   Zda  
01000100111.....000101..........
        ze 1Zm       SZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "16-bit" and "32-bit" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "16-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field.

sqrdmlsh (vectors) - signed saturating rounding doubling multiply-subtract high from accumulator (unpredicated) - Multiply then double the corresponding signed elements of the first and second source vectors, and destructively subtract the rounded high half of each result from the corresponding elements of the addend and destination vector. Each destination element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated.
01000100..0.....011101..........
        ze Zm        SZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqrdmulh (indexed) - signed saturating rounding doubling multiply high (indexed) - Multiply all signed elements within each 128-bit segment of the first source vector by the specified signed element in the corresponding second source vector segment, double and place the most significant rounded half of the result in the corresponding elements of the destination vector register. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 1 to 3 bits                         depending on the size of the element.
010001000.1.....111101..........
         h 3lZm      RZn   Zd   
01000100101.....111101..........
        ze i2Zm      RZn   Zd   
01000100111.....111101..........
        ze 1Zm       RZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "16-bit" and "32-bit" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "16-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field.

sqrdmulh (vectors) - signed saturating rounding doubling multiply high (unpredicated) - Multiply then double the corresponding signed elements of the first and second source vectors, and place the most significant rounded half of the result in the corresponding elements of the destination vector. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated.
00000100..1.....011101..........
        ze Zm        RZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqrshl - signed saturating rounding shift left by vector (predicated) - Shift active signed elements of the first source vector by corresponding elements of the second source vector and destructively place the rounded results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. Inactive elements in the destination vector register remain unmodified.
01000100..001010100.............
        ze  QRNU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqrshlr - signed saturating rounding shift left reversed vectors (predicated) - Shift active signed elements of the second source vector by corresponding elements of the first source vector and destructively place the rounded results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. Inactive elements in the destination vector register remain unmodified.
01000100..001110100.............
        ze  QRNU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqrshrn - signed saturating rounding shift right narrow by immediate and interleave - Shift right by an immediate value, the signed integer value in each element of the group of two source vectors and place the two-way interleaved rounded results in the half-width destination elements. Each result element is saturated to the half-width N-bit element's signed integer range -2(N-1)  to (2(N-1) )-1. The immediate shift amount is an unsigned value in the range 1 to 16. is unpredicated.
010001011011....001010....0.....
         h limm4  pUR Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn1>:name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.
 <Zn2>:name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.
 <const>:immediate shift amount, in the range 1 to 16, encoded in the "imm4" field.

sqrshrnb - signed saturating rounding shift right narrow by immediate (bottom) - Shift each signed integer value in the source vector elements right by an immediate value, and place the rounded results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. Each result element is saturated to the half-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....001010..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

sqrshrnt - signed saturating rounding shift right narrow by immediate (top) - Shift each signed integer value in the source vector elements right by an immediate value, and place the rounded results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. Each result element is saturated to the half-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....001011..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

sqrshrun - signed saturating rounding shift right unsigned narrow by immediate and interleave - Shift right by an immediate value, the signed integer value in each element of the group of two source vectors and place the two-way interleaved rounded results in the half-width destination elements. Each result element is saturated to the half-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to 16. is unpredicated.
010001011011....000010....0.....
         h limm4  pUR Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn1>:name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.
 <Zn2>:name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.
 <const>:immediate shift amount, in the range 1 to 16, encoded in the "imm4" field.

sqrshrunb - signed saturating rounding shift right unsigned narrow by immediate (bottom) - Shift each signed integer value in the source vector elements right by an immediate value, and place the rounded results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. Each result element is saturated to the half-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....000010..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

sqrshrunt - signed saturating rounding shift right unsigned narrow by immediate (top) - Shift each signed integer value in the source vector elements right by an immediate value, and place the rounded results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. Each result element is saturated to the half-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....000011..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

sqshl (immediate) - signed saturating shift left by immediate - Shift left by immediate each active signed element of the source vector, and destructively place the results in the corresponding elements of the source vector. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. The immediate shift amount is an unsigned value in the range 0 to number of bits per element minus 1. Inactive elements in the destination vector register remain unmodified.
00000100..000110100.............
        zh  pcLU   Pg zlmm3Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>:immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3".

sqshl (vectors) - signed saturating shift left by vector (predicated) - Shift active signed elements of the first source vector by corresponding elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. Inactive elements in the destination vector register remain unmodified.
01000100..001000100.............
        ze  QRNU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqshlr - signed saturating shift left reversed vectors (predicated) - Shift active signed elements of the second source vector by corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. Inactive elements in the destination vector register remain unmodified.
01000100..001100100.............
        ze  QRNU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqshlu - signed saturating shift left unsigned by immediate - Shift left by immediate each active signed element of the source vector, and destructively place the results in the corresponding elements of the source vector. Each result element is saturated to the  N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 0 to number of bits per element minus 1. Inactive elements in the destination vector register remain unmodified.
00000100..001111100.............
        zh  pcLU   Pg zlmm3Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>:immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3".

sqshrnb - signed saturating shift right narrow by immediate (bottom) - Shift each signed integer value in the source vector elements right by an immediate value, and place the truncated results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. Each result element is saturated to the half-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....001000..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

sqshrnt - signed saturating shift right narrow by immediate (top) - Shift each signed integer value in the source vector elements right by an immediate value, and place the truncated results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. Each result element is saturated to the half-width N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....001001..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

sqshrunb - signed saturating shift right unsigned narrow by immediate (bottom) - Shift each signed integer value in the source vector elements right by an immediate value, and place the truncated results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. Each result element is saturated to the half-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....000000..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

sqshrunt - signed saturating shift right unsigned narrow by immediate (top) - Shift each signed integer value in the source vector elements right by an immediate value, and place the truncated results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. Each result element is saturated to the half-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....000001..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

sqsub (immediate) - signed saturating subtract immediate (unpredicated) - Signed saturating subtract of an unsigned immediate from each element of the source vector, and destructively place the results in the corresponding elements of the  source vector. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated. The immediate is an unsigned value in the range 0 to 255, and for element widths of 16 bits or higher it may also be a positive multiple of 256 in the range 256 to 65280. The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<uimm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".
00100101..10011011..............
        ze     U  himm8    Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm>:Is an unsigned immediate in the range 0 to 255, encoded in the "imm8" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #8

sqsub (vectors, predicated) - signed saturating subtraction (predicated) - Subtract active signed elements of the second source vector from corresponding signed elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. Inactive elements in the destination vector register remain unmodified.
01000100..011010100.............
        ze   pSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqsub (vectors, unpredicated) - signed saturating subtract vectors (unpredicated) - Signed saturating subtract all elements of the second source vector from corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. is unpredicated.
00000100..1.....000110..........
        ze Zm        UZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqsubr - signed saturating subtraction reversed vectors (predicated) - Subtract active signed elements of the first source vector from corresponding signed elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. Inactive elements in the destination vector register remain unmodified.
01000100..011110100.............
        ze   pSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sqxtnb - signed saturating extract narrow (bottom) - Saturate the signed integer value in each source element to half the original source element width, and place the results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero.
010001010.1..000010000..........
         h zl       UTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 10 | H
 0 | 11 | RESERVED
 1 | 00 | S
 1 | 01 | RESERVED
 1 | 1x | RESERVED
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 10 | S
 0 | 11 | RESERVED
 1 | 00 | D
 1 | 01 | RESERVED
 1 | 1x | RESERVED

sqxtnt - signed saturating extract narrow (top) - Saturate the signed integer value in each source element to half the original source element width, and place the results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged.
010001010.1..000010001..........
         h zl       UTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 10 | H
 0 | 11 | RESERVED
 1 | 00 | S
 1 | 01 | RESERVED
 1 | 1x | RESERVED
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 10 | S
 0 | 11 | RESERVED
 1 | 00 | D
 1 | 01 | RESERVED
 1 | 1x | RESERVED

sqxtunb - signed saturating unsigned extract narrow (bottom) - Saturate the signed integer value in each source element to an unsigned integer value that is half the original source element width, and place the results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero.
010001010.1..000010100..........
         h zl      pcTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 10 | H
 0 | 11 | RESERVED
 1 | 00 | S
 1 | 01 | RESERVED
 1 | 1x | RESERVED
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 10 | S
 0 | 11 | RESERVED
 1 | 00 | D
 1 | 01 | RESERVED
 1 | 1x | RESERVED

sqxtunt - signed saturating unsigned extract narrow (top) - Saturate the signed integer value in each source element to an unsigned integer value that is half the original source element width, and place the results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged.
010001010.1..000010101..........
         h zl      pcTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 10 | H
 0 | 11 | RESERVED
 1 | 00 | S
 1 | 01 | RESERVED
 1 | 1x | RESERVED
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 10 | S
 0 | 11 | RESERVED
 1 | 00 | D
 1 | 01 | RESERVED
 1 | 1x | RESERVED

srhadd - signed rounding halving addition - Add active signed elements of the first source vector to corresponding signed elements of the second source vector, shift right one bit, and destructively place the rounded results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01000100..010100100.............
        ze   RSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sri - shift right and insert (immediate) - Shift each source vector element right by an immediate value, and insert the result into the corresponding vector element in the destination vector register, merging the shifted bits from each source element with existing bits in each destination vector element. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
01000101..0.....111100..........
        zh zlmm3     pZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

srshl - signed rounding shift left by vector (predicated) - Shift active signed elements of the first source vector by corresponding elements of the second source vector and destructively place the rounded results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Inactive elements in the destination vector register remain unmodified.
01000100..000010100.............
        ze  QRNU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

srshlr - signed rounding shift left reversed vectors (predicated) - Shift active signed elements of the second source vector by corresponding elements of the first source vector and destructively place the rounded results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Inactive elements in the destination vector register remain unmodified.
01000100..000110100.............
        ze  QRNU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

srshr - signed rounding shift right by immediate - Shift right by immediate each active signed element of the source vector, and destructively place the rounded results in the corresponding elements of the source vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. Inactive elements in the destination vector register remain unmodified.
00000100..001100100.............
        zh  pcLU   Pg zlmm3Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

srsra - signed rounding shift right and accumulate (immediate) - Shift right by immediate each signed element of the source vector, preserving the sign bit, and add the rounded intermediate result destructively to the corresponding elements of the addend vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
01000101..0.....111010..........
        zh zlmm3    RUZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

sshllb - signed shift left long by immediate (bottom) - Shift left by immediate each even-numbered signed element of the source vector, and place the results in the overlapping double-width elements of the destination vector. The immediate shift amount is an unsigned value in the range 0 to number of bits per element minus 1. is unpredicated.
010001010.0.....101000..........
         h zlmm3    UTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <const>:immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3".

sshllt - signed shift left long by immediate (top) - Shift left by immediate each odd-numbered signed element of the source vector, and place the results in the overlapping double-width elements of the destination vector. The immediate shift amount is an unsigned value in the range 0 to number of bits per element minus 1. is unpredicated.
010001010.0.....101001..........
         h zlmm3    UTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <const>:immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3".

ssra - signed shift right and accumulate (immediate) - Shift right by immediate each signed element of the source vector, preserving the sign bit, and add the truncated intermediate result destructively to the corresponding elements of the addend vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
01000101..0.....111000..........
        zh zlmm3    RUZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

ssublb - signed subtract long (bottom) - Subtract the even-numbered signed elements of the second source vector from the corresponding signed elements of the first source vector, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....000100..........
        ze Zm     pSUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

ssublbt - signed subtract long (bottom - top) - Subtract the odd-numbered signed elements of the second source vector from the even-numbered signed elements of the first source vector, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....100010..........
        ze Zm       SbZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

ssublt - signed subtract long (top) - Subtract the odd-numbered signed elements of the second source vector from the corresponding signed elements of the first source vector, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....000101..........
        ze Zm     pSUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

ssubltb - signed subtract long (top - bottom) - Subtract the even-numbered signed elements of the second source vector from the odd-numbered signed elements of the first source vector, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....100011..........
        ze Zm       SbZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

ssubwb - signed subtract wide (bottom) - Subtract the even-numbered signed elements of the second source vector from the overlapping double-width elements of the first source vector and place the results in the corresponding double-width elements of the destination vector. is unpredicated.
01000101..0.....010100..........
        ze Zm      SUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S

ssubwt - signed subtract wide (top) - Subtract the even-numbered signed elements of the second source vector from the overlapping double-width elements of the first source vector and place the results in the corresponding double-width elements of the destination vector. is unpredicated.
01000101..0.....010101..........
        ze Zm      SUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S

st1b (scalar plus immediate, consecutive registers) - contiguous store of bytes from multiple consecutive vectors (immediate index) - Contiguous store of bytes from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements are not written to memory.
101000000110....000............0
            imm4 szPNgRn   Zt  N
101000000110....100...........00
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

st1b (scalar plus immediate, single register) - contiguous store bytes from vector (immediate index) - Contiguous store  of  bytes from elements of a vector register to the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements are not written to memory.
111001000..0....111.............
       szze imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

st1b (scalar plus scalar, consecutive registers) - contiguous store of bytes from multiple consecutive vectors (scalar index) - Contiguous store of bytes from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory.
10100000001.....000............0
           Rm    szPNgRn   Zt  N
10100000001.....100...........00
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

st1b (scalar plus scalar, single register) - contiguous store bytes from vector (scalar index) - Contiguous store  of  bytes from elements of a vector register to the memory address generated by a 64-bit scalar base and scalar index which is      added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements are not written to memory.
111001000..!= 11111!= 11111!= 11111!= 11111!= 11111010.............
         zeRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st1b (scalar plus vector) - scatter store bytes from a vector (vector index) - Scatter store of  bytes from the active elements of a vector register to the memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally        sign or zero-extended from 32 to 64 bits. Inactive elements are not written to memory. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11100100000.....1.0.............
       sz  Zm    s Pg Rn   Zt   
11100100010.....1.0.............
       sz  Zm    s Pg Rn   Zt   
11100100000.....101.............
       sz  Zm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

st1b (vector plus immediate) - scatter store bytes from a vector (immediate index) - Scatter store of  bytes from the active elements of a vector register to the memory addresses generated by a  vector base plus immediate index. The index is in the range 0 to 31. Inactive elements are not written to memory. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11100100011.....101.............
       sz  imm5    Pg Zn   Zt   
11100100010.....101.............
       sz  imm5    Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, in the range 0 to 31, defaulting to 0, encoded in the "imm5" field.

st1d (scalar plus immediate, consecutive registers) - contiguous store of doublewords from multiple consecutive vectors (immediate index) - Contiguous store of doublewords from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements are not written to memory.
101000000110....011............0
            imm4 szPNgRn   Zt  N
101000000110....111...........00
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

st1d (scalar plus immediate, single register) - contiguous store doublewords from vector (immediate index) - Contiguous store  of  doublewords from elements of a vector register to the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements are not written to memory. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
111001011110....111.............
       szpc imm4   Pg Rn   Zt   
111001011100....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

st1d (scalar plus scalar, consecutive registers) - contiguous store of doublewords from multiple consecutive vectors (scalar index) - Contiguous store of doublewords from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory.
10100000001.....011............0
           Rm    szPNgRn   Zt  N
10100000001.....111...........00
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

st1d (scalar plus scalar, single register) - contiguous store doublewords from vector (scalar index) - Contiguous store  of  doublewords from elements of a vector register to the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 8 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements are not written to memory. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11100101111!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       opc2Rm      Pg Rn   Zt   
11100101110!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       opc2Rm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st1d (scalar plus vector) - scatter store doublewords from a vector (vector index) - Scatter store of  doublewords from the active elements of a vector register to the memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then optionally multiplied by 8. Inactive elements are not written to memory. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11100101101.....1.0.............
       sz  Zm    s Pg Rn   Zt   
11100101100.....1.0.............
       sz  Zm    s Pg Rn   Zt   
11100101101.....101.............
       sz  Zm      Pg Rn   Zt   
11100101100.....101.............
       sz  Zm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

st1d (vector plus immediate) - scatter store doublewords from a vector (immediate index) - Scatter store of  doublewords from the active elements of a vector register to the memory addresses generated by a  vector base plus immediate index. The index is a multiple of 8 in the range 0 to 248. Inactive elements are not written to memory. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11100101110.....101.............
       sz  imm5    Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 8 in the range 0 to 248, defaulting to 0, encoded in the "imm5" field.

st1h (scalar plus immediate, consecutive registers) - contiguous store of halfwords from multiple consecutive vectors (immediate index) - Contiguous store of halfwords from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements are not written to memory.
101000000110....001............0
            imm4 szPNgRn   Zt  N
101000000110....101...........00
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

st1h (scalar plus immediate, single register) - contiguous store halfwords from vector (immediate index) - Contiguous store  of  halfwords from elements of a vector register to the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements are not written to memory.
111001001..0....111.............
       szze imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

st1h (scalar plus scalar, consecutive registers) - contiguous store of halfwords from multiple consecutive vectors (scalar index) - Contiguous store of halfwords from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory.
10100000001.....001............0
           Rm    szPNgRn   Zt  N
10100000001.....101...........00
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

st1h (scalar plus scalar, single register) - contiguous store halfwords from vector (scalar index) - Contiguous store  of  halfwords from elements of a vector register to the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 2 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements are not written to memory.
111001001..!= 11111!= 11111!= 11111!= 11111!= 11111010.............
         zeRm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st1h (scalar plus vector) - scatter store halfwords from a vector (vector index) - Scatter store of  halfwords from the active elements of a vector register to the memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then optionally multiplied by 2. Inactive elements are not written to memory. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11100100111.....1.0.............
       sz  Zm    s Pg Rn   Zt   
11100100101.....1.0.............
       sz  Zm    s Pg Rn   Zt   
11100100100.....1.0.............
       sz  Zm    s Pg Rn   Zt   
11100100110.....1.0.............
       sz  Zm    s Pg Rn   Zt   
11100100101.....101.............
       sz  Zm      Pg Rn   Zt   
11100100100.....101.............
       sz  Zm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

st1h (vector plus immediate) - scatter store halfwords from a vector (immediate index) - Scatter store of  halfwords from the active elements of a vector register to the memory addresses generated by a  vector base plus immediate index. The index is a multiple of 2 in the range 0 to 62. Inactive elements are not written to memory. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11100100111.....101.............
       sz  imm5    Pg Zn   Zt   
11100100110.....101.............
       sz  imm5    Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 62, defaulting to 0, encoded in the "imm5" field.

st1q - scatter store quadwords - Scatter store of quadwords from the active elements of a vector register to the memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements are not written to memory. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11100100001.....001.............
           Rm      Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

st1w (scalar plus immediate, consecutive registers) - contiguous store of words from multiple consecutive vectors (immediate index) - Contiguous store of words from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements are not written to memory.
101000000110....010............0
            imm4 szPNgRn   Zt  N
101000000110....110...........00
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

st1w (scalar plus immediate, single register) - contiguous store words from vector (immediate index) - Contiguous store  of  words from elements of a vector register to the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements are not written to memory. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
1110010101.0....111.............
       sz z imm4   Pg Rn   Zt   
111001010000....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <T>
 sz | <T>
 0 | S
 1 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

st1w (scalar plus scalar, consecutive registers) - contiguous store of words from multiple consecutive vectors (scalar index) - Contiguous store of words from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory.
10100000001.....010............0
           Rm    szPNgRn   Zt  N
10100000001.....110...........00
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

st1w (scalar plus scalar, single register) - contiguous store words from vector (scalar index) - Contiguous store  of  words from elements of a vector register to the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 4 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements are not written to memory. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
1110010101.!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       opczRm      Pg Rn   Zt   
11100101000!= 11111!= 11111!= 11111!= 11111!= 11111010.............
       opc2Rm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <T>
 sz | <T>
 0 | S
 1 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st1w (scalar plus vector) - scatter store words from a vector (vector index) - Scatter store of  words from the active elements of a vector register to the memory addresses generated by a 64-bit scalar base plus vector index. The index values are  optionally  first      sign or zero-extended from 32 to 64 bits and then optionally multiplied by 4. Inactive elements are not written to memory. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11100101011.....1.0.............
       sz  Zm    s Pg Rn   Zt   
11100101001.....1.0.............
       sz  Zm    s Pg Rn   Zt   
11100101000.....1.0.............
       sz  Zm    s Pg Rn   Zt   
11100101010.....1.0.............
       sz  Zm    s Pg Rn   Zt   
11100101001.....101.............
       sz  Zm      Pg Rn   Zt   
11100101000.....101.............
       sz  Zm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Zm>:name of the offset scalable vector register, encoded in the "Zm" field.
 <mod>
 xs | <mod>
 0 | UXTW
 1 | SXTW

st1w (vector plus immediate) - scatter store words from a vector (immediate index) - Scatter store of  words from the active elements of a vector register to the memory addresses generated by a  vector base plus immediate index. The index is a multiple of 4 in the range 0 to 124. Inactive elements are not written to memory. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11100101011.....101.............
       sz  imm5    Pg Zn   Zt   
11100101010.....101.............
       sz  imm5    Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <imm>:optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 124, defaulting to 0, encoded in the "imm5" field.

st2b (scalar plus immediate) - contiguous store two-byte structures from two vectors (immediate index) - Contiguous store two-byte structures, each from the same element number in two vector registers to the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 2 in the range -16 to 14 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  bytes in memory which make up each structure. Inactive structures are not written to memory.
111001000011....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.

st2b (scalar plus scalar) - contiguous store two-byte structures from two vectors (scalar index) - Contiguous store two-byte structures, each from the same element number in two vector registers to the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register    and added to the base address.   After each structure access the index value is   incremented by two.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  bytes in memory which make up each structure. Inactive structures are not written to memory.
11100100001!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st2d (scalar plus immediate) - contiguous store two-doubleword structures from two vectors (immediate index) - Contiguous store two-doubleword structures, each from the same element number in two vector registers to the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 2 in the range -16 to 14 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  doublewords in memory which make up each structure. Inactive structures are not written to memory.
111001011011....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.

st2d (scalar plus scalar) - contiguous store two-doubleword structures from two vectors (scalar index) - Contiguous store two-doubleword structures, each from the same element number in two vector registers to the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by two.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  doublewords in memory which make up each structure. Inactive structures are not written to memory.
11100101101!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st2h (scalar plus immediate) - contiguous store two-halfword structures from two vectors (immediate index) - Contiguous store two-halfword structures, each from the same element number in two vector registers to the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 2 in the range -16 to 14 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  halfwords in memory which make up each structure. Inactive structures are not written to memory.
111001001011....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.

st2h (scalar plus scalar) - contiguous store two-halfword structures from two vectors (scalar index) - Contiguous store two-halfword structures, each from the same element number in two vector registers to the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by two.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  halfwords in memory which make up each structure. Inactive structures are not written to memory.
11100100101!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st2q (scalar plus immediate) - contiguous store two-quadword structures from two vectors (immediate index) - Contiguous store two-quadword structures, each from the same element number in two vector registers to the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 2 in the range -16 to 14 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  quadwords in memory which make up each structure. Inactive structures are not written to memory.
111001000100....000.............
        um  imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.

st2q (scalar plus scalar) - contiguous store two-quadword structures from two vectors (scalar index) - Contiguous store two-quadword structures, each from the same element number in two vector registers to the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by two.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  quadwords in memory which make up each structure. Inactive structures are not written to memory.
11100100011!= 11111!= 11111!= 11111!= 11111!= 11111000.............
        um Rm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st2w (scalar plus immediate) - contiguous store two-word structures from two vectors (immediate index) - Contiguous store two-word structures, each from the same element number in two vector registers to the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 2 in the range -16 to 14 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  words in memory which make up each structure. Inactive structures are not written to memory.
111001010011....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.

st2w (scalar plus scalar) - contiguous store two-word structures from two vectors (scalar index) - Contiguous store two-word structures, each from the same element number in two vector registers to the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by two.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive  words in memory which make up each structure. Inactive structures are not written to memory.
11100101001!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st3b (scalar plus immediate) - contiguous store three-byte structures from three vectors (immediate index) - Contiguous store three-byte structures, each from the same element number in three vector registers to the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 3 in the range -24 to 21 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  bytes in memory which make up each structure. Inactive structures are not written to memory.
111001000101....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 3 in the range -24 to 21, defaulting to 0, encoded in the "imm4" field.

st3b (scalar plus scalar) - contiguous store three-byte structures from three vectors (scalar index) - Contiguous store three-byte structures, each from the same element number in three vector registers to the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register    and added to the base address.   After each structure access the index value is   incremented by three.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  bytes in memory which make up each structure. Inactive structures are not written to memory.
11100100010!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st3d (scalar plus immediate) - contiguous store three-doubleword structures from three vectors (immediate index) - Contiguous store three-doubleword structures, each from the same element number in three vector registers to the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 3 in the range -24 to 21 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  doublewords in memory which make up each structure. Inactive structures are not written to memory.
111001011101....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 3 in the range -24 to 21, defaulting to 0, encoded in the "imm4" field.

st3d (scalar plus scalar) - contiguous store three-doubleword structures from three vectors (scalar index) - Contiguous store three-doubleword structures, each from the same element number in three vector registers to the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by three.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  doublewords in memory which make up each structure. Inactive structures are not written to memory.
11100101110!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st3h (scalar plus immediate) - contiguous store three-halfword structures from three vectors (immediate index) - Contiguous store three-halfword structures, each from the same element number in three vector registers to the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 3 in the range -24 to 21 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  halfwords in memory which make up each structure. Inactive structures are not written to memory.
111001001101....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 3 in the range -24 to 21, defaulting to 0, encoded in the "imm4" field.

st3h (scalar plus scalar) - contiguous store three-halfword structures from three vectors (scalar index) - Contiguous store three-halfword structures, each from the same element number in three vector registers to the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by three.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  halfwords in memory which make up each structure. Inactive structures are not written to memory.
11100100110!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st3q (scalar plus immediate) - contiguous store three-quadword structures from three vectors (immediate index) - Contiguous store three-quadword structures, each from the same element number in three vector registers to the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 3 in the range -24 to 21 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  quadwords in memory which make up each structure. Inactive structures are not written to memory.
111001001000....000.............
        um  imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 3 in the range -24 to 21, defaulting to 0, encoded in the "imm4" field.

st3q (scalar plus scalar) - contiguous store three-quadword structures from three vectors (scalar index) - Contiguous store three-quadword structures, each from the same element number in three vector registers to the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by three.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  quadwords in memory which make up each structure. Inactive structures are not written to memory.
11100100101!= 11111!= 11111!= 11111!= 11111!= 11111000.............
        um Rm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st3w (scalar plus immediate) - contiguous store three-word structures from three vectors (immediate index) - Contiguous store three-word structures, each from the same element number in three vector registers to the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 3 in the range -24 to 21 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  words in memory which make up each structure. Inactive structures are not written to memory.
111001010101....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 3 in the range -24 to 21, defaulting to 0, encoded in the "imm4" field.

st3w (scalar plus scalar) - contiguous store three-word structures from three vectors (scalar index) - Contiguous store three-word structures, each from the same element number in three vector registers to the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by three.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive  words in memory which make up each structure. Inactive structures are not written to memory.
11100101010!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st4b (scalar plus immediate) - contiguous store four-byte structures from four vectors (immediate index) - Contiguous store four-byte structures, each from the same element number in four vector registers to the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 4 in the range -32 to 28 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  bytes in memory which make up each structure. Inactive structures are not written to memory.
111001000111....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.

st4b (scalar plus scalar) - contiguous store four-byte structures from four vectors (scalar index) - Contiguous store four-byte structures, each from the same element number in four vector registers to the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register    and added to the base address.   After each structure access the index value is   incremented by four.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  bytes in memory which make up each structure. Inactive structures are not written to memory.
11100100011!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st4d (scalar plus immediate) - contiguous store four-doubleword structures from four vectors (immediate index) - Contiguous store four-doubleword structures, each from the same element number in four vector registers to the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 4 in the range -32 to 28 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  doublewords in memory which make up each structure. Inactive structures are not written to memory.
111001011111....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.

st4d (scalar plus scalar) - contiguous store four-doubleword structures from four vectors (scalar index) - Contiguous store four-doubleword structures, each from the same element number in four vector registers to the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by four.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  doublewords in memory which make up each structure. Inactive structures are not written to memory.
11100101111!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st4h (scalar plus immediate) - contiguous store four-halfword structures from four vectors (immediate index) - Contiguous store four-halfword structures, each from the same element number in four vector registers to the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 4 in the range -32 to 28 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  halfwords in memory which make up each structure. Inactive structures are not written to memory.
111001001111....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.

st4h (scalar plus scalar) - contiguous store four-halfword structures from four vectors (scalar index) - Contiguous store four-halfword structures, each from the same element number in four vector registers to the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by four.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  halfwords in memory which make up each structure. Inactive structures are not written to memory.
11100100111!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st4q (scalar plus immediate) - contiguous store four-quadword structures from four vectors (immediate index) - Contiguous store four-quadword structures, each from the same element number in four vector registers to the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 4 in the range -32 to 28 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  quadwords in memory which make up each structure. Inactive structures are not written to memory.
111001001100....000.............
        um  imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.

st4q (scalar plus scalar) - contiguous store four-quadword structures from four vectors (scalar index) - Contiguous store four-quadword structures, each from the same element number in four vector registers to the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by four.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  quadwords in memory which make up each structure. Inactive structures are not written to memory.
11100100111!= 11111!= 11111!= 11111!= 11111!= 11111000.............
        um Rm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

st4w (scalar plus immediate) - contiguous store four-word structures from four vectors (immediate index) - Contiguous store four-word structures, each from the same element number in four vector registers to the memory address generated by a 64-bit scalar base and an immediate index which  is a multiple of 4 in the range -32 to 28 that is multiplied  by the vector's in-memory size, irrespective of predication,   Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  words in memory which make up each structure. Inactive structures are not written to memory.
111001010111....111.............
       szpc imm4   Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.

st4w (scalar plus scalar) - contiguous store four-word structures from four vectors (scalar index) - Contiguous store four-word structures, each from the same element number in four vector registers to the memory address generated by a 64-bit scalar base  and    a 64-bit scalar index   register scaled by the element size (LSL option)    and added to the base address.   After each structure access the index value is   incremented by four.   The index register is not updated by the instruction.  Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive  words in memory which make up each structure. Inactive structures are not written to memory.
11100101011!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       szpcRm      Pg Rn   Zt   
 <Zt1>:name of the first scalable vector register to be transferred, encoded in the "Zt" field.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
 <Zt3>:name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

stnt1b (scalar plus immediate, consecutive registers) - contiguous store non-temporal of bytes from multiple consecutive vectors (immediate index) - Contiguous store non-temporal of bytes from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
101000000110....000............1
            imm4 szPNgRn   Zt  N
101000000110....100...........01
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

stnt1b (scalar plus immediate, single register) - contiguous store non-temporal bytes from vector (immediate index) - Contiguous store non-temporal of  bytes from elements of a vector register to the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
111001000001....111.............
       sz   imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

stnt1b (scalar plus scalar, consecutive registers) - contiguous store non-temporal of bytes from multiple consecutive vectors (scalar index) - Contiguous store non-temporal of bytes from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
10100000001.....000............1
           Rm    szPNgRn   Zt  N
10100000001.....100...........01
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

stnt1b (scalar plus scalar, single register) - contiguous store non-temporal bytes from vector (scalar index) - Contiguous store non-temporal of  bytes from elements of a vector register to the memory address generated by a 64-bit scalar base and scalar index which is      added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
11100100000!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       sz  Rm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

stnt1b (vector plus scalar) - scatter store non-temporal bytes - Scatter store non-temporal of  bytes from the active elements of a vector register to the memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11100100010.....001.............
       sz  Rm      Pg Zn   Zt   
11100100000.....001.............
       sz  Rm      Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

stnt1d (scalar plus immediate, consecutive registers) - contiguous store non-temporal of doublewords from multiple consecutive vectors (immediate index) - Contiguous store non-temporal of doublewords from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
101000000110....011............1
            imm4 szPNgRn   Zt  N
101000000110....111...........01
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

stnt1d (scalar plus immediate, single register) - contiguous store non-temporal doublewords from vector (immediate index) - Contiguous store non-temporal of  doublewords from elements of a vector register to the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
111001011001....111.............
       sz   imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

stnt1d (scalar plus scalar, consecutive registers) - contiguous store non-temporal of doublewords from multiple consecutive vectors (scalar index) - Contiguous store non-temporal of doublewords from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
10100000001.....011............1
           Rm    szPNgRn   Zt  N
10100000001.....111...........01
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

stnt1d (scalar plus scalar, single register) - contiguous store non-temporal doublewords from vector (scalar index) - Contiguous store non-temporal of  doublewords from elements of a vector register to the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 8 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
11100101100!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       sz  Rm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

stnt1d (vector plus scalar) - scatter store non-temporal doublewords - Scatter store non-temporal of  doublewords from the active elements of a vector register to the memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11100101100.....001.............
       sz  Rm      Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

stnt1h (scalar plus immediate, consecutive registers) - contiguous store non-temporal of halfwords from multiple consecutive vectors (immediate index) - Contiguous store non-temporal of halfwords from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
101000000110....001............1
            imm4 szPNgRn   Zt  N
101000000110....101...........01
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

stnt1h (scalar plus immediate, single register) - contiguous store non-temporal halfwords from vector (immediate index) - Contiguous store non-temporal of  halfwords from elements of a vector register to the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
111001001001....111.............
       sz   imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

stnt1h (scalar plus scalar, consecutive registers) - contiguous store non-temporal of halfwords from multiple consecutive vectors (scalar index) - Contiguous store non-temporal of halfwords from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
10100000001.....001............1
           Rm    szPNgRn   Zt  N
10100000001.....101...........01
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

stnt1h (scalar plus scalar, single register) - contiguous store non-temporal halfwords from vector (scalar index) - Contiguous store non-temporal of  halfwords from elements of a vector register to the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 2 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
11100100100!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       sz  Rm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

stnt1h (vector plus scalar) - scatter store non-temporal halfwords - Scatter store non-temporal of  halfwords from the active elements of a vector register to the memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11100100110.....001.............
       sz  Rm      Pg Zn   Zt   
11100100100.....001.............
       sz  Rm      Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

stnt1w (scalar plus immediate, consecutive registers) - contiguous store non-temporal of words from multiple consecutive vectors (immediate index) - Contiguous store non-temporal of words from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and immediate index which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
101000000110....010............1
            imm4 szPNgRn   Zt  N
101000000110....110...........01
            imm4 szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field.
 <imm>:For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

stnt1w (scalar plus immediate, single register) - contiguous store non-temporal words from vector (immediate index) - Contiguous store non-temporal of  words from elements of a vector register to the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size,        irrespective of predication, and added to the base address.  Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
111001010001....111.............
       sz   imm4   Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

stnt1w (scalar plus scalar, consecutive registers) - contiguous store non-temporal of words from multiple consecutive vectors (scalar index) - Contiguous store non-temporal of words from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
10100000001.....010............1
           Rm    szPNgRn   Zt  N
10100000001.....110...........01
           Rm    szPNgRn   Zt  N
 <Zt1>:For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2.
 <Zt1>:For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4.
 <Zt2>:name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1.
 <PNg>:name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.
 <Zt4>:name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3.

stnt1w (scalar plus scalar, single register) - contiguous store non-temporal words from vector (scalar index) - Contiguous store non-temporal of  words from elements of a vector register to the memory address generated by a 64-bit scalar base and scalar index which is      multiplied by 4 and added to the base address. After each     element access     the index value is incremented,     but the index register is not updated. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
11100101000!= 11111!= 11111!= 11111!= 11111!= 11111011.............
       sz  Rm      Pg Rn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <Xm>:64-bit name of the general-purpose offset register, encoded in the "Rm" field.

stnt1w (vector plus scalar) - scatter store non-temporal words - Scatter store non-temporal of  words from the active elements of a vector register to the memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements are not written to memory. A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
11100101010.....001.............
       sz  Rm      Pg Zn   Zt   
11100101000.....001.............
       sz  Rm      Pg Zn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the base scalable vector register, encoded in the "Zn" field.
 <Xm>:optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

str (predicate) - store predicate register - Store a predicate register to a memory address generated by a 64-bit scalar base, plus an immediate offset in the range -256 to 255 which is multiplied by the current predicate register size in bytes. is unpredicated. The store is performed as contiguous byte accesses, each containing 8 consecutive predicate bits in ascending element order, with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then a general-purpose base register must be aligned to 2 bytes. For programmer convenience, an assembler must also accept       a predicate-as-counter register name for the source       predicate register.
1110010110......000........0....
          imm9h    m9lRn    Pt  
 <Pt>:name of the scalable predicate transfer register, encoded in the "Pt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9h:imm9l" fields.

str (vector) - store vector register - Store a vector register to a memory address generated by a 64-bit scalar base, plus an immediate offset in the range -256 to 255 which is multiplied by the current vector register size in bytes. is unpredicated. The store is performed as contiguous byte accesses,  with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then the base register must be aligned to 16 bytes.
1110010110......010.............
          imm9h    m9lRn   Zt   
 <Zt>:name of the scalable vector register to be transferred, encoded in the "Zt" field.
 <Xn|SP>:64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
 <imm>:optional signed immediate vector offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9h:imm9l" fields.

sub (immediate) - subtract immediate (unpredicated) - Subtract an unsigned immediate from each element of the source vector, and destructively place the results in the corresponding elements of the  source vector. is unpredicated. The immediate is an unsigned value in the range 0 to 255, and for element widths of 16 bits or higher it may also be a positive multiple of 256 in the range 256 to 65280. The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<uimm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".
00100101..10000111..............
        ze   opc  himm8    Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm>:Is an unsigned immediate in the range 0 to 255, encoded in the "imm8" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #8

sub (vectors, predicated) - subtract vectors (predicated) - Subtract active elements of the second source vector from corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..000001000.............
        ze   opc   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sub (vectors, unpredicated) - subtract vectors (unpredicated) - Subtract all elements of the second source vector from corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. is unpredicated.
00000100..1.....000001..........
        ze Zm      opcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

subhnb - subtract narrow high part (bottom) - Subtract each vector element of the second source vector from the corresponding vector element in the first source vector, and place the most significant half of the result in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. is unpredicated.
01000101..1.....011100..........
        ze Zm      SRTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

subhnt - subtract narrow high part (top) - Subtract each vector element of the second source vector from the corresponding vector element in the first source vector, and place the most significant half of the result in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. is unpredicated.
01000101..1.....011101..........
        ze Zm      SRTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

subpt (predicated) - subtract checked pointer vectors (predicated) - Subtract with pointer check active elements of the second source vector from corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
0000010011000101000.............
        ze   opc   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

subpt (unpredicated) - subtract checked pointer vectors (unpredicated) - Subtract with pointer check all elements of the second source vector from corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. is unpredicated. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
00000100111.....000011..........
        ze Zm      opcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

subr (immediate) - reversed subtract from immediate (unpredicated) - Reversed subtract from an unsigned immediate each element of the source vector, and destructively place the results in the corresponding elements of the  source vector. is unpredicated. The immediate is an unsigned value in the range 0 to 255, and for element widths of 16 bits or higher it may also be a positive multiple of 256 in the range 256 to 65280. The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<uimm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".
00100101..10001111..............
        ze   opc  himm8    Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm>:Is an unsigned immediate in the range 0 to 255, encoded in the "imm8" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #8

subr (vectors) - reversed subtract vectors (predicated) - Reversed subtract active elements of the first source vector from corresponding elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..000011000.............
        ze   opc   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sudot - signed by unsigned integer indexed dot product - The signed by unsigned integer indexed dot product instruction computes the dot product of a group of four signed 8-bit  integer values held in each 32-bit  element of the first source vector multiplied by a group of four unsigned 8-bit  integer values in an indexed 32-bit  element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit  element of the destination vector. The groups within the second source vector are specified using an immediate index which selects the same group position within each 128-bit vector segment.  The index range is from 0 to 3. is unpredicated. ID_AA64ZFR0_EL1.I8MM indicates whether this instruction is implemented.
01000100101.....000111..........
        ze i2Zm      UZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index of a 32-bit group of four 8-bit values within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.

sunpkhi, sunpklo - signed unpack and extend half of vector - Unpack elements from the lowest or highest half of the source vector and then sign-extend them to place in elements of twice their size within the destination vector.  is unpredicated.
00000101..110001001110..........
        ze    UH      Zn   Zd   
00000101..110000001110..........
        ze    UH      Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S

suqadd - signed saturating addition of unsigned value - Add active unsigned elements of the source vector to the corresponding signed elements of the addend vector, and destructively place the results in the corresponding elements of the addend vector.  Each result element is saturated to the  N-bit element's signed integer range -2(N-1)  to (2(N-1))-1. Inactive elements in the destination vector register remain unmodified.
01000100..011100100.............
        ze   pSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

sxtb, sxth, sxtw - signed byte / halfword / word extend (predicated) - Sign-extend the least-significant sub-element  of each active element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
00000100..010000101.............
        ze M   U   Pg Zn   Zd   
00000100..000000101.............
        ze M   U   Pg Zn   Zd   
00000100..010010101.............
        ze M   U   Pg Zn   Zd   
00000100..000010101.............
        ze M   U   Pg Zn   Zd   
00000100..010100101.............
        ze M   U   Pg Zn   Zd   
00000100..000100101.............
        ze M   U   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <T>
 size<0> | <T>
 0 | S
 1 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

tbl - programmable table lookup in one or two vector table (zeroing) - Reads each element of the second source (index) vector and uses its value to select an indexed element from a table of elements consisting of    one or two consecutive vector registers,    where the first or only vector    holds the lower numbered elements, and places the indexed table element in the destination vector element corresponding to the index vector element. If an index value is greater than or equal to the  number of vector elements then it places zero in the corresponding destination vector element. Since the index values can select any element in a vector this operation is not naturally vector length agnostic.
00000101..1.....001100..........
        ze Zm         Zn   Zd   
00000101..1.....001010..........
        ze Zm        pZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Zn1>:name of the first scalable vector register of the first source multi-vector group, encoded in the "Zn" field.
 <Zn2>:name of the second scalable vector register of the first source multi-vector group, encoded in the "Zn" field.

tblq - programmable table lookup within each quadword vector segment (zeroing) - For each 128-bit destination vector segment, reads each element of the corresponding second source (index) vector segment and uses its value to select an indexed element from the corresponding first source (table) vector segment. The indexed table element is placed in the element of the destination vector that corresponds to the index vector element. If an index value is greater than or equal to the number of elements in a 128-bit vector segment then it places zero in the corresponding destination vector element. is unpredicated.
01000100..0.....111110..........
        ze Zm      opcZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

tbx - programmable table lookup in single vector table (merging) - Reads each element of the second source (index) vector and uses its value to select an indexed element from a table of elements in the first source vector, and places the indexed element in the destination vector element corresponding to the index vector element. If an index value is greater than or equal to the number of vector elements then the corresponding destination vector element is left unchanged. Since the index values can select any element in a vector this operation is not naturally vector length agnostic.
00000101..1.....001011..........
        ze Zm        pZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

tbxq - programmable table lookup within each quadword vector segment (merging) - For each 128-bit destination vector segment, reads each element of the corresponding second source (index) vector segment and uses its value to select an indexed element from the corresponding first source (table) vector segment. The indexed table element is placed in the element of the destination vector that corresponds to the index vector element. If an index value is greater than or equal to the number of elements in a 128-bit vector segment then the corresponding destination vector element is left unchanged. is unpredicated.
00000101..1.....001101..........
        ze Zm         Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

trn1, trn2 (predicates) - interleave even or odd elements from two predicates - Interleave alternating even or odd-numbered elements from the  first and second source predicates and place in elements of the destination predicate.  is unpredicated.
00000101..10....0101000....0....
        ze  Pm     pcH Pn   Pd  
00000101..10....0101010....0....
        ze  Pm     pcH Pn   Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

trn1, trn2 (vectors) - interleave even or odd elements from two vectors - Interleave alternating even or odd-numbered elements from the  first and second source vectors and place in elements of the destination vector.  is unpredicated. The 128-bit element variant requires that the Effective SVE vector length is at least 256 bits. ID_AA64ZFR0_EL1.F64MM indicates whether the 128-bit element variant is implemented. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
00000101..1.....011100..........
        ze Zm        HZn   Zd   
00000101101.....000110..........
           Zm      pcHZn   Zd   
00000101..1.....011101..........
        ze Zm        HZn   Zd   
00000101101.....000111..........
           Zm      pcHZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uaba - unsigned absolute difference and accumulate - Compute the absolute difference between unsigned integer values in elements of the second source vector and corresponding elements of the first source vector, and add the difference to the corresponding elements of the destination vector. is unpredicated.
01000101..0.....111111..........
        ze Zm        UZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uabalb - unsigned absolute difference and accumulate long (bottom) - Compute the absolute difference between even-numbered unsigned elements of the second source vector and corresponding elements of the first source vector, and destructively add to the overlapping double-width elements of the addend vector. is unpredicated.
01000101..0.....110010..........
        ze Zm       UTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uabalt - unsigned absolute difference and accumulate long (top) - Compute the absolute difference between odd-numbered unsigned elements of the second source vector and corresponding elements of the first source vector, and destructively add to the overlapping double-width elements of the addend vector. is unpredicated.
01000101..0.....110011..........
        ze Zm       UTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uabd - unsigned absolute difference (predicated) - Compute the absolute difference between unsigned integer values in active elements of the second source vector and corresponding elements of the first source vector and destructively place the difference in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..001101000.............
        ze   pcU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uabdlb - unsigned absolute difference long (bottom) - Compute the absolute difference between the even-numbered unsigned integer values in elements of the second source vector and the corresponding elements of the first source vector, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....001110..........
        ze Zm     pSUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uabdlt - unsigned absolute difference long (top) - Compute the absolute difference between the odd-numbered unsigned integer values in elements of the second source vector and corresponding elements of the first source vector, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....001111..........
        ze Zm     pSUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uadalp - unsigned add and accumulate long pairwise - Add pairs of adjacent unsigned integer values and accumulate the results into the overlapping double-width elements of the destination vector.
01000100..000101101.............
        ze     U   Pg Zn   Zda  
 <Zda>:name of the second source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S

uaddlb - unsigned add long (bottom) - Add the corresponding even-numbered unsigned elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....000010..........
        ze Zm     pSUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uaddlt - unsigned add long (top) - Add the corresponding odd-numbered unsigned elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....000011..........
        ze Zm     pSUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uaddv - unsigned add reduction to scalar - Unsigned add horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register. Narrow elements are first zero-extended to 64 bits. Inactive elements in the source vector are treated as zero.
00000100..000001001.............
        ze    pU   Pg Zn   Vd   
 <Dd>:64-bit name of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

uaddwb - unsigned add wide (bottom) - Add the even-numbered unsigned elements of the second source vector to the overlapping double-width elements of the first source vector and place the results in the corresponding double-width elements of the destination vector.  is unpredicated.
01000101..0.....010010..........
        ze Zm      SUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S

uaddwt - unsigned add wide (top) - Add the odd-numbered unsigned elements of the second source vector to the overlapping double-width elements of the first source vector and place the results in the corresponding double-width elements of the destination vector.  is unpredicated.
01000101..0.....010011..........
        ze Zm      SUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S

uclamp - unsigned clamp to minimum/maximum vector - Clamp each unsigned element in the destination vector to between the unsigned minimum value in the corresponding element of the first source vector and the unsigned maximum value in the corresponding element of the second source vector and destructively write the results in the corresponding elements of the destination vector. is unpredicated.
01000100..0.....110001..........
        ze Zm        UZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

ucvtf - unsigned integer convert to floating-point (predicated) - Convert to floating-point from the unsigned integer in each active element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. If the input and result types have a different size the smaller type is held unpacked in the least significant bits of elements of the larger size. When the input is the smaller type the upper bits of each source element are ignored. When the result is the smaller type the results are zero-extended to fill each destination element.
0110010101010011101.............
        pc   c2U   Pg Zn   Zd   
0110010001011100111.............
        pc     2 3UPg Zn   Zd   
0110010101010101101.............
        pc   c2U   Pg Zn   Zd   
0110010001011101101.............
        pc     2 3UPg Zn   Zd   
0110010110010101101.............
        pc   c2U   Pg Zn   Zd   
0110010010011101101.............
        pc     2 3UPg Zn   Zd   
0110010111010001101.............
        pc   c2U   Pg Zn   Zd   
0110010011011100101.............
        pc     2 3UPg Zn   Zd   
0110010101010111101.............
        pc   c2U   Pg Zn   Zd   
0110010001011101111.............
        pc     2 3UPg Zn   Zd   
0110010111010101101.............
        pc   c2U   Pg Zn   Zd   
0110010011011101101.............
        pc     2 3UPg Zn   Zd   
0110010111010111101.............
        pc   c2U   Pg Zn   Zd   
0110010011011101111.............
        pc     2 3UPg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

udiv - unsigned divide (predicated) - Unsigned divide active elements of the first source vector by corresponding elements of the second source vector and destructively place the quotient in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..010101000.............
        ze    RU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size<0> | <T>
 0 | S
 1 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

udivr - unsigned reversed divide (predicated) - Unsigned reversed divide active elements of the second source vector by corresponding elements of the first source vector and destructively place the quotient in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..010111000.............
        ze    RU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size<0> | <T>
 0 | S
 1 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

udot (2-way, indexed) - unsigned integer indexed dot product - The unsigned  integer indexed dot product instruction computes the dot product of a group of two unsigned 16-bit integer values held in each 32-bit element of the first source vector multiplied by a group of two unsigned 16-bit integer values in an indexed 32-bit element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit element of the destination vector. The groups within the second source vector are specified using an immediate index which selects the same group position within each 128-bit vector segment.  The index range is from 0 to 3. is unpredicated.
01000100100.....110011..........
           i2Zm      UZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index of a group of two 16-bit elements within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.

udot (2-way, vectors) - unsigned integer dot product - The unsigned  integer  dot product instruction computes the dot product of a group of two unsigned 16-bit integer values held in each 32-bit element of the first source vector multiplied by a group of two unsigned 16-bit integer values in the corresponding 32-bit element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit element of the destination vector. is unpredicated.
01000100000.....110011..........
           Zm        UZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

udot (4-way, indexed) - unsigned integer indexed dot product - The unsigned  integer indexed dot product instruction computes the dot product of a group of four unsigned 8-bit or 16-bit integer values held in each 32-bit or 64-bit element of the first source vector multiplied by a group of four unsigned 8-bit or 16-bit integer values in an indexed 32-bit or 64-bit element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit or 64-bit element of the destination vector. The groups within the second source vector are specified using an immediate index which selects the same group position within each 128-bit vector segment.  The index range is from 0 to one less than the number of groups per                         128-bit segment, encoded in 1 to 2 bits                         depending on the size of the group. is unpredicated.
01000100101.....000001..........
        ze i2Zm      UZn   Zda  
01000100111.....000001..........
        ze 1Zm       UZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the immediate index of a 32-bit group of four 8-bit values within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.
 <imm>:For the "64-bit" variant: is the immediate index of a 64-bit group of four 16-bit values within each 128-bit vector segment, in the range 0 to 1, encoded in the "i1" field.

udot (4-way, vectors) - unsigned integer dot product - The unsigned  integer  dot product instruction computes the dot product of a group of four unsigned 8-bit or 16-bit integer values held in each 32-bit or 64-bit element of the first source vector multiplied by a group of four unsigned 8-bit or 16-bit integer values in the corresponding 32-bit or 64-bit element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit or 64-bit element of the destination vector. is unpredicated.
01000100..0.....000001..........
        ze Zm        UZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size<0> | <T>
 0 | S
 1 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size<0> | <Tb>
 0 | B
 1 | H
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uhadd - unsigned halving addition - Add active unsigned elements of the first source vector to corresponding unsigned elements of the second source vector, shift right one bit, and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01000100..010001100.............
        ze   RSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uhsub - unsigned halving subtract - Subtract active unsigned elements of the second source vector from corresponding unsigned elements of the first source vector, shift right one bit, and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01000100..010011100.............
        ze   RSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uhsubr - unsigned halving subtract reversed vectors - Subtract active unsigned elements of the first source vector from corresponding unsigned elements of the second source vector, shift right one bit, and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01000100..010111100.............
        ze   RSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

umax (immediate) - unsigned maximum with immediate (unpredicated) - Determine the unsigned maximum of an immediate and each element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate is an unsigned 8-bit value in the range 0 to 255, inclusive. is unpredicated.
00100101..101001110.............
        ze     U  2imm8    Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm>:unsigned immediate operand, in the range 0 to 255, encoded in the "imm8" field.

umax (vectors) - unsigned maximum vectors (predicated) - Determine the unsigned maximum of active elements of the second source vector and corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..001001000.............
        ze   pcU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

umaxp - unsigned maximum pairwise - Compute the maximum value of each pair of adjacent unsigned integer elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector.
01000100..010101101.............
        ze   pcU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

umaxqv - unsigned maximum reduction of quadword vector segments - Unsigned maximum of the same element numbers from each 128-bit source vector segment, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as zero.
00000100..001101001.............
        ze    pU   Pg Zn   Vd   
 <Vd>:name of the destination SIMD&FP register, encoded in the "Vd" field.
 <T>
 size | <T>
 00 | 16B
 01 | 8H
 10 | 4S
 11 | 2D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | B
 01 | H
 10 | S
 11 | D

umaxv - unsigned maximum reduction to scalar - Unsigned maximum horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register.  Inactive elements in the source vector are treated as zero.
00000100..001001001.............
        ze    pU   Pg Zn   Vd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

umin (immediate) - unsigned minimum with immediate (unpredicated) - Determine the unsigned minimum of an immediate and each element of the source vector, and destructively place the results in the corresponding elements of the  source vector. The immediate is an unsigned 8-bit value in the range 0 to 255, inclusive. is unpredicated.
00100101..101011110.............
        ze     U  2imm8    Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm>:unsigned immediate operand, in the range 0 to 255, encoded in the "imm8" field.

umin (vectors) - unsigned minimum vectors (predicated) - Determine the unsigned minimum of active elements of the second source vector and corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..001011000.............
        ze   pcU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uminp - unsigned minimum pairwise - Compute the minimum value of each pair of adjacent unsigned integer elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector.
01000100..010111101.............
        ze   pcU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uminqv - unsigned minimum reduction of quadword vector segments - Unsigned minimum of the same element numbers from each 128-bit source vector segment, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as the maximum unsigned integer for the element size.
00000100..001111001.............
        ze    pU   Pg Zn   Vd   
 <Vd>:name of the destination SIMD&FP register, encoded in the "Vd" field.
 <T>
 size | <T>
 00 | 16B
 01 | 8H
 10 | 4S
 11 | 2D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | B
 01 | H
 10 | S
 11 | D

uminv - unsigned minimum reduction to scalar - Unsigned minimum horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register.  Inactive elements in the source vector are treated as the maximum unsigned integer for the element size.
00000100..001011001.............
        ze    pU   Pg Zn   Vd   
 <V>
 size | <V>
 00 | B
 01 | H
 10 | S
 11 | D
 <d>:number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D

umlalb (indexed) - unsigned multiply-add long to accumulator (bottom, indexed) - Multiply the even-numbered unsigned elements within each 128-bit segment of the first source vector by the specified unsigned element in the corresponding second source vector segment and destructively add to the overlapping double-width elements of the addend vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....1001.0..........
        ze 3hZm   SUlTZn   Zda  
01000100111.....1001.0..........
        ze hZm    SUlTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

umlalb (vectors) - unsigned multiply-add long to accumulator (bottom) - Multiply the corresponding even-numbered unsigned elements of the first and second source vectors and destructively add to the overlapping double-width elements of the addend vector. is unpredicated.
01000100..0.....010010..........
        ze Zm      SUTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

umlalt (indexed) - unsigned multiply-add long to accumulator (top, indexed) - Multiply the odd-numbered unsigned elements within each 128-bit segment of the first source vector by the specified unsigned element in the corresponding second source vector segment and destructively add to the overlapping double-width elements of the addend vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....1001.1..........
        ze 3hZm   SUlTZn   Zda  
01000100111.....1001.1..........
        ze hZm    SUlTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

umlalt (vectors) - unsigned multiply-add long to accumulator (top) - Multiply the corresponding odd-numbered unsigned elements of the first and second source vectors and destructively add to the overlapping double-width elements of the addend vector. is unpredicated.
01000100..0.....010011..........
        ze Zm      SUTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

umlslb (indexed) - unsigned multiply-subtract long from accumulator (bottom, indexed) - Multiply the even-numbered unsigned elements within each 128-bit segment of the first source vector by the specified unsigned element in the corresponding second source vector segment and destructively subtract from the overlapping double-width elements of the addend vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....1011.0..........
        ze 3hZm   SUlTZn   Zda  
01000100111.....1011.0..........
        ze hZm    SUlTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

umlslb (vectors) - unsigned multiply-subtract long from accumulator (bottom) - Multiply the corresponding even-numbered unsigned elements of the first and second source vectors and destructively subtract from the overlapping double-width elements of the addend vector. is unpredicated.
01000100..0.....010110..........
        ze Zm      SUTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

umlslt (indexed) - unsigned multiply-subtract long from accumulator (top, indexed) - Multiply the odd-numbered unsigned elements within each 128-bit segment of the first source vector by the specified unsigned element in the corresponding second source vector segment and destructively subtract from the overlapping double-width elements of the addend vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....1011.1..........
        ze 3hZm   SUlTZn   Zda  
01000100111.....1011.1..........
        ze hZm    SUlTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

umlslt (vectors) - unsigned multiply-subtract long from accumulator (top) - Multiply the corresponding odd-numbered unsigned elements of the first and second source vectors and destructively subtract from the overlapping double-width elements of the addend vector. is unpredicated.
01000100..0.....010111..........
        ze Zm      SUTZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

ummla - unsigned integer matrix multiply-accumulate - The unsigned  integer matrix multiply-accumulate instruction multiplies the 2×8 matrix of unsigned 8-bit integer values held in each 128-bit segment of the first source vector by the 8×2 matrix of unsigned 8-bit integer values in the corresponding segment of the second source vector. The resulting 2×2 widened 32-bit integer matrix product is then destructively added to the 32-bit integer matrix accumulator held in the corresponding segment of the addend and destination vector. This is equivalent to performing an 8-way dot product per destination element. is unpredicated. ID_AA64ZFR0_EL1.I8MM indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01000101110.....100110..........
        ns Zm         Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

umulh (predicated) - unsigned multiply returning high half (predicated) - Widening multiply unsigned integer values in active elements of the first source vector by corresponding elements of the second source vector and destructively place the high half of the result in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
00000100..010011000.............
        ze    HU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

umulh (unpredicated) - unsigned multiply returning high half (unpredicated) - Widening multiply unsigned integer values of all elements of the first source vector by corresponding elements of the second source vector and place the high half of the result in the corresponding elements of the destination vector. is unpredicated.
00000100..1.....011011..........
        ze Zm        UZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

umullb (indexed) - unsigned multiply long (bottom, indexed) - Multiply the even-numbered unsigned elements within each 128-bit segment of the first source vector by the specified unsigned element in the corresponding second source vector segment, and place the results in the overlapping double-width elements of the destination vector register. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....1101.0..........
        ze 3hZm    UlTZn   Zd   
01000100111.....1101.0..........
        ze hZm     UlTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

umullb (vectors) - unsigned multiply long (bottom) - Multiply the corresponding even-numbered unsigned elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....011110..........
        ze Zm      pUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

umullt (indexed) - unsigned multiply long (top, indexed) - Multiply the odd-numbered unsigned elements within each 128-bit segment of the first source vector by the specified unsigned element in the corresponding second source vector segment, and place the results in the overlapping double-width elements of the destination vector register. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment.  The index range is from 0 to one less than the number of elements per                         128-bit segment, encoded in 2 or 3 bits                         depending on the size of the element.
01000100101.....1101.1..........
        ze 3hZm    UlTZn   Zd   
01000100111.....1101.1..........
        ze hZm     UlTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <Zm>:For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
 <imm>:For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
 <imm>:For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

umullt (vectors) - unsigned multiply long (top) - Multiply the corresponding odd-numbered unsigned elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....011111..........
        ze Zm      pUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uqadd (immediate) - unsigned saturating add immediate (unpredicated) - Unsigned saturating add of an unsigned immediate to each element of the source vector, and destructively place the results in the corresponding elements of the  source vector. Each result element is saturated to the  N-bit element's unsigned integer range 0 to (2N)-1. is unpredicated. The immediate is an unsigned value in the range 0 to 255, and for element widths of 16 bits or higher it may also be a positive multiple of 256 in the range 256 to 65280. The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<uimm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".
00100101..10010111..............
        ze     U  himm8    Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm>:Is an unsigned immediate in the range 0 to 255, encoded in the "imm8" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #8

uqadd (vectors, predicated) - unsigned saturating addition (predicated) - Add active unsigned elements of the first source vector to corresponding unsigned elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. Each result element is saturated to the  N-bit element's unsigned integer range 0 to (2N)-1. Inactive elements in the destination vector register remain unmodified.
01000100..011001100.............
        ze   pSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uqadd (vectors, unpredicated) - unsigned saturating add vectors (unpredicated) - Unsigned saturating add all elements of the second source vector to corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. Each result element is saturated to the  N-bit element's unsigned integer range 0 to (2N)-1. is unpredicated.
00000100..1.....000101..........
        ze Zm        UZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uqcvtn - unsigned saturating extract narrow and interleave - Saturate the unsigned integer value in each element of the group of two source vectors to half the original source element width, and place the two-way interleaved results in the half-width destination elements. is unpredicated.
0100010100110001010010....0.....
         h zl       U Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn1>:name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.
 <Zn2>:name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.

uqdecb - unsigned saturating decrement scalar by multiple of 8-bit predicate constraint element count - Determines the number of active 8-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement the   scalar destination. The   result is   saturated to the       general-purpose register's   unsigned integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001000010....111111..........
        ze fimm4    DUtternRdn  
000001000011....111111..........
        ze fimm4    DUtternRdn  
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

uqdecd (scalar) - unsigned saturating decrement scalar by multiple of 64-bit predicate constraint element count - Determines the number of active 64-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement the   scalar destination. The   result is   saturated to the       general-purpose register's   unsigned integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001110....111111..........
        ze fimm4    DUtternRdn  
000001001111....111111..........
        ze fimm4    DUtternRdn  
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

uqdecd (vector) - unsigned saturating decrement vector by multiple of 64-bit predicate constraint element count - Determines the number of active 64-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement all destination vector elements. The   results are   saturated to the   64-bit    unsigned integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001110....110011..........
        ze  imm4    DUtternZdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

uqdech (scalar) - unsigned saturating decrement scalar by multiple of 16-bit predicate constraint element count - Determines the number of active 16-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement the   scalar destination. The   result is   saturated to the       general-purpose register's   unsigned integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001000110....111111..........
        ze fimm4    DUtternRdn  
000001000111....111111..........
        ze fimm4    DUtternRdn  
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

uqdech (vector) - unsigned saturating decrement vector by multiple of 16-bit predicate constraint element count - Determines the number of active 16-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement all destination vector elements. The   results are   saturated to the   16-bit    unsigned integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001000110....110011..........
        ze  imm4    DUtternZdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

uqdecp (scalar) - unsigned saturating decrement scalar by count of true predicate elements - Counts the number of true elements in the source predicate and then uses the result to decrement the   scalar destination. The   result is   saturated to the       general-purpose register's   unsigned integer range.
00100101..1010111000100.........
        ze    DU     fpPm  Rdn  
00100101..1010111000110.........
        ze    DU     fpPm  Rdn  
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <Pm>:name of the source scalable predicate register, encoded in the "Pm" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

uqdecp (vector) - unsigned saturating decrement vector by count of true predicate elements - Counts the number of true elements in the source predicate and then uses the result to decrement all destination vector elements. The   results are   saturated to the   element    unsigned integer range. The predicate size specifier may be omitted in assembler    source code, but this is deprecated and will be    prohibited in a future release of the architecture.
00100101..1010111000000.........
        ze    DU     pcPm  Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pm>:name of the source scalable predicate register, encoded in the "Pm" field.

uqdecw (scalar) - unsigned saturating decrement scalar by multiple of 32-bit predicate constraint element count - Determines the number of active 32-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement the   scalar destination. The   result is   saturated to the       general-purpose register's   unsigned integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001010....111111..........
        ze fimm4    DUtternRdn  
000001001011....111111..........
        ze fimm4    DUtternRdn  
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

uqdecw (vector) - unsigned saturating decrement vector by multiple of 32-bit predicate constraint element count - Determines the number of active 32-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement all destination vector elements. The   results are   saturated to the   32-bit    unsigned integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001010....110011..........
        ze  imm4    DUtternZdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

uqincb - unsigned saturating increment scalar by multiple of 8-bit predicate constraint element count - Determines the number of active 8-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment the   scalar destination. The   result is   saturated to the       general-purpose register's   unsigned integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001000010....111101..........
        ze fimm4    DUtternRdn  
000001000011....111101..........
        ze fimm4    DUtternRdn  
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

uqincd (scalar) - unsigned saturating increment scalar by multiple of 64-bit predicate constraint element count - Determines the number of active 64-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment the   scalar destination. The   result is   saturated to the       general-purpose register's   unsigned integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001110....111101..........
        ze fimm4    DUtternRdn  
000001001111....111101..........
        ze fimm4    DUtternRdn  
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

uqincd (vector) - unsigned saturating increment vector by multiple of 64-bit predicate constraint element count - Determines the number of active 64-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment all destination vector elements. The   results are   saturated to the   64-bit    unsigned integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001110....110001..........
        ze  imm4    DUtternZdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

uqinch (scalar) - unsigned saturating increment scalar by multiple of 16-bit predicate constraint element count - Determines the number of active 16-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment the   scalar destination. The   result is   saturated to the       general-purpose register's   unsigned integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001000110....111101..........
        ze fimm4    DUtternRdn  
000001000111....111101..........
        ze fimm4    DUtternRdn  
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

uqinch (vector) - unsigned saturating increment vector by multiple of 16-bit predicate constraint element count - Determines the number of active 16-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment all destination vector elements. The   results are   saturated to the   16-bit    unsigned integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001000110....110001..........
        ze  imm4    DUtternZdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

uqincp (scalar) - unsigned saturating increment scalar by count of true predicate elements - Counts the number of true elements in the source predicate and then uses the result to increment the   scalar destination. The   result is   saturated to the       general-purpose register's   unsigned integer range.
00100101..1010011000100.........
        ze    DU     fpPm  Rdn  
00100101..1010011000110.........
        ze    DU     fpPm  Rdn  
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <Pm>:name of the source scalable predicate register, encoded in the "Pm" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

uqincp (vector) - unsigned saturating increment vector by count of true predicate elements - Counts the number of true elements in the source predicate and then uses the result to increment all destination vector elements. The   results are   saturated to the   element    unsigned integer range. The predicate size specifier may be omitted in assembler    source code, but this is deprecated and will be    prohibited in a future release of the architecture.
00100101..1010011000000.........
        ze    DU     pcPm  Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Pm>:name of the source scalable predicate register, encoded in the "Pm" field.

uqincw (scalar) - unsigned saturating increment scalar by multiple of 32-bit predicate constraint element count - Determines the number of active 32-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment the   scalar destination. The   result is   saturated to the       general-purpose register's   unsigned integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001010....111101..........
        ze fimm4    DUtternRdn  
000001001011....111101..........
        ze fimm4    DUtternRdn  
 <Wdn>:32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.
 <Xdn>:64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

uqincw (vector) - unsigned saturating increment vector by multiple of 32-bit predicate constraint element count - Determines the number of active 32-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment all destination vector elements. The   results are   saturated to the   32-bit    unsigned integer range. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
000001001010....110001..........
        ze  imm4    DUtternZdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <pattern>
 pattern | <pattern>
 00000 | POW2
 00001 | VL1
 00010 | VL2
 00011 | VL3
 00100 | VL4
 00101 | VL5
 00110 | VL6
 00111 | VL7
 01000 | VL8
 01001 | VL16
 01010 | VL32
 01011 | VL64
 01100 | VL128
 01101 | VL256
 0111x | #uimm5
 1xx00 | #uimm5
 1x0x1 | #uimm5
 1x010 | #uimm5
 101x1 | #uimm5
 10110 | #uimm5
 11101 | MUL4
 11110 | MUL3
 11111 | ALL
 <imm>:immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

uqrshl - unsigned saturating rounding shift left by vector (predicated) - Shift active unsigned elements of the first source vector by corresponding elements of the second source vector and destructively place the rounded results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Each result element is saturated to the  N-bit element's unsigned integer range 0 to (2N)-1. Inactive elements in the destination vector register remain unmodified.
01000100..001011100.............
        ze  QRNU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uqrshlr - unsigned saturating rounding shift left reversed vectors (predicated) - Shift active unsigned elements of the second source vector by corresponding elements of the first source vector and destructively place the rounded results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Each result element is saturated to the  N-bit element's unsigned integer range 0 to (2N)-1. Inactive elements in the destination vector register remain unmodified.
01000100..001111100.............
        ze  QRNU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uqrshrn - unsigned saturating rounding shift right narrow by immediate and interleave - Shift right by an immediate value, the unsigned integer value in each element of the group of two source vectors and place the two-way interleaved rounded results in the half-width destination elements. Each result element is saturated to the half-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to 16. is unpredicated.
010001011011....001110....0.....
         h limm4  pUR Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Zn1>:name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.
 <Zn2>:name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.
 <const>:immediate shift amount, in the range 1 to 16, encoded in the "imm4" field.

uqrshrnb - unsigned saturating rounding shift right narrow by immediate (bottom) - Shift each unsigned integer value in the source vector elements right by an immediate value, and place the rounded results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. Each result element is saturated to the half-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....001110..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

uqrshrnt - unsigned saturating rounding shift right narrow by immediate (top) - Shift each unsigned integer value in the source vector elements by an immediate value, and place the rounded results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. Each result element is saturated to the half-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....001111..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

uqshl (immediate) - unsigned saturating shift left by immediate - Shift left by immediate each active unsigned element of the source vector, and destructively place the results in the corresponding elements of the source vector. Each result element is saturated to the  N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 0 to number of bits per element minus 1. Inactive elements in the destination vector register remain unmodified.
00000100..000111100.............
        zh  pcLU   Pg zlmm3Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>:immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3".

uqshl (vectors) - unsigned saturating shift left by vector (predicated) - Shift active unsigned elements of the first source vector by corresponding elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Each result element is saturated to the  N-bit element's unsigned integer range 0 to (2N)-1. Inactive elements in the destination vector register remain unmodified.
01000100..001001100.............
        ze  QRNU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uqshlr - unsigned saturating shift left reversed vectors (predicated) - Shift active unsigned elements of the second source vector by corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Each result element is saturated to the  N-bit element's unsigned integer range 0 to (2N)-1. Inactive elements in the destination vector register remain unmodified.
01000100..001101100.............
        ze  QRNU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uqshrnb - unsigned saturating shift right narrow by immediate (bottom) - Shift each unsigned integer value in the source vector elements right by an immediate value, and place the truncated results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. Each result element is saturated to the half-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....001100..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

uqshrnt - unsigned saturating shift right narrow by immediate (top) - Shift each unsigned integer value in the source vector elements right by an immediate value, and place the truncated results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. Each result element is saturated to the half-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
010001010.1.....001101..........
         h zlmm3  pURTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

uqsub (immediate) - unsigned saturating subtract immediate (unpredicated) - Unsigned saturating subtract an unsigned immediate from each element of the source vector, and destructively place the results in the corresponding elements of the  source vector. Each result element is saturated to the  N-bit element's unsigned integer range 0 to (2N)-1. is unpredicated. The immediate is an unsigned value in the range 0 to 255, and for element widths of 16 bits or higher it may also be a positive multiple of 256 in the range 256 to 65280. The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<uimm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".
00100101..10011111..............
        ze     U  himm8    Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <imm>:Is an unsigned immediate in the range 0 to 255, encoded in the "imm8" field.
 <shift>
 sh | <shift>
 0 | LSL #0
 1 | LSL #8

uqsub (vectors, predicated) - unsigned saturating subtraction (predicated) - Subtract active unsigned elements of the second source vector from corresponding unsigned elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Each result element is saturated to the  N-bit element's unsigned integer range 0 to (2N)-1. Inactive elements in the destination vector register remain unmodified.
01000100..011011100.............
        ze   pSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uqsub (vectors, unpredicated) - unsigned saturating subtract vectors (unpredicated) - Unsigned saturating subtract all elements of the second source vector from corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. Each result element is saturated to the  N-bit element's unsigned integer range 0 to (2N)-1. is unpredicated.
00000100..1.....000111..........
        ze Zm        UZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uqsubr - unsigned saturating subtraction reversed vectors (predicated) - Subtract active unsigned elements of the first source vector from corresponding unsigned elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. Each result element is saturated to the  N-bit element's unsigned integer range 0 to (2N)-1. Inactive elements in the destination vector register remain unmodified.
01000100..011111100.............
        ze   pSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uqxtnb - unsigned saturating extract narrow (bottom) - Saturate the unsigned integer value in each source element to half the original source element width, and place the results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero.
010001010.1..000010010..........
         h zl       UTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 10 | H
 0 | 11 | RESERVED
 1 | 00 | S
 1 | 01 | RESERVED
 1 | 1x | RESERVED
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 10 | S
 0 | 11 | RESERVED
 1 | 00 | D
 1 | 01 | RESERVED
 1 | 1x | RESERVED

uqxtnt - unsigned saturating extract narrow (top) - Saturate the unsigned integer value in each source element to half the original source element width, and place the results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged.
010001010.1..000010011..........
         h zl       UTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 10 | H
 0 | 11 | RESERVED
 1 | 00 | S
 1 | 01 | RESERVED
 1 | 1x | RESERVED
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 10 | S
 0 | 11 | RESERVED
 1 | 00 | D
 1 | 01 | RESERVED
 1 | 1x | RESERVED

urecpe - unsigned reciprocal estimate (predicated) - Find the approximate reciprocal of each active unsigned element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
01000100..000000101.............
        ze  Q Zp   Pg Zn   Zd   
01000100..000010101.............
        ze  Q Zp   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

urhadd - unsigned rounding halving addition - Add active unsigned elements of the first source vector to corresponding unsigned elements of the second source vector, shift right one bit, and destructively place the rounded results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
01000100..010101100.............
        ze   RSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

urshl - unsigned rounding shift left by vector (predicated) - Shift active unsigned elements of the first source vector by corresponding elements of the second source vector and destructively place the rounded results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Inactive elements in the destination vector register remain unmodified.
01000100..000011100.............
        ze  QRNU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

urshlr - unsigned rounding shift left reversed vectors (predicated) - Shift active unsigned elements of the second source vector by corresponding elements of the first source vector and destructively place the rounded results in the corresponding elements of the first source vector. A positive shift amount performs a left shift, otherwise a right shift by the negated shift amount is performed. Inactive elements in the destination vector register remain unmodified.
01000100..000111100.............
        ze  QRNU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

urshr - unsigned rounding shift right by immediate - Shift right by immediate each active unsigned element of the source vector, and destructively place the rounded results in the corresponding elements of the source vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. Inactive elements in the destination vector register remain unmodified.
00000100..001101100.............
        zh  pcLU   Pg zlmm3Zdn  
 <Zdn>:name of the source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

ursqrte - unsigned reciprocal square root estimate (predicated) - Find the approximate reciprocal square root of each active unsigned element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
01000100..000001101.............
        ze  Q Zp   Pg Zn   Zd   
01000100..000011101.............
        ze  Q Zp   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

ursra - unsigned rounding shift right and accumulate (immediate) - Shift right by immediate each unsigned element of the source vector, inserting zeroes, and add the rounded intermediate result destructively to the corresponding elements of the addend vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
01000101..0.....111011..........
        zh zlmm3    RUZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

usdot (indexed) - unsigned by signed integer indexed dot product - The unsigned by signed integer indexed dot product instruction computes the dot product of a group of four unsigned 8-bit  integer values held in each 32-bit  element of the first source vector multiplied by a group of four signed 8-bit  integer values in an indexed 32-bit  element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit  element of the destination vector. The groups within the second source vector are specified using an immediate index which selects the same group position within each 128-bit vector segment.  The index range is from 0 to 3. is unpredicated. ID_AA64ZFR0_EL1.I8MM indicates whether this instruction is implemented.
01000100101.....000110..........
        ze i2Zm      UZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
 <imm>:immediate index of a 32-bit group of four 8-bit values within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.

usdot (vectors) - unsigned by signed integer dot product - The unsigned by signed integer  dot product instruction computes the dot product of a group of four unsigned 8-bit  integer values held in each 32-bit  element of the first source vector multiplied by a group of four signed 8-bit  integer values in the corresponding 32-bit  element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit  element of the destination vector. is unpredicated. ID_AA64ZFR0_EL1.I8MM indicates whether this instruction is implemented.
01000100100.....011110..........
        ze Zm         Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

ushllb - unsigned shift left long by immediate (bottom) - Shift left by immediate each even-numbered unsigned element of the source vector, and place the results in the overlapping double-width elements of the destination vector. The immediate shift amount is an unsigned value in the range 0 to number of bits per element minus 1. is unpredicated.
010001010.0.....101010..........
         h zlmm3    UTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <const>:immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3".

ushllt - unsigned shift left long by immediate (top) - Shift left by immediate each odd-numbered unsigned element of the source vector, and place the results in the overlapping double-width elements of the destination vector. The immediate shift amount is an unsigned value in the range 0 to number of bits per element minus 1. is unpredicated.
010001010.0.....101011..........
         h zlmm3    UTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 tszh | tszl | <T>
 0 | 00 | RESERVED
 0 | 01 | H
 0 | 1x | S
 1 | xx | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 tszh | tszl | <Tb>
 0 | 00 | RESERVED
 0 | 01 | B
 0 | 1x | H
 1 | xx | S
 <const>:immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3".

usmmla - unsigned by signed integer matrix multiply-accumulate - The unsigned by signed integer matrix multiply-accumulate instruction multiplies the 2×8 matrix of unsigned 8-bit integer values held in each 128-bit segment of the first source vector by the 8×2 matrix of signed 8-bit integer values in the corresponding segment of the second source vector. The resulting 2×2 widened 32-bit integer matrix product is then destructively added to the 32-bit integer matrix accumulator held in the corresponding segment of the addend and destination vector. This is equivalent to performing an 8-way dot product per destination element. is unpredicated. ID_AA64ZFR0_EL1.I8MM indicates whether this instruction is implemented. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
01000101100.....100110..........
        ns Zm         Zn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

usqadd - unsigned saturating addition of signed value - Add active signed elements of the source vector to the corresponding unsigned elements of the addend vector, and destructively place the results in the corresponding elements of the addend vector.  Each result element is saturated to the  N-bit element's unsigned integer range 0 to (2N)-1. Inactive elements in the destination vector register remain unmodified.
01000100..011101100.............
        ze   pSU   Pg Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

usra - unsigned shift right and accumulate (immediate) - Shift right by immediate each unsigned element of the source vector, inserting zeroes, and add the truncated intermediate result destructively to the corresponding elements of the addend vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. is unpredicated.
01000101..0.....111001..........
        zh zlmm3    RUZn   Zda  
 <Zda>:name of the third source and destination scalable vector register, encoded in the "Zda" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

usublb - unsigned subtract long (bottom) - Subtract the even-numbered unsigned elements of the second source vector from the corresponding unsigned elements of the first source vector, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....000110..........
        ze Zm     pSUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

usublt - unsigned subtract long (top) - Subtract the odd-numbered unsigned elements of the second source vector from the corresponding unsigned elements of the first source vector, and place the results in the overlapping double-width elements of the destination vector. is unpredicated.
01000101..0.....000111..........
        ze Zm     pSUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

usubwb - unsigned subtract wide (bottom) - Subtract the even-numbered unsigned elements of the second source vector from the overlapping double-width elements of the first source vector and place the results in the corresponding double-width elements of the destination vector.  is unpredicated.
01000101..0.....010110..........
        ze Zm      SUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S

usubwt - unsigned subtract wide (top) - Subtract the odd-numbered unsigned elements of the second source vector from the overlapping double-width elements of the first source vector and place the results in the corresponding double-width elements of the destination vector.  is unpredicated. is unpredicated.
01000101..0.....010111..........
        ze Zm      SUTZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S

uunpkhi, uunpklo - unsigned unpack and extend half of vector - Unpack elements from the lowest or highest half of the source vector and then zero-extend them to place in elements of twice their size within the destination vector.  is unpredicated.
00000101..110011001110..........
        ze    UH      Zn   Zd   
00000101..110010001110..........
        ze    UH      Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.
 <Tb>
 size | <Tb>
 00 | RESERVED
 01 | B
 10 | H
 11 | S

uxtb, uxth, uxtw - unsigned byte / halfword / word extend (predicated) - Zero-extend the least-significant sub-element  of each active element of the source vector, and place the results in the corresponding elements of the destination vector.  Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
00000100..010001101.............
        ze M   U   Pg Zn   Zd   
00000100..000001101.............
        ze M   U   Pg Zn   Zd   
00000100..010011101.............
        ze M   U   Pg Zn   Zd   
00000100..000011101.............
        ze M   U   Pg Zn   Zd   
00000100..010101101.............
        ze M   U   Pg Zn   Zd   
00000100..000101101.............
        ze M   U   Pg Zn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | RESERVED
 01 | H
 10 | S
 11 | D
 <T>
 size<0> | <T>
 0 | S
 1 | D
 <Pg>:name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 <Zn>:name of the source scalable vector register, encoded in the "Zn" field.

uzp1, uzp2 (predicates) - concatenate even or odd elements from two predicates - Concatenate adjacent even or odd-numbered elements from the  first and second source predicates and place in elements of the destination predicate.  is unpredicated.
00000101..10....0100100....0....
        ze  Pm     pcH Pn   Pd  
00000101..10....0100110....0....
        ze  Pm     pcH Pn   Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

uzp1, uzp2 (vectors) - concatenate even or odd elements from two vectors - Concatenate adjacent even or odd-numbered elements from the  first and second source vectors and place in elements of the destination vector.  is unpredicated. Note: UZP1 is equivalent to truncating and packing each element from two source vectors into a single destination vector with elements of half the size. The 128-bit element variant requires that the Effective SVE vector length is at least 256 bits. ID_AA64ZFR0_EL1.F64MM indicates whether the 128-bit element variant is implemented. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
00000101..1.....011010..........
        ze Zm        HZn   Zd   
00000101101.....000010..........
           Zm      pcHZn   Zd   
00000101..1.....011011..........
        ze Zm        HZn   Zd   
00000101101.....000011..........
           Zm      pcHZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uzpq1 - concatenate even elements within each pair of quadword vector segments - Concatenate adjacent even-numbered elements from the corresponding 128-bit vector segments of the first and second source vectors and place in elements of the corresponding destination vector segment. is unpredicated.
01000100..0.....111010..........
        ze Zm        HZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

uzpq2 - concatenate odd elements within each pair of quadword vector segments - Concatenate adjacent odd-numbered elements from the corresponding 128-bit vector segments of the first and second source vectors and place in elements of the corresponding destination vector segment. is unpredicated.
01000100..0.....111011..........
        ze Zm        HZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

whilege (predicate as counter) - while decrementing signed scalar greater than or equal to scalar (predicate-as-counter) - Generate a predicate for a group of two or four vectors that starting from the highest numbered element of the group is true while the decrementing value of the first, signed  scalar operand is greater than or equal to the second scalar operand and false thereafter down to the lowest numbered element of the group. If the second scalar operand is equal to the minimum signed  integer value then a condition which includes an equality test can never fail and the result will be an all-true predicate. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size. The predicate result is placed in the predicate destination register using the predicate-as-counter encoding. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....01.000.....10...
        ze Rm     l UtRn    qPNd
 <PNd>:name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.
 <vl>
 vl | <vl>
 0 | VLx2
 1 | VLx4

whilege (predicate pair) - while decrementing signed scalar greater than or equal to scalar (pair of predicates) - Generate a pair of predicates that starting from the highest numbered element of the pair is true while the decrementing value of the first, signed  scalar operand is greater than or equal to the second scalar operand and false thereafter down to the lowest numbered element of the pair. If the second scalar operand is equal to the minimum signed  integer value then a condition which includes an equality test can never fail and the result will be an all-true predicate. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The lower-numbered elements are placed in the first predicate destination register, and the higher-numbered elements in the second predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....010100.....1...0
        ze Rm       UtRn    Pd q
 <Pd1>:name of the first destination scalable predicate register, encoded as "Pd" times 2.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pd2>:name of the second destination scalable predicate register, encoded as "Pd" times 2 plus 1.
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.

whilege (predicate) - while decrementing signed scalar greater than or equal to scalar - Generate a predicate that starting from the highest numbered element is true while the decrementing value of the first, signed  scalar operand is greater than or equal to the second scalar operand and false thereafter down to the lowest numbered element. If the second scalar operand is equal to the minimum signed  integer value then a condition which includes an equality test can never fail and the result will be an all-true predicate. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The predicate result is placed in the predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....000.00.....0....
        ze Rm      fUtRn   qPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <R>
 sf | <R>
 0 | W
 1 | X
 <n>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field.
 <m>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

whilegt (predicate as counter) - while decrementing signed scalar greater than scalar (predicate-as-counter) - Generate a predicate for a group of two or four vectors that starting from the highest numbered element of the group is true while the decrementing value of the first, signed  scalar operand is greater than the second scalar operand and false thereafter down to the lowest numbered element of the group. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size. The predicate result is placed in the predicate destination register using the predicate-as-counter encoding. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....01.000.....11...
        ze Rm     l UtRn    qPNd
 <PNd>:name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.
 <vl>
 vl | <vl>
 0 | VLx2
 1 | VLx4

whilegt (predicate pair) - while decrementing signed scalar greater than scalar (pair of predicates) - Generate a pair of predicates that starting from the highest numbered element of the pair is true while the decrementing value of the first, signed  scalar operand is greater than the second scalar operand and false thereafter down to the lowest numbered element of the pair. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The lower-numbered elements are placed in the first predicate destination register, and the higher-numbered elements in the second predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....010100.....1...1
        ze Rm       UtRn    Pd q
 <Pd1>:name of the first destination scalable predicate register, encoded as "Pd" times 2.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pd2>:name of the second destination scalable predicate register, encoded as "Pd" times 2 plus 1.
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.

whilegt (predicate) - while decrementing signed scalar greater than scalar - Generate a predicate that starting from the highest numbered element is true while the decrementing value of the first, signed  scalar operand is greater than the second scalar operand and false thereafter down to the lowest numbered element. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The predicate result is placed in the predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....000.00.....1....
        ze Rm      fUtRn   qPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <R>
 sf | <R>
 0 | W
 1 | X
 <n>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field.
 <m>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

whilehi (predicate as counter) - while decrementing unsigned scalar higher than scalar (predicate-as-counter) - Generate a predicate for a group of two or four vectors that starting from the highest numbered element of the group is true while the decrementing value of the first, unsigned  scalar operand is higher than the second scalar operand and false thereafter down to the lowest numbered element of the group. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size. The predicate result is placed in the predicate destination register using the predicate-as-counter encoding. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....01.010.....11...
        ze Rm     l UtRn    qPNd
 <PNd>:name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.
 <vl>
 vl | <vl>
 0 | VLx2
 1 | VLx4

whilehi (predicate pair) - while decrementing unsigned scalar higher than scalar (pair of predicates) - Generate a pair of predicates that starting from the highest numbered element of the pair is true while the decrementing value of the first, unsigned  scalar operand is higher than the second scalar operand and false thereafter down to the lowest numbered element of the pair. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The lower-numbered elements are placed in the first predicate destination register, and the higher-numbered elements in the second predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....010110.....1...1
        ze Rm       UtRn    Pd q
 <Pd1>:name of the first destination scalable predicate register, encoded as "Pd" times 2.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pd2>:name of the second destination scalable predicate register, encoded as "Pd" times 2 plus 1.
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.

whilehi (predicate) - while decrementing unsigned scalar higher than scalar - Generate a predicate that starting from the highest numbered element is true while the decrementing value of the first, unsigned  scalar operand is higher than the second scalar operand and false thereafter down to the lowest numbered element. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The predicate result is placed in the predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....000.10.....1....
        ze Rm      fUtRn   qPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <R>
 sf | <R>
 0 | W
 1 | X
 <n>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field.
 <m>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

whilehs (predicate as counter) - while decrementing unsigned scalar higher or same as scalar (predicate-as-counter) - Generate a predicate for a group of two or four vectors that starting from the highest numbered element of the group is true while the decrementing value of the first, unsigned  scalar operand is higher or same as the second scalar operand and false thereafter down to the lowest numbered element of the group. If the second scalar operand is equal to the minimum unsigned  integer value then a condition which includes an equality test can never fail and the result will be an all-true predicate. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size. The predicate result is placed in the predicate destination register using the predicate-as-counter encoding. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....01.010.....10...
        ze Rm     l UtRn    qPNd
 <PNd>:name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.
 <vl>
 vl | <vl>
 0 | VLx2
 1 | VLx4

whilehs (predicate pair) - while decrementing unsigned scalar higher or same as scalar (pair of predicates) - Generate a pair of predicates that starting from the highest numbered element of the pair is true while the decrementing value of the first, unsigned  scalar operand is higher or same as the second scalar operand and false thereafter down to the lowest numbered element of the pair. If the second scalar operand is equal to the minimum unsigned  integer value then a condition which includes an equality test can never fail and the result will be an all-true predicate. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The lower-numbered elements are placed in the first predicate destination register, and the higher-numbered elements in the second predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....010110.....1...0
        ze Rm       UtRn    Pd q
 <Pd1>:name of the first destination scalable predicate register, encoded as "Pd" times 2.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pd2>:name of the second destination scalable predicate register, encoded as "Pd" times 2 plus 1.
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.

whilehs (predicate) - while decrementing unsigned scalar higher or same as scalar - Generate a predicate that starting from the highest numbered element is true while the decrementing value of the first, unsigned  scalar operand is higher or same as the second scalar operand and false thereafter down to the lowest numbered element. If the second scalar operand is equal to the minimum unsigned  integer value then a condition which includes an equality test can never fail and the result will be an all-true predicate. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The predicate result is placed in the predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....000.10.....0....
        ze Rm      fUtRn   qPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <R>
 sf | <R>
 0 | W
 1 | X
 <n>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field.
 <m>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

whilele (predicate as counter) - while incrementing signed scalar less than or equal to scalar (predicate-as-counter) - Generate a predicate for a group of two or four vectors that starting from the lowest numbered element of the group is true while the incrementing value of the first, signed  scalar operand is less than or equal to the second scalar operand and false thereafter up to the highest numbered element of the group. If the second scalar operand is equal to the maximum signed  integer value then a condition which includes an equality test can never fail and the result will be an all-true predicate. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is incremented by one for each destination predicate element, irrespective of the predicate result element size. The predicate result is placed in the predicate destination register using the predicate-as-counter encoding. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....01.001.....11...
        ze Rm     l UtRn    qPNd
 <PNd>:name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.
 <vl>
 vl | <vl>
 0 | VLx2
 1 | VLx4

whilele (predicate pair) - while incrementing signed scalar less than or equal to scalar (pair of predicates) - Generate a pair of predicates that starting from the lowest numbered element of the pair is true while the incrementing value of the first, signed  scalar operand is less than or equal to the second scalar operand and false thereafter up to the highest numbered element of the pair. If the second scalar operand is equal to the maximum signed  integer value then a condition which includes an equality test can never fail and the result will be an all-true predicate. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is incremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The lower-numbered elements are placed in the first predicate destination register, and the higher-numbered elements in the second predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....010101.....1...1
        ze Rm       UtRn    Pd q
 <Pd1>:name of the first destination scalable predicate register, encoded as "Pd" times 2.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pd2>:name of the second destination scalable predicate register, encoded as "Pd" times 2 plus 1.
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.

whilele (predicate) - while incrementing signed scalar less than or equal to scalar - Generate a predicate that starting from the lowest numbered element is true while the incrementing value of the first, signed  scalar operand is less than or equal to the second scalar operand and false thereafter up to the highest numbered element. If the second scalar operand is equal to the maximum signed  integer value then a condition which includes an equality test can never fail and the result will be an all-true predicate. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is incremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The predicate result is placed in the predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....000.01.....1....
        ze Rm      fUtRn   qPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <R>
 sf | <R>
 0 | W
 1 | X
 <n>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field.
 <m>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

whilelo (predicate as counter) - while incrementing unsigned scalar lower than scalar (predicate-as-counter) - Generate a predicate for a group of two or four vectors that starting from the lowest numbered element of the group is true while the incrementing value of the first, unsigned  scalar operand is lower than the second scalar operand and false thereafter up to the highest numbered element of the group. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is incremented by one for each destination predicate element, irrespective of the predicate result element size. The predicate result is placed in the predicate destination register using the predicate-as-counter encoding. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....01.011.....10...
        ze Rm     l UtRn    qPNd
 <PNd>:name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.
 <vl>
 vl | <vl>
 0 | VLx2
 1 | VLx4

whilelo (predicate pair) - while incrementing unsigned scalar lower than scalar (pair of predicates) - Generate a pair of predicates that starting from the lowest numbered element of the pair is true while the incrementing value of the first, unsigned  scalar operand is lower than the second scalar operand and false thereafter up to the highest numbered element of the pair. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is incremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The lower-numbered elements are placed in the first predicate destination register, and the higher-numbered elements in the second predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....010111.....1...0
        ze Rm       UtRn    Pd q
 <Pd1>:name of the first destination scalable predicate register, encoded as "Pd" times 2.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pd2>:name of the second destination scalable predicate register, encoded as "Pd" times 2 plus 1.
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.

whilelo (predicate) - while incrementing unsigned scalar lower than scalar - Generate a predicate that starting from the lowest numbered element is true while the incrementing value of the first, unsigned  scalar operand is lower than the second scalar operand and false thereafter up to the highest numbered element. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is incremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The predicate result is placed in the predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....000.11.....0....
        ze Rm      fUtRn   qPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <R>
 sf | <R>
 0 | W
 1 | X
 <n>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field.
 <m>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

whilels (predicate as counter) - while incrementing unsigned scalar lower or same as scalar (predicate-as-counter) - Generate a predicate for a group of two or four vectors that starting from the lowest numbered element of the group is true while the incrementing value of the first, unsigned  scalar operand is lower or same as the second scalar operand and false thereafter up to the highest numbered element of the group. If the second scalar operand is equal to the maximum unsigned  integer value then a condition which includes an equality test can never fail and the result will be an all-true predicate. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is incremented by one for each destination predicate element, irrespective of the predicate result element size. The predicate result is placed in the predicate destination register using the predicate-as-counter encoding. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....01.011.....11...
        ze Rm     l UtRn    qPNd
 <PNd>:name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.
 <vl>
 vl | <vl>
 0 | VLx2
 1 | VLx4

whilels (predicate pair) - while incrementing unsigned scalar lower or same as scalar (pair of predicates) - Generate a pair of predicates that starting from the lowest numbered element of the pair is true while the incrementing value of the first, unsigned  scalar operand is lower or same as the second scalar operand and false thereafter up to the highest numbered element of the pair. If the second scalar operand is equal to the maximum unsigned  integer value then a condition which includes an equality test can never fail and the result will be an all-true predicate. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is incremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The lower-numbered elements are placed in the first predicate destination register, and the higher-numbered elements in the second predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....010111.....1...1
        ze Rm       UtRn    Pd q
 <Pd1>:name of the first destination scalable predicate register, encoded as "Pd" times 2.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pd2>:name of the second destination scalable predicate register, encoded as "Pd" times 2 plus 1.
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.

whilels (predicate) - while incrementing unsigned scalar lower or same as scalar - Generate a predicate that starting from the lowest numbered element is true while the incrementing value of the first, unsigned  scalar operand is lower or same as the second scalar operand and false thereafter up to the highest numbered element. If the second scalar operand is equal to the maximum unsigned  integer value then a condition which includes an equality test can never fail and the result will be an all-true predicate. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is incremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The predicate result is placed in the predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....000.11.....1....
        ze Rm      fUtRn   qPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <R>
 sf | <R>
 0 | W
 1 | X
 <n>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field.
 <m>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

whilelt (predicate as counter) - while incrementing signed scalar less than scalar (predicate-as-counter) - Generate a predicate for a group of two or four vectors that starting from the lowest numbered element of the group is true while the incrementing value of the first, signed  scalar operand is less than the second scalar operand and false thereafter up to the highest numbered element of the group. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is incremented by one for each destination predicate element, irrespective of the predicate result element size. The predicate result is placed in the predicate destination register using the predicate-as-counter encoding. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....01.001.....10...
        ze Rm     l UtRn    qPNd
 <PNd>:name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.
 <vl>
 vl | <vl>
 0 | VLx2
 1 | VLx4

whilelt (predicate pair) - while incrementing signed scalar less than scalar (pair of predicates) - Generate a pair of predicates that starting from the lowest numbered element of the pair is true while the incrementing value of the first, signed  scalar operand is less than the second scalar operand and false thereafter up to the highest numbered element of the pair. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is incremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The lower-numbered elements are placed in the first predicate destination register, and the higher-numbered elements in the second predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....010101.....1...0
        ze Rm       UtRn    Pd q
 <Pd1>:name of the first destination scalable predicate register, encoded as "Pd" times 2.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pd2>:name of the second destination scalable predicate register, encoded as "Pd" times 2 plus 1.
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.

whilelt (predicate) - while incrementing signed scalar less than scalar - Generate a predicate that starting from the lowest numbered element is true while the incrementing value of the first, signed  scalar operand is less than the second scalar operand and false thereafter up to the highest numbered element. The full  width of the scalar operands is significant for the purposes of comparison, and the full width  first operand is incremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The predicate result is placed in the predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....000.01.....0....
        ze Rm      fUtRn   qPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <R>
 sf | <R>
 0 | W
 1 | X
 <n>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field.
 <m>:number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

whilerw - while free of read-after-write conflicts - checks two addresses for a conflict or overlap between address ranges of the form [addr,addr+VL÷8), where VL is the accessible vector length in bits, that could result in a loop-carried   dependency through memory due to the use of these addresses by contiguous load and store instructions within the same iteration of a loop.  Generate a predicate whose elements are true while the addresses cannot conflict within the same iteration, and false thereafter.  Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....001100.....1....
        ze Rm         Rn   wPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.

whilewr - while free of write-after-read/write conflicts - checks two addresses for a conflict or overlap between address ranges of the form [addr,addr+VL÷8), where VL is the accessible vector length in bits, that could result in a loop-carried   dependency through memory due to the use of these addresses by contiguous load and store instructions within the same iteration of a loop.  Generate a predicate whose elements are true while the addresses cannot conflict within the same iteration, and false thereafter.  Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
00100101..1.....001100.....0....
        ze Rm         Rn   wPd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Xn>:64-bit name of the first source general-purpose register, encoded in the "Rn" field.
 <Xm>:64-bit name of the second source general-purpose register, encoded in the "Rm" field.

wrffr - write the first-fault register - Read the source predicate register and place in the first-fault register (FFR). is intended to restore a saved FFR and is not recommended for general use by applications. requires that the source predicate contains a monotonic predicate value, in which starting from bit 0 there are zero or more 1 bits, followed only by 0 bits in any remaining bit positions. If the source is not a monotonic predicate value, then the resulting value in the FFR will be UNPREDICTABLE. It is not possible to generate a non-monotonic value in FFR when using SETFFR followed by first-fault or non-fault loads. is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
00100101001010001001000....00000
        pc             Pn       
 <Pn>:name of the source scalable predicate register, encoded in the "Pn" field.

xar - bitwise exclusive-or and rotate right by immediate - Bitwise exclusive-OR the corresponding elements of the first and second source vectors, then rotate each result element right by an immediate amount. The final results are destructively placed in the corresponding elements of the destination and first source vector. is unpredicated.
00000100..1.....001101..........
        zh zlmm3      Zm   Zdn  
 <Zdn>:name of the first source and destination scalable vector register, encoded in the "Zdn" field.
 <T>
 tszh | tszl | <T>
 00 | 00 | RESERVED
 00 | 01 | B
 00 | 1x | H
 01 | xx | S
 1x | xx | D
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.
 <const>:immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

zip1, zip2 (predicates) - interleave elements from two half predicates - Interleave alternating  elements from the lowest or highest halves of the first and second source predicates and place in elements of the destination predicate.  is unpredicated.
00000101..10....0100010....0....
        ze  Pm     pcH Pn   Pd  
00000101..10....0100000....0....
        ze  Pm     pcH Pn   Pd  
 <Pd>:name of the destination scalable predicate register, encoded in the "Pd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Pn>:name of the first source scalable predicate register, encoded in the "Pn" field.
 <Pm>:name of the second source scalable predicate register, encoded in the "Pm" field.

zip1, zip2 (vectors) - interleave elements from two half vectors - Interleave alternating  elements from the lowest or highest halves of the first and second source vectors and place in elements of the destination vector.  is unpredicated. The 128-bit element variant requires that the Effective SVE vector length is at least 256 bits. ID_AA64ZFR0_EL1.F64MM indicates whether the 128-bit element variant is implemented. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
00000101..1.....011001..........
        ze Zm        HZn   Zd   
00000101101.....000001..........
           Zm      pcHZn   Zd   
00000101..1.....011000..........
        ze Zm        HZn   Zd   
00000101101.....000000..........
           Zm      pcHZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

zipq1 - interleave elements from low halves of each pair of quadword vector segments - Interleave alternating elements from low halves of the corresponding 128-bit vector segments of the first and second source vectors and place in elements of the corresponding destination vector segment. is unpredicated.
01000100..0.....111000..........
        ze Zm        HZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.

zipq2 - interleave elements from high halves of each pair of quadword vector segments - Interleave alternating elements from high halves of the corresponding 128-bit vector segments of the first and second source vectors and place in elements of the corresponding destination vector segment. is unpredicated.
01000100..0.....111001..........
        ze Zm        HZn   Zd   
 <Zd>:name of the destination scalable vector register, encoded in the "Zd" field.
 <T>
 size | <T>
 00 | B
 01 | H
 10 | S
 11 | D
 <Zn>:name of the first source scalable vector register, encoded in the "Zn" field.
 <Zm>:name of the second source scalable vector register, encoded in the "Zm" field.